LTE DL Channel Encoder v2.

0
XMP023 April 24, 2009 Product Brief

Introduction
The Xilinx® LTE DL Channel Encoder core provides • CRC
designers with an LTE Downlink Channel Encoding ♦ 24-bit CRC applied to DL-SCH, PCH, and
block for the 3GPP TS 36.212 v8.4.0 Multiplexing and MCH transport blocks
channel coding specification. ♦ 16-bit CRC applied to BCH and DCI code
blocks (with additional scrambling on parity
bits)
Features
• Segmentation
• Available for Virtex®-6, Virtex-5, Virtex-4,
♦ Code block segmentation applied to DL-SCH,
Spartan®-6, and Spartan-3A DSP FPGAs
PCH, and MCH transport blocks (i.e., data that
• Channel coding for 3GPP TS 36.212 supports: are turbo encoded), with an additional 24-bit
DL-SCH, PCH, MCH, BCH, CFI, HI, and DCI CRC computed on each code-block (in cases
• Bit-accurate C model available where segmentation produces more than one
code-block).
• Fully optimized for speed and area
• Encoding
• Fully synchronous design using a single clock
♦ Turbo code applied to DL-SCH, PCH, and
• For use with the Xilinx CORE Generator™ v11.1
MCH data
and higher
♦ Convolutional code applied to BCH and DCI
data (single code block)
Overview • Rate Matching
The LTE DL Channel Encoder core provides a channel ♦ Applied on a code-block basis to DL-SCH,
encoding solution for the 3GPP 36.212 specification. PCH, MCH, BCH, and DCI data. This function
Figure 1 and Figure 2 illustrate the main blocks in the performs appropriate puncturing according to
LTE encoding chain for the two main channel types that the AMC parameters and redundancy version.
are supported by the core. The architecture has been • Control Format Indicator Generation
designed to provide efficient use of the FPGA while ♦ The HI or CFI coded outputs are generated
also offering a low bandwidth processor interface to according to the type indicated from the
reduce system-level overhead. Timing critical opera- control signaling from the MAC layer.
tions are performed by the FPGA.
The interface to the core can be easily attached to any
bus-based system. The memory mapped interface
allows for simple integration and validation within the
system.
Data is processed sequentially on a transport block
basis for each of the two main channel types, where the
term “transport block“ is used to describe a block of
data originating from the MAC layer. Specific process-
ing is applied depending on the type of input block,
which is indicated as part of the control signaling pro-
vided by the MAC layer. The following functions are
supported by the core:

© 2008-2009 Xilinx, Inc., XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United States and
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Product Brief
LTE DL Channel Encoder v2.0

Control and Broadcast Channel Processing

X-Ref Target - Figure 1

PBCH and PDCCH

CRC16 Tail Biting

and Convolution Rate Match
Masking Encoder CCH

ds699_01_072508

Figure 1: Downlink Channel Processing for BCH and DCI - CCH Channel Stream

Shared, Paging, and Multicast Channel Processing

X-Ref Target - Figure 2

PDSCH, PMCH, and PPCH

CRC24 Segment Turbo Encoder Rate Match SCH

ds699_02_072508

Figure 2: Downlink Channel Processing for DL-SCH, PCH and MCH - SCH Channel Stream

Support
Xilinx provides technical support at www.xilinx.com/support for this LogiCORE product when used
as described in the product documentation. Xilinx cannot guarantee timing, functionality, or support of
product if implemented in devices that are not defined in the documentation, if customized beyond
that allowed in the product documentation, or if changes are made to any section of the design labeled
DO NOT MODIFY.
Refer to the IP Release Notes Guide (XTP025) for further information on this core. There will be a link
to all the DSP IP and then to the relevant core being designed with.
For each core, there is a master Answer Record that contains the Release Notes and Known Issues list
for the core being used. The following information is listed for each version of the core:
• New Features
• Bug Fixes
• Known Issues

Ordering Information
The LTE DL Channel Encoder core is provided under the SignOnce IP Site License and can be generated
using the Xilinx® CORE Generator v11.1 or higher. The CORE Generator software is shipped with Xil-
inx ISE® Foundation™ Series Development software.
To access the full functionality of the core, including simulation and FPGA bitstream generation, a full
license must be obtained from Xilinx. For more information, visit the LTE DL Channel Encoder product
page.

2 www.xilinx.com XMP023 April 24, 2009

Product Brief
 LTE DL Channel Encoder v2.0

Contact your local Xilinx sales representative for pricing and availability of additional Xilinx® Logi-
CORE modules and software. Information about additional Xilinx® LogiCORE modules is available on
the Xilinx IP Center.
France Telecom, for itself and certain other parties, claims certain intellectual property rights covering
Turbo Codes technology, and has decided to license these rights under a licensing program called the
Turbo Codes Licensing Program. Supply of this IP core does not convey a license nor imply any right to
use any Turbo Codes patents owned by France Telecom, TDF or GET. Please contact France Telecom for
information about its Turbo Codes Licensing Program at the following address: France Telecom R&D,
VAT/TURBOCODES 38, rue du Général Leclerc, 92794 Issy Moulineaux, Cedex 9, France.

Revision History
The following table shows the revision history for this document:

Date Version Description of Revisions

09/19/08 1.0 Initial Xilinx release.
04/24/09 1.5 Added support for Spartan-6 and Virtex-6 device families.

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Product Brief