## Are you sure?

This action might not be possible to undo. Are you sure you want to continue?

Set No. 1

II B.Tech I Semester Supplementary Examinations, February 2007 SWITCHING THEORY AND LOGIC DESIGN ( Common to Electrical & Electronic Engineering, Electronics & Communication Engineering, Computer Science & Engineering, Electronics & Instrumentation Engineering, Bio-Medical Engineering, Information Technology, Electronics & Control Engineering, Computer Science & Systems Engineering, Electronics & Telematics and Electronics & Computer Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. (a) Write the following binary numbers in signed 1’s complement form and signed 2’s complement form using 16 bit registers. i. ii. iii. iv. +1001010 -11110000 -11001100.1 +100000011.111

(b) Perform N1+N2,N1+(-N2) for the following 8 bit numbers expressed in a 2’s complement representation. Verify your answers by using decimal addition and subtraction i. N1=00110010, N2=11111101 ii. N1=10001110, N2=00001101 [10+6] 2. (a) i. Given AB + AB = C, Show that AC + AC = B. ii. (A + B)(A + C)(B + D)(+CD) ;simplify

(b) Deﬁne the connective * for the two valued variables A, B, and C as follows A ∗ B = AB + A B Let C = A*B, Determine which of the following is valid i. A=B*C ii. B=A*C iii. A*B*C=1 [8+8] 3. (a) Derive Boolean expression for a 2 input Ex-NOR gate to realize with two input NOR gates, without using complemented variables and draw the circuit. (b) Redraw the given circuit (ﬁgure1) after simpliﬁcation. [8+8] 4. (a) Design a BCD to excess-3 code converter using 1 of 2

Code No: RR210203

Set No. 1

Figure 1: i. ROM ii. PAL (b) Show how a 4 x 16 decoder can be constructed with two 3 x 8 decoders. [5+5+6] 5. (a) Distinguish between combinational logic and sequential logic (b) Draw the schematic circuit of an edge triggered J-K - Flip-Flop with “active low preset” and “active low clear” using NAND gates and explain its operations with the help of Truth-Table. [6+10] 6. Design a synchronous modulo 10 up down counter .Use T ﬂip ﬂops for synthesis. [16] 7. (a) Convert the following Mealy machine into a corresponding Moore machine: PS A B C D NS,Z X=0 X=1 C,0 B,0 A,1 D,0 B,1 A,1 D,1 C,0

(b) Design the circuit for the above table. [8+8] 8. Design a half adder and half subtractor circuit using (a) multiplexer and registers (b) one ﬂipﬂop per state..Draw the state diagram and convert it to ASM block and tablulate its state table. [8+8] ⋆⋆⋆⋆⋆

2 of 2

Code No: RR210203

Set No. 2

II B.Tech I Semester Supplementary Examinations, February 2007 SWITCHING THEORY AND LOGIC DESIGN ( Common to Electrical & Electronic Engineering, Electronics & Communication Engineering, Computer Science & Engineering, Electronics & Instrumentation Engineering, Bio-Medical Engineering, Information Technology, Electronics & Control Engineering, Computer Science & Systems Engineering, Electronics & Telematics and Electronics & Computer Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. (a) Consider the following four codes. Code A 0001 0010 0100 1000 Code B Code C 000 01011 001 01100 011 1 10010 010 10101 110 111 101 100 Code D 000000 001111 3 110011

2

4

Which of the following properties is satisﬁed by each of the above codes? i. ii. iii. iv. v. Detects single errors Detects double errors Detects triple errors Corrects single errors Corrects double errors Corrects singe and detects double errors. [8+8] 2. (a) Simplify the function using Karnaugh map method F (A,B,C,D) = (4,5,7,12,14,15)+ d(3,8,10). (b) Give three possible ways to express the function F = A B D + A B C D + ABD + ABCD with eight or less literals. [8+8]

(b) Add the following decimal number 109 and 876 in BCD and Excess-3 forms.

3. Using the tabular method, obtain the prime implicants of a four- input single-output function f(w,x,y,z) = m(0,2,4,5,6,7,8,9,10,11,13). Reduce the prime-implicant table and ﬁnd the minimal cover of f. [16] 4. (a) Implement the following function using a multiplexer of proper size. F(w,x,y,z) = m(0, 1, 2, 3, 4, 9, 13, 14, 15) 1 of 2

Code No: RR210203

Set No. 2

[8+8]

(b) Draw the circuit diagram of a 4 bit look a head carry generator circuit.

5. (a) Deﬁne a sequential system and how does it diﬀer from a combinational system? (b) Draw the schematic circuit of a negative edge-trigger S-R-Flip-Flop with “active low preset” and “active low clear” inputs using NAND gates and explain its operation with the help of Truth-Table [6+10] 6. A sequential circuit has three D ﬂip-ﬂops, A, B, C and one input x.. It is described by the following ﬂip-ﬂops input functions DA = (BC 1 + B 1 C)x + (BC + B 1 C 1 )x1 DB=A DC=B (a) Derive the state stable for the circuit. (b) Draw two state diagrams one for x=0, and the other for x=1. [16] 7. (a) Distinguish between Mealy and Moore machines (b) Convert the following Mealy machine into a corresponding Moore machine: PS A B C D E NS,Z X-0 X=1 B,0 E,0 E,0 D,0 D,1 A,0 C,1 E,0 B,0 D,0 [6+10] 8. Design a half adder and half subtractor circuit using (a) multiplexer and registers (b) one ﬂipﬂop per state..Draw the state diagram and convert it to ASM block and tablulate its state table. [8+8] ⋆⋆⋆⋆⋆

2 of 2

Code No: RR210203

Set No. 3

II B.Tech I Semester Supplementary Examinations, February 2007 SWITCHING THEORY AND LOGIC DESIGN ( Common to Electrical & Electronic Engineering, Electronics & Communication Engineering, Computer Science & Engineering, Electronics & Instrumentation Engineering, Bio-Medical Engineering, Information Technology, Electronics & Control Engineering, Computer Science & Systems Engineering, Electronics & Telematics and Electronics & Computer Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. (a) Write the following binary numbers in signed 1’s complement form and signed 2’s complement form using 16 bit registers. i. ii. iii. iv. +1001010 -11110000 -11001100.1 +100000011.111

(b) Perform N1+N2,N1+(-N2) for the following 8 bit numbers expressed in a 2’s complement representation. Verify your answers by using decimal addition and subtraction i. N1=00110010, N2=11111101 ii. N1=10001110, N2=00001101 [10+6] 2. (a) Minimize the function using Karnaugh map method f (A,B,C,D) = (1,3,5,8,9,11) + Sd (2,13). (b) Simply the given expressions using Boolean theorem i. f= AB + A C + C + AD + A B C+ABC. ii. (x + xyz + (x + xyz)(x + x yz) iii. a + ab + a bc + abcd + ......... [8+8] 3. Using the Quine-Mc Cluskey method of tabular reduction ,minimize the given combinational single - output function f(w,x,y,z) = m(0,1,5,7,810,14,15) [16] 4. (a) Give the circuit implementation of a 4 - bit carry look-ahead adder. (b) Give the implementation of a 2 -bit magnitude comparator. (c) Bring out the diﬀerences among a PAL and PLA. [6+6+4] m

1 of 2

Code No: RR210203

Set No. 3

5. (a) Deﬁne a sequential system and how does it diﬀer from a combinational system (b) Augment an S-R Flip-Flop with two AND gates to form a J-K-Flip-Flop and explain its operations with the help of Truth-Table [6+10] 6. A sequential circuit has three D ﬂip-ﬂops, A, B, C and one input x.. It is described by the following ﬂip-ﬂops input functions DA = (BC 1 + B 1 C)x + (BC + B 1 C 1 )x1 DB=A DC=B (a) Derive the state stable for the circuit. (b) Draw two state diagrams one for x=0, and the other for x=1. [16] 7. (a) Deﬁne state equivalance and machine equivalance with reference to sequential machines. (b) Reduce the number of states in the following state table and tabulate the reduce state table and give proper assignment. PS A B C D E F G H NS,Z X-0 X=1 F,0 B,0 D,0 C,0 F,0 E,0 G,1 A,0 D,0 C,0 F,1 B,1 G,0 H,0 G,1 A,0 [4+12] 8. Construct an ASM block that has 3 input variables (A,B,C), 4 output (W,X,Y,Z) and 2 exit paths. For this block, output Z is always 1, and W is 1 if A & B are both 1. If C=1 & A=0, Y=1 and exit path 1 is taken. If C=0 or A=1, X=1 and exit path 2 is taken. Realize the above using the One ﬂip ﬂop per state. [16] ⋆⋆⋆⋆⋆

2 of 2

Code No: RR210203

Set No. 4

II B.Tech I Semester Supplementary Examinations, February 2007 SWITCHING THEORY AND LOGIC DESIGN ( Common to Electrical & Electronic Engineering, Electronics & Communication Engineering, Computer Science & Engineering, Electronics & Instrumentation Engineering, Bio-Medical Engineering, Information Technology, Electronics & Control Engineering, Computer Science & Systems Engineering, Electronics & Telematics and Electronics & Computer Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. (a) Write the following binary numbers in signed 1’s complement form and signed 2’s complement form using 16 bit registers. i. ii. iii. iv. +1001010 -11110000 -11001100.1 +100000011.111

(b) Perform N1+N2,N1+(-N2) for the following 8 bit numbers expressed in a 2’s complement representation. Verify your answers by using decimal addition and subtraction i. N1=00110010, N2=11111101 ii. N1=10001110, N2=00001101 [10+6] 2. (a) Simplify the function using Karnaugh map method F (A,B,C,D) = (4,5,7,12,14,15)+ d(3,8,10). (b) Give three possible ways to express the function F = A B D + A B C D + ABD + ABCD with eight or less literals. [8+8]

3. (a) Derive Boolean expression for a 2input Ex-OR gate to realize with 2 input NAND gates without using complemented variables and draw the circuit. (b) Redraw the given circuit in (ﬁgure1)after simpliﬁcation .

Figure 1: [8+8] 1 of 3

Code No: RR210203 4. (a) Write a note on ‘high-speed adders’

Set No. 4

(b) Give the logic realization of a two −bit word comporator to compare two words A=A1 A0 and B = B1 B0 in binary code. (c) Implement the following function using eight−to-one mux F(x, y, z) = m(0, 2, 3, 5) [4+8+4]

5. (a) Analyze the circuit(ﬁgure2) given and prove it is equivalent to a T ﬂip ﬂop.

Figure 2: (b) Draw the circuit diagram of a mod-10 ripple counter and explain its operation with the aid of output state timing diagram. [6+10] 6. Design a counter which could count either in mod 8 straight binary or in mod 8 cyclic code based on a control signal. [16] 7. What are the conditions for the two machines are to be equivalent? For the machine given below, ﬁnd the equivalence partition and a corresponding reduced machine in standard form: PS A B C D E F G NS,Z X=0 X=1 F,0 B,1 G,0 A,1 B,0 C,1 C,0 B,1 D,0 A,1 E,1 F,1 E,1 G,1 [16] 8. Design a half adder and half subtractor circuit using (a) multiplexer and registers (b) one ﬂipﬂop per state..Draw the state diagram and convert it to ASM block and tablulate its state table. [8+8] 2 of 3

Code No: RR210203 ⋆⋆⋆⋆⋆

Set No. 4

3 of 3

- 16-1 Mux Using 8-1 Mux, 4-1mux , And 2-1 Mux
- 8086 Instruction Set
- AIUB-B.Sc. EEE Course List
- Manual de Entrada_salidas Analogicas Plc
- ME_Mtech-2Sem090311072659
- Lec1.pdf
- Dry Contact Installation
- Mult Logic Opt
- Handbook COE (UNITEN)
- Number System operation& code Digital System
- Rr210203 Switching Theory and Logic Design
- ElecHW1_Papa.docx
- Digitization of collections for the National Jukebox website
- Computer Division
- Notification for KRCL Recruitment 2016
- Capacitive Multi Button Configurations
- Burst contention resolving mechanisms for Optical Burst Switching
- 2-Lecture Notes Lesson3 5
- Documentgkkkkkk
- Hradware developer or Engineer or Forensics Tech or Designer
- Control Tutorials for MATLAB and Simulink - Extras_ Simulink Basics Tutorial - Block Libraries
- CS6211 Digital manual.pdf
- 2074_Syllabus_Fall_2013-3
- Advt MT External
- Design Lab Report
- DESIGN OF 8 BIT ALU USING MICROWIND 3.1
- Multiplexer,decoder and encoder.pdf
- bsnl
- Electronic Engineer or Electronic Technician
- Osmania University B.E. Examinations Time Table 2011-2012 2012

- 43-Mca-Or-Design and Analysis of Algorithm
- r5 401 Mba Strategic Management Set1
- Rr322305 Immunology
- r05320305 Design of Machine Members II
- r05320205 Switchgear and Protection
- r5 401 Mba Strategic Management Set1
- 41 Mca Nr Software Engineering
- r5 402 Mba Management of Technology Set1
- r6 43 Mca Data Warehousing and Mining Set1
- 41 Mca or Software Engineering
- 41 Mca Nr Software Engineering
- r05320403 Microwave Engineering
- 43-Mca-Or-Design and Analysis of Algorithm
- r6 42 Mca Advanced Java Programming Set1
- 42 Mca Nr Programming in Java
- r5 408 Mba Decision Support Systems Set1
- Nr 305 Mba Retailing Management Set1
- r5 410 Mba Management of Change Set1
- Nr 302 Mba Cost and Management Accounting Set1
- Nr 31 Mca Database Management Systems
- Or 34 Mca Management Information Systems
- r5 305 Mba Retailing Management Set1
- r5 304 Mba Enterprise Resource Planning
- Or 32 Mcacomputer Communication Networks
- Nr-35-Mca-Design and Analysis of Algorithm
- r6 47 Mca Distributed Operating Systems Set1
- r6 43 Mca Data Warehousing and Mining Set1
- r6 34 Mca Management Information Systems Set1
- r6 33 Mca Unix Networks Programming Set1
- r6 48 Mca Mobile Computing Set1

Read Free for 30 Days

Cancel anytime.

Close Dialog## Are you sure?

This action might not be possible to undo. Are you sure you want to continue?

Loading