Code No: RR310401

Set No. 1

III B.Tech I Semester Supplementary Examinations, February 2007 DIGITAL IC APPLICATIONS (Electronics & Communication Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. (a) Explain the effect of floating inputs on CMOS gate? (b) Explain how a CMOS device is destroyed? (c) What is the difference between transmission time and propagation delay? Explain these two parameters with reference to CMOS logic? [4+4+8] 2. (a) Explain the following terms with reference to TTL gate? i. ii. iii. iv. Logic levels DC Noise margin Low-state unit load High-state fanout

[4+4]

(b) Design a transistor circuit of 2-input ECL NOR gate? Explain the operation with the help of function table? [8] 3. Explain with example the syntax and the function of the following VHDL statements (a) Process statement (b) If, else and elseif statements (c) Case statement (d) Loop statement [4x4=16]

4. Design a priority encoder that can handle 32 requests? Use 74×148 and required discrete gates? Provide the truth table and explain the operation? [4+4+4+4] 5. (a) Design a full adder using two half adders? Write VHDL data flow program for the above implementation? [4+4] (b) Design a 4×4 combinational multiplexer and write the corresponding VHDL program? [4+4] 6. (a) Design a switch debouncer circuit using 74×109 IC? Explain the operation using timing diagram? (b) Discuss the logic circuit of 74×377 register? Write a VHDL program for the above logic? [8+8] 7. (a) Draw the logic diagram of 74x194 and explain the operation?

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Code No: RR310401

Set No. 1

(b) Design a serial binary adder? Develop the VHDL program for simulating serial binary adder? [8+8] 8. (a) Discuss the operation of IOB in XC4000 FPGA with a neat sketch? (b) Realize the logic function performed by 74x381 with ROM? ⋆⋆⋆⋆⋆ [8+8]

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Code No: RR310401

Set No. 2

III B.Tech I Semester Supplementary Examinations, February 2007 DIGITAL IC APPLICATIONS (Electronics & Communication Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. (a) Design a 4-input CMOS OR-AND-INVERT gate? Explain the circuit with the help of logic diagram and function table? [4+4] (b) Explain the following terms with reference to CMOS logic? i. ii. iii. iv. Logic Levels DC Noise margin Power supply rails Propagation delay

[4+4]

2. (a) Design a transistor circuit of 2-input ECL NOR gate? Explain the operation with the help of function table? (b) A single pull-up resistor to +5V is used to provide a constant-1 logic source to 15 different 74LS00 inputs. What is the maximum value of this resistor? How much high state DC noise margin can be provided in this case? [8+8] 3. (a) Explain with example the syntax and the function of the following VHDL statements? i. Process statement ii. Case statement [4+4]

(b) Design the logic circuit and write a data-flow style VHDL program for the following function? F (Q) = ΣA,B,C,D (0,2,5,7,8,10,13,15) + d(11) [8] 4. (a) Design a 16-bit comparator using 74×85s? (b) Write a behavioral VHDL program to compare 16-bit signed and unsigned integers? [8+8] 5. (a) Show the logic diagram of 74×283 binary adder? Explain the principle of generating sum and carry at every stage using the logic diagram? [4+4] (b) Design a 24-bit group ripple adder using 74×283 Ics? [8]

6. (a) Distinguish between latch and flip-flop? Show the logic diagram for both? Explain the operation with the help of function table? [4+4] (b) Design a conversion circuit to convert a T flip-flop to J-K flip-flop? [8]

7. (a) Define clock skew? Explain how clock skew leads to incorrect outputs in synchronous circuits? Design one logic circuit that minimizes clock skew? 1 of 2

Code No: RR310401

Set No. 2

(b) Design an 8-bit serial-in and parallel-out shift register with flip-flops? Explain the operation with the help of timing waveforms? [8+8] 8. (a) Explain how a 4x4 binary multiplier can be designed using 256x8 ROM? (b) Discuss how PROM, EPROM and EEPROM technologies differ from each other? [8+8] ⋆⋆⋆⋆⋆

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Code No: RR310401

Set No. 3

III B.Tech I Semester Supplementary Examinations, February 2007 DIGITAL IC APPLICATIONS (Electronics & Communication Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. (a) Draw the logic diagram equivalent to the internal structure of an 8-input CMOS NAND gate? Explain the operation with the help of function table? (b) Compare HC, HCT, VHC and VHCT CMOS logic families with the help of input specifications with VCC from 4.5V to 5.5V? [10+6] 2. (a) What is the necessity of separate interfacing circuit to connect CMOS gate to TTL gate? Draw the interface circuit and explain the operation? (b) Draw the circuit diagram of basic CMS gate and explain the operation?[10+6] 3. (a) Explain with example the syntax and the function of the following VHDL statements? i. Process statement ii. Case statement [4+4]

(b) Design the logic circuit and write a data-flow style VHDL program for the following function? F (Q) = ΣA,B,C,D (0,2,5,7,8,10,13,15) + d(11) [8] 4. Design a 10 to 4 encoder with inputs 1- out of 10 code and outputs in BCD? Provide the data flow style VHDL program? [8+8=16] 5. (a) Design a full subtractor with logic gates and write VHDL data flow program for the implementation of the above subtractor? (b) Using the above subtractor design a 8-bit ripple subtractor and write the corresponding VHDL program? [8+8] 6. (a) Discuss the logic circuit of 74×377 register? Write a VHDL program for the above logic? (b) Design a modulo-50 counter using 74×163 ICs? [8+8]

7. (a) Design an 8-bit serial-in and serial-out shift register? Write the data-flow style VHDL program for this shift register? (b) Define clock skew? Explain how clock skew leads to incorrect outputs in synchronous circuits? Design one logic circuit that minimizes clock skew? [8+8] 8. (a) Explain how a 4x4 binary multiplier can be designed using 256x8 ROM?

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Code No: RR310401

Set No. 3

(b) With a neat diagram explain the general architecture of CPLD? Discuss the key features of Xilinx XC9500 CPLD family? [8+8] ⋆⋆⋆⋆⋆

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Code No: RR310401

Set No. 4

III B.Tech I Semester Supplementary Examinations, February 2007 DIGITAL IC APPLICATIONS (Electronics & Communication Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. (a) What are the parameters that are necessary to define the electrical characteristics of CMOS circuits? Mention the typical values of a CMOS NAND gate? (b) Design a 4-input CMOS AND-OR-INVERT gate? Draw the logic diagram and function table? [8+8] 2. (a) Explain the following terms with reference to TTL gate? i. ii. iii. iv. Logic levels DC Noise margin Low-state unit load High-state fanout

[4+4]

(b) List out TTL families and compare them with reference to propagation delay, power consumption, speed-power product and low level input current? [8] 3. (a) Explain data-flow design elements of VHDL? (b) Write a data-flow style VHDL program for the following functions? F(S) = A ⊕B⊕CI F(CO ) = AB + ACI + BCI 4. (a) Write a VHDL program for 74×245? (b) Design a 16-bit comparator using 74×85 Ics? [8+8] [8]

[4+4]

5. (a) Design a full adder using two half adders? Write VHDL data flow program for the above implementation? [4+4] (b) Design a 4×4 combinational multiplexer and write the corresponding VHDL program? [4+4] 6. (a) With the help of logic diagram explain the function of PAL16R6? (b) Design a switch debouncer circuit using 74×109 IC? Explain the operation using timing diagram? [8+8] 7. (a) Draw the logic diagram of 74x194 and explain the operation? (b) Design a serial binary adder? Develop the VHDL program for simulating serial binary adder? [8+8] 8. (a) Explain the internal structure of 64Kx1 DRAM? With the help of timing waveforms discuss DRAM access? 1 of 2

Code No: RR310401

Set No. 4
[8+8] ⋆⋆⋆⋆⋆

(b) Explain XC4000 programmable interconnect structure?

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