Code No: RR410506

Set No. 1

IV B.Tech I Semester Supplementary Examinations, February 2007 FAULT TOLERANT SYSTEMS ( Common to Computer Science & Engineering and Electronics & Computer Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. (a) How does a feedback briding fault leads the circuit into oscillation. What are the conditions? [4+4] (b) What are temporary faults? Differentiate between Transient faults and intermittent faults. Which one is preferrable? [3+2+2+1] 2. (a) A circuit realizes the function. Z=X1 X4 +X2 X3 +X1 X4 Using Boolean Difference method find the test vectors for SA0, SA1 faults on all input lines of the circuit. (b) What are the different properties of Boolean differences? Explain [5+5+6] 3. (a) Construct a seven-bit error correcting code to represent the decimal digit by augmenting the Excess-3 code and by using add-1 parity check. (b) Design a redundant circuit for f = a ⊕ b [9+7] 4. (a) What is the mechanism adopted in COPRA a fault Tolerant system. Explain in detail. (b) What is meant by Time redundancy? Explain. [4+4+4+4] 5. (a) What is the need for self checking circuits (b) Design a totally self checking checker by using reddy’s partition method for 2out of 5 code. [6+10] 6. Explain in detail about fail-safe sequential circuits design with an example. 7. Write a short notes an (a) (b) (c) (d) Controllability Observability Positive unate function Syndrom relations of all types of terminating gates. [16]

[4x4=16]

8. (a) Discuss the sequential circuit design using nonscan techniques. (b) i. What is meant by Enhanced controllability? ii. How is a sequential circuit modified for the above sequential circuit and enhanced controllability? [6+4+6] ⋆⋆⋆⋆⋆ 1 of 1

Code No: RR410506

Set No. 2

IV B.Tech I Semester Supplementary Examinations, February 2007 FAULT TOLERANT SYSTEMS ( Common to Computer Science & Engineering and Electronics & Computer Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. (a) Distinguish between failures, and faults Explain [2+2]

(b) Explain the different modeling schemes of faults that generally come across in digital circuits. [3x2=6] (c) Explain the following terms with respect to digital circuits with suitable examples. i. Fault diagnosis. ii. Fault detection test set. iii. Test vector generation. 2. (a) Distinguish between fault detection and fault location

[3x2=6] [2+2]

(b) Illustrate the principles involved in fault table method of test generation using the figure1 given below.Verify the above test vector, generated, with the help of D-algorithm for C SAO fault. [12]

Figure 1: 3. (a) Analyze the circuit shown in fig2 below for static hazards. Redesign the circuit so that it becomes hazard free? [4+4] (b) Explain the concept of sift out modular redundancy scheme. 4. With an example explain : (a) software redundancy. (b) time redundancy. 5. (a) What is the need for self checking circuits (b) Design a totally self checking checker by using reddy’s partition method for 2out of 5 code. [6+10] 1 of 2 [8+8] [8]

Code No: RR410506

Set No. 2

Figure 2: 6. Explain in detail about fail-safe sequential circuits design with an example. [16]

7. Explain the technique for designing minimally testable network which produces a circuit which can be tested by three tests only.Modify the function f = A BC +A B C into a circuit which has only three tests. [10+6] 8. (a) Draw the logic diagram of Hazard-free polarity hold latch, and explain with the help of flow table & excitation table. [2+2+2] (b) Draw the logic diagram of shift register latch and explain its principle. Using above latch. [3+7] ⋆⋆⋆⋆⋆

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Code No: RR410506

Set No. 3

IV B.Tech I Semester Supplementary Examinations, February 2007 FAULT TOLERANT SYSTEMS ( Common to Computer Science & Engineering and Electronics & Computer Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. Define and derive the following terms in a system. (a) MTTR (b) Hazard rate functions. 2. (a) What is a tree like circuit. Give properties of tree like circuits. (b) For the given tree like circuit find the complete test set using path sensitizing method as show in figure1. [3+5+8] [2+6] [2+6]

Figure 1: 3. (a) Explain fail soft-operation. [4]

(b) Explain the 5 MR reconfiguration mechanism and also explain how it care tolerate single, double and Trible faults in a given system. [3x4=12] 4. With an example explain : (a) software redundancy. (b) time redundancy. 5. (a) What is the need for self checking circuits (b) Design a totally self checking checker by using reddy’s partition method for 2out of 5 code. [6+10] 6. Explain in detail about fail-safe sequential circuits design with an example. [16] [8+8]

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Code No: RR410506

Set No. 3

7. (a) Prove that five tests are sufficient to detect all faults in a combinational logic circuit by inserting addition control logic to the following function, obtain the test pattern. f=(A,B,C,D)=AB+BC+BD (b) Obtain the ten sequences denoted as P = {xo x1 ......xa } from the basic module of the above circuit and get the compatable pair from the set P. [8+8] 8. (a) Draw the logic diagram of Built-in Logic Block Observer. (b) Discuss BILBO based BIST architecture. ⋆⋆⋆⋆⋆ [8+8]

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Code No: RR410506

Set No. 4

IV B.Tech I Semester Supplementary Examinations, February 2007 FAULT TOLERANT SYSTEMS ( Common to Computer Science & Engineering and Electronics & Computer Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. (a) Distinguish between failures, and faults Explain [2+2]

(b) Explain the different modeling schemes of faults that generally come across in digital circuits. [3x2=6] (c) Explain the following terms with respect to digital circuits with suitable examples. i. Fault diagnosis. ii. Fault detection test set. iii. Test vector generation. 2. (a) What are the goals of Design for testability? (b) Distinguish between ditermenistic test pattern generation and probabilitstic test pattern generation methods. [6+5+5] 3. (a) With an example explain sift out modular redundancy technique. (b) With an example explain self-purging redundancy. [8+8]

[3x2=6]

4. (a) What is the goal of “pluibus” system used in ARPA network. Explain its working. (b) What is ment by fail soft operation? What should a system have to achieve the capability of fail soft operation. [4+4+4+4] 5. Design a totally (a) self-checking circuit for m out of n codes by translating the code to 1 out of 2. (b) Verify it for 3 out of 5 code. [8+8]

6. (a) Explain the design consideration of self checking PLA considering stray faults with suitable example. (b) How do you implement strong fault service for the functional PLA. [8+8]

7. (a) Prove that five tests are sufficient to detect all faults in a combinational logic circuit by inserting addition control logic to the following function, obtain the test pattern. f=(A,B,C,D)=AB+BC+BD (b) Obtain the ten sequences denoted as P = {xo x1 ......xa } from the basic module of the above circuit and get the compatable pair from the set P. [8+8] 1 of 2

Code No: RR410506

Set No. 4

8. Explain observability enhancement with neat diagram with suitable examples. [4+2+10]

⋆⋆⋆⋆⋆

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