You are on page 1of 2

M.E. (Hons.

) Microelectronics
Course Description Core Courses

MEL G611 IC Fabrication Technology

[3 2 !

Material properties; crystal growth and doping; diffusion; oxidation; epitaxy; ion implantation; deposition of films using CVD, LPCVD and sputtering techniques; wet and dry etching and cleaning; lithographic process; device and circuit fa rication; process modeling and simulation! MEL G621 "L#I Design [3 2 !

"ntroduction to #M$% and CM$% circuits; #M$% and CM$% processing technology; CM$% circuits and logic design; circuit characteri&ation and performance estimation; structured design and testing; sym olic layout systems; CM$% su system design; system case studies! MEL G631 $hysics an% Mo%elling o& Microelectronic De'ices [3 2 !

Physics and properties of semiconductor ' a review; pn (unction diode; ipolar transistor; metal semiconductor contacts; )*+, and M+%*+,; M$%*+, and scaling; CCD and photonic devices! MEL G632 (nalog IC Design [3 2 !

-asic concepts; -"CM$% process and technology; current and voltage sources; differential and operational amplifiers; multipliers and modulators; phase'loc. techniques; D'to'/ and /' to'D converters; micropower circuits; high voltage circuits; radiation resistant circuits; filter design considerations! MEL G6)2 "L#I (rchitectures [2 2 )!

$verview of C"%C processor architectures; "nstruction set architecture of C"%C processor; hardware flow'charting methods; implementing microprocessor logic from hard'ware flowcharts; 0"%C instruction set architecture; Pipelined execution of 0"%C instructions; pipeline execution unit design; control ha&ards; design of memory hierarchy!

Elective Courses
C# G 3 *econ&igurable Co+puting [ !

Overview of Programmable Logics. FPGA fabric architectures. Logic Elements and Switch Networks. esign and S!nthesis of "ombinational and Se#uential Elements. Placement and $outing. Pi%elining and other esign &ethodologies. Fine'grained and "oarse'Grained FPGAs. Static and !namic $econfiguration. Partitioning. (ardware)Software Portioning and Partial Evaluation. S!stolic Architectures. EEE F)3) Digital #ignal $rocessing [3!

"ntroduction; design of analog filters; design of digital filters1 2""0 and *"03; structures for the

random signals and random processes. linear least square estimator.elihood method. pipeline execution unit design. models and model classification.are #o&t. negative resistance oscillator. dielectric resonator oscillators. 6igh speed arithmetic circuits design.alman'filter. Logical effort in circuit design. asic concepts in 0* circuit design. /rchitecture mapping. D%P algorithms for different applications! EEE G 1.echniques in 0. numerical identification methods! EEE G626 -ar%. memory and array structures.'Parallel prefix computation. active 0* components1 various 0* diodes and transistors and their circuit models. Cloc.are Co/Design [)! *P5/ and /%"C ased design. application of 0* electronics in modern systems.s.. 4iener filters. Pipelined execution of 0"%C instructions. classical methods of identification of impulse response and transfer function models. simultaneous state and parameter estimation of extended .ing! 6ardware %oftware partitioning and scheduling. 0"%C instruction set architecture. low noise mixers. 0* amplifier design1 low power. some field of applications. "nput7output circuits design. issues in analog circuit testing and testa ility! MEL G6)2 "L#I (rchitectures [2 2 )! $verview of C"%C processor architectures. microwave transmitters and receivers! EEE G 12 E+be%%e% #yste+ Design [3 1 )! "ntroduction to em edded systems. test generation for sequential logic. low noise and road and amplifiers. em edded architectures1 /rchitectures and programming of microcontrollers and D%Ps! +m edded applications and technologies. D%P processor architecture. minimum variance algorithm. control ha&ards. phase noise! 0* Mixers1 -alanced mixers. *P5/ technology. Design of VL%" systems! MEL G626 "L#I Test an% Testability [ ! *ault models and types. Co'simulation. synthesis and verifications. non'linear identification. design for testa ility. Digital -"CM$% circuits. signals and system timing''Digital phase loc. "nstruction set architecture of C"%C processor. noise in 0* circuits. the identification pro lem. introduction to software and hardware co'design! EEE G613 (%'ance% Digital #ignal $rocessing [ ! 0eview of stochastic processes. hardware flow'charting methods. design of memory hierarchy! . linear estimation and prediction.reali&ation of digital filters. /%"C technology. 64'%4 "nterfaces and 0e'configura le computing! MEL G623 (%'ance% "L#I Design [ ! Deep su micron device ehavior and models. Low power VL%" circuits' /dia atic logic circuits. quasi lineari&ation. automated test generation for com inational logic. "nterconnect modeling for parasitic estimation. 0* oscillator design. Low'Power . methods. implementing microprocessor logic from hard'ware flowcharts.ed loop design. matching and iasing networ. Multi threshold circuits. stochastic approximation method and maximum li. structured D*. +m edded %ystems $n'chip networ. need for adding testa ility logic. /dhoc D*. test generation for delay fault. model learning techniques. power issues in system design. *F Microelectronics [ ! "ntroduction.