You are on page 1of 4

VLSI LAB PROGRAMS

S.No List of Main Programs Exercise Programs to be done 1. Realize Half adder using Two input NAND Gates in structural model 2. Realize Half adder using Two input NOR Gates in structural Model . Realize Half su!tractor using Two input NAND Gates in structural model ". Realize Half su!tractor using Two input NOR Gates in structural model #. Design Half adder using wit$..select and %$en..else wit$ &ropagation dela's. (. Design Half su!tractor using wit$..select and %$en..else wit$ &ropagation dela's. ). Design Half su!tractor using case..w$en and Half adder using if .. t$en statements 1. Realize *ull adder using Two input NAND Gates in structural model 2. Realize *ull adder using Two input NOR Gates in structural model . Realize *ull adder using Two Half adders in structural model ". Design *ull adder using w$en..else statement wit$ a Transport dela' of "++ ns. #. Design *ull adder using if,t$en statement 1. Design *ull su!tractor using Two input NAND gates in structural model 2. Design *ull su!tractor using Two input NOR gates in structural model . Design *ull su!tractor using wit$,select statement wit$ a propagation dela' of ++ ns ". Design *ull su!tractor using case..w$en statement #. Design t$e circuit in page No. #- of .a! manual in structural model (. Design t$e circuit in page No. (+ of .a! manual in structural model 1. Design 1 !it comparator using NAND gates in structural model 2. Design 1 !it comparator using NOR gates in structural model . Design 1 !it comparator using wit$..select statement ". Design 1 !it comparator using nested if statement #. Design " !it comparator using structural model (. Design " !it comparator using for,generate statement in structural model

1.

a!f Adder " S#btractor

$.

%#!! Adder

&.

%#!! S#btractor

'.

(om)arator

*.

M#!ti)!exer

+.

,ecoder

-.

N. Bit adder

/.

Priorit0 encoder

). Design " !it comparator using if,generate statement in structural model 1. Design " /1 Mu0 using case..w$en and w$en..else statements 2. Design 1/1 Mu0 using wit$,select and nested if statements. . Design "/1 Mu0 wit$ logic gates using structural model ". Design Half adder using two 2/1 Mu0es in structural model #. Design Half su!tractor using two 2 / 1 Mu0es in structural model (. Design *ull adder wit$ two " / 1 Mu0es in structural model ). Design *ull su!tractor wit$ two " / 1 Mu0es in structural model 1. Design t$e following 2O& e0pression using 1 / 1 Mu0 *3A45464D7 8 9 324 4#4)4-41141 41#7 -. Design 1(/1 Mu0 wit$ two 1/1 Mu0es 1. Design /1 Decoder using nested if and w$en..else statements 2. Design "/1( Decoder wit$ /1 decoders using structural model . Design 2/" decoder using case..w$en statement ". :mplement "/1( decoder using 2/" decoders in structural model #. Design 2/" decoder and "/1( decoder using .;T approac$ (. Design "/1( decoder wit$ logic gates using structural model ). Design t$e following 2O& e0pression using /1 decoder *3A45464D7 8 9 31424 4#4(7 1. Design #/ 2 decoder using /1 decoders 1. Design " !it adder using *ull adders in structural model 2. Design " !it adder using for..generate in structural model . Design " !it adder using if..generate in structural model ". Design 1 !it adder using " !it adders in structural model #. Design 2 !it adder wit$ " !it adders using for,generate in structural model (. Design " !it adder< 2u!tractor using structural model 1. Design "/2 encoder using case..w$en and w$en..else statements. :nputs Output D+ D1 D2 D =1 =+ 1 + + + + + > 1 + + + 1 > > 1 + 1 + > > > 1 1 1 2. Design a 1/ encoder using logic gates wit$ structural model . Design a 1/ priorit' encoder wit$ following trut$ ta!le ;sing structural model as well as using if.. statements

1.

%!i).%!o)s

12.

S3ift registers

:nputs Output D+ D1 D2 D D" D# D( D) > = ? 1 + + + + + + + + + + > 1 + + + + + + + + 1 > > 1 + + + + + + 1 + > > > 1 + + + + + 1 1 > > > > 1 + + + 1 + + > > > > > 1 + + 1 + 1 > > > > > > 1 + 1 1 + > > > > > > > 1 1 1 1 1. Design @AB *<*4 2AR *<*4 T *<* and D *<* using nested if statements 2. Design @AB *lip flop using NAND gates and 2R flip flop using NOR gates in structural model . %rite a CHD. coding for realizing clocDed @B flip flop using NAND gates along wit$ preset and clear action. ". Design D flip flop and T *lip flops using if statement #. Design master slaEe D flip flop and Eerif' t$e result. Design Master slaEe @AB *<* using structural model 1. Design a " !it 2:&O and &:2O s$ift registers using D *<*s in structural model 2. Design " !it 2:&O42:2O4&:2O and &:&O using nested if statements . Design 1 !it 2:&O and &:2O s$ift registers using D flip flops in structural model ". Design !arrel s$ifter using structural model #. Design a "!it uniEersal s$ift register. 1.Design "!it ripple counter using D *lip flop using structural model and Eerif' t$e result. 2. Design "!it up<down counter using T flip flop wit$ structural model and Eerif' t$e result. . Design # !it up<down counter t$at counts from +++++ to 1+111 and t$en decrements to +++++ using nested if statement. ". Generate a clocD signal wit$ freFuenc' (+BHz and dut' c'cle 2#<)#. Assume t$e input clocD c'cle period as 2#ns. 1.%rite a CHD. coding for a " !it !inar' arra' Multiplier using structural model and Eerif' t$e result. 2. %rite a CHD. coding for "!it 0 !it !inar' Multiplier using structural model and Eerif' t$e result. .%rite a CHD. coding for " !it 5aug$ %oole' Multiplier using structural model and Eerif' t$e result.

11.

(o#nters

1$.

M#!ti)!ier

". %rite a CHD. coding for "!it 5raun Multiplier using structural model and Eerif' t$e result.