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Block Memory Generator v2.8
DS512 September 19, 2008
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Product Specification

Introduction
The Xilinx LogiCORE™ IP Block Memory Generator core is an advanced memory constructor that generates area and performance-optimized memories using embedded block RAM resources in Xilinx FPGAs. Available through the CORE Generator™ software, users can quickly create optimized memories to leverage the performance and features of block RAMs in Xilinx FPGAs.

LogiCORE IP Facts Core Specifics
Virtex-5, Virtex-4, Virtex-II Pro, Virtex-II, Spartan-3E, Spartan-3A/3AN/3A DSP, Spartan-3 All All Varied, based on core parameters

Supported Device Family

Package Speed Grade Performance

Features
• Generates Single-port RAM, Simple Dual-port RAM, True Dual-port RAM, Single-port ROM, and Dual-port ROM • Performance up to 450 MHz • Supports data widths from 1 to 1152 bits • Supports memory depths from 2 to 9M words (limited only by memory resources on selected part) • Supports configurable port aspect ratios for dual-port configurations • Supports read-to-write aspect ratios in Virtex®-4 and Virtex-5 FPGAs • Optimized algorithm for minimum block RAM resource utilization • Algorithm for low power utilization • Configurable memory initialization • Supports individual write enable per byte in Virtex-5, Virtex-4, and Spartan®-3A/3A DSP FPGA devices with or without parity • Optimized VHDL and Verilog behavioral models for fast simulation times; structural simulation models for precise simulation of memory behaviors • Selectable operating mode per port: WRITE_FIRST, READ_FIRST, or NO_CHANGE • Supports built-in Hamming Error Correction Capability (ECC) • Supports pipelining of DOUT bus for improved performance in specific configurations

Core Resources
Block RAM DCM BUFG IOBs/RocketIO™ Transceivers PPC IOB-FF/TBUFs Varied, based on core parameters None None None None None

Provided with Core
Documentation Design File Formats Product Specification Migration Guide1 NGC netlist

Design Tool Requirements
Xilinx Implementation Tools ISE® 10.1 VHDL Structural Verilog Structural VHDL Behavioral2 Verilog Behavioral2 XST

Simulation Models

Synthesis

Support
Provided by Xilinx, Inc. @ www.xilinx.com
1. The Migration Guide provides instructions for converting legacy designs containing LogiCORE IP v6.x Single or Dual Port Block Memory instances to LogiCORE IP Block Memory Generator blocks. 2. Behavioral models do not precisely model collision behavior. See "Simulation Models" on page 23 for details.

©2006-2008 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners.

DS512 September 19, 2008 Product Specification

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Block Memory Generator v2.8

Overview
The Block Memory Generator core uses embedded Block Memory primitives in Xilinx FPGAs to extend the functionality and capability of a single primitive to memories of arbitrary widths and depths. Sophisticated algorithms within the Block Memory Generator core produce optimized solutions to provide convenient access to memories for a wide range of configurations. The Block Memory Generator has two fully independent ports that access a shared memory space. Both A and B ports have a write and a read interface. In Virtex-5 and Virtex-4 FPGA architectures, all four interfaces can be uniquely configured, each with a different data width. When not using all four interfaces, the user can select a simplified memory configuration (for example, a Single-Port Memory or Simple Dual-Port Memory), allowing the core to more efficiently use available resources. The Block Memory Generator is not completely backward-compatible with the Single-Port Block Memory and Dual-Port Block Memory cores; for information about the differences, see "Compatibility with Older Memory Cores" on page 40.

Applications
The Block Memory Generator core is used to create customized memories to suit any application. Typical applications include: • Single-port RAM: Processor scratch RAM, look-up tables • Simple Dual-port RAM: Content addressable memories, FIFOs • True Dual-port RAM: Multi-processor storage • Single-port ROM: Program code storage, initialization ROM • Dual-port ROM: Single ROM shared between two processors/systems

Feature Summary
Memory Types
The Block Memory Generator core uses embedded block RAM to generate five types of memories: • Single-port RAM • Simple Dual-port RAM • True Dual-port RAM • Single-port ROM • Dual-port ROM For dual-port memories, each port operates independently. Operating mode, clock frequency, optional output registers, and optional pins are selectable per port. For Simple Dual-port RAM, the operating modes are not selectable; they are fixed as READ_FIRST. See "Collision Behavior" on page 15 for additional information.

Selectable Memory Algorithm
The core concatenates block RAM primitives according to one of the following algorithms: • Minimum Area Algorithm: The memory is generated using the minimum number of block RAM primitives. Both data and parity bits are utilized. • Low Power Algorithm: The memory is generated such that the minimum number of block RAM primitives are enabled during a read or write operation.

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DS512 September 19, 2008 Product Specification

Block Memory Generator v2.8

• Fixed Primitive Algorithm: The memory is generated using only one type of block RAM primitive. For a complete list of primitives available for each device family, see the data sheet for that family.

Configurable Width and Depth
The Block Memory Generator can generate memory structures from 1 to 1152 bits wide, and at least two locations deep. The maximum depth of the memory is limited only by the number of block RAM primitives in the target device.

Selectable Operating Mode per Port
The Block Memory Generator supports the following block RAM primitive operating modes: WRITE FIRST, READ FIRST, and NO CHANGE. Each port may be assigned an operating mode.

Selectable Port Aspect Ratios
The core supports the same port aspect ratios as the block RAM primitives: • In all supported device families, the A port width may differ from the B port width by a factor of 1, 2, 4, 8, 16, or 32. • In Virtex-5 and Virtex-4 FPGA-based memories, the read width may differ from the write width by a factor of 1, 2, 4, 8, 16, or 32 for each port. The maximum ratio between any two of the data widths (DINA, DOUTA, DINB, and DOUTB) is 32:1.

Optional Byte-Write Enable
In Virtex-5, Virtex-4, and Spartan-3A/3A DSP FPGA-based memories, the Block Memory Generator core provides byte-write support for memory widths of 8-bit (no parity) or 9-bit multiples (with parity).

Optional Output Registers
The Block Memory Generator provides two optional stages of output registering to increase memory performance. The output registers can be chosen for port A and port B separately. The core supports the Virtex-5, Virtex-4, and Spartan-3A DSP embedded block RAM registers as well as registers implemented in the FPGA fabric. See "Output Register Configurations" on page 47 for more information about using these registers.

Optional Pipeline Stages
The core provides optional pipeline stages within the MUX, available only when the registers at the output of the memory core are enabled and only for specific configurations. For the available configurations, the number of pipeline stages can be 1, 2, or 3. For detailed information, see "Optional Pipeline Stages" on page 19.

Optional Enable Pin
The core provides optional port enable pins (ENA and ENB) to control the operation of the memory. When deasserted, no read, write, or reset operations are performed on the respective port. If the enable pins are not used, it is assumed that the port is always enabled.

Optional Synchronous Set/Reset Pin
The core provides optional set/reset pins (SSRA and SSRB) pin per port that synchronously initialize the read output to a programmable value.

DS512 September 19, 2008 Product Specification

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automating the process of primitive instantiation and concatenation. The ECC memory automatically detects single. Figure Top x-ref 1 Single-Port ROM ADDRA ENA SSRA REGCEA CLKA DOUTA Figure 1: Single-port ROM 4 www.Block Memory Generator v2. Single-port ROM. for example. A COE file can define the initial contents of each individual memory location. a Simple Dual-port RAM with symmetric ports can utilize the special Simple Dual-port RAM primitive in Virtex-5 devices. optimizations are made within the core to minimize the total resources used. Figures 1 through 5 illustrate the signals available for each type. probing the contents of the memory.xilinx. Functional Description The Block Memory Generator is used to build custom memory modules from block RAM primitives in Xilinx FPGAs. debugging. For example. The core implements an optimal memory by arranging block RAM primitives based on user selections. and Dual-port ROM. and is able to auto-correct the single-bit errors. Memory Type The Block Memory Generator creates five memory types: Single-port RAM. Using the CORE Generator Graphical User Interface (GUI).and double-bit errors. Built-in Hamming Error Correction Capability Single-port RAM and Simple Dual-port RAM memory types support the Virtex-5 FPGA Hamming Error Correction Capability (ECC) of the Virtex-5 FPGA block RAM primitives.8 Memory Initialization The memory contents can be optionally initialized using a memory coefficient (COE) file or by using the default data option. For each configuration. Simulation Models The Block Memory Generator core provides behavioral and structural simulation models in VHDL and Verilog for both simple and precise modeling of memory behaviors. as illustrated in Figure 1.com DS512 September 19. and collision detection. Simple Dual-port RAM. which can save as much as fifty percent of the block RAM resources for memories 512 words deep or fewer. Optional pins are displayed in italics. The Single-port ROM allows read access to the memory space through a single port. while the default data option defines the initial content of all locations. 2008 Product Specification . True Dual-port RAM. users can configure the core and rapidly generate a highly optimized custom memory solution.

Figure Top x-ref 3 Single-Port RAM DINA ADDRA WEA ENA SSRA REGCEA CLKA DOUTA Figure 3: Single-port RAM DS512 September 19. as shown in Figure 3. 2008 Product Specification www.Block Memory Generator v2. Figure Top x-ref 2 Dual-Port ROM ADDRA ENA SSRA REGCEA CLKA DOUTA ADDRB ENB SSRB REGCEB CLKB DOUTB Figure 2: Dual-port ROM The Single-port RAM allows read and write access to the memory through a single port.com 5 . as shown in Figure 2.8 The Dual-port ROM allows read access to the memory space through two ports.xilinx.

A and B. A and B.8 The Simple Dual-port RAM provides two ports. Figure Top x-ref 4 Simple Dual-Port RAM DINA ADDRA WEA ENA CLKA ADDRB ENB SSRB REGCEB CLKB DOUTB Figure 4: Simple Dual-port RAM The True Dual-port RAM provides two ports. Write access to the memory is allowed via port A.xilinx.Block Memory Generator v2. 2008 Product Specification . and read access is allowed via port B. Read and write accesses to the memory are allowed on either port.com DS512 September 19. as illustrated in Figure 5. Figure Top x-ref 5 True Dual-Port RAM DINA ADDRA WEA ENA SSRA REGCEA CLKA DOUTA DINB ADDRB WEB ENB SSRB REGCEB CLKB DOUTB Figure 5: True Dual-port RAM 6 www. as illustrated in Figure 4.

This algorithm is not optimized for area and may use more block RAMs and DS512 September 19. Figure Top x-ref 6 3kx16 memory 2kx9 2kx9 5kx17 memory 2kx9 4kx4 1kx18 4kx4 2kx9 1kx18 Figure 6: Examples of the Minimum Area Algorithm The first example. further demonstrates how the algorithm can pack block RAMs efficiently to use the fewest resources while maximizing performance by reducing output multiplexing. a 3kx16 memory is implemented using three block RAMs.Block Memory Generator v2. while reducing output multiplexing. a 5kx17 memory. Minimum Area Algorithm The minimum area algorithm provides a highly optimized solution. Figure 6 shows two examples of memories built using the minimum area algorithm.com 7 . The minimum area algorithm maximizes performance in this way while maintaining minimum block RAM usage. The second example. 2008 Product Specification www. Low Power Algorithm The low power algorithm provides a solution that minimizes the number of primitives enabled during a read or write operation. this would require more output multiplexing. While it may have been possible to concatenate three 1kx18 block RAMs in depth. resulting in a minimum number of block RAM primitives used. the low power algorithm and the fixed primitive algorithm.xilinx.8 Selectable Memory Algorithm The Block Memory Generator core arranges block RAM primitives according to one of three algorithms: the minimum area algorithm.

Figure 7 shows two examples of memories built using the low power algorithm. the other built using the 4kx4 primitive type. Figure Top x-ref 8 3kx16 memory 2kx9 2kx9 3kx16 memory 4kx4 4kx4 4kx4 4kx4 2kx9 2kx9 Figure 8: Examples of the Fixed Primitive Algorithm Note that both implementations use four block RAMs. The core will build the memory by concatenating this single primitive type in width and depth.com DS512 September 19. 2008 Product Specification . 4kx4. 8kx2.Block Memory Generator v2.xilinx. It is up to the user to decide which primitive type is best for their application. It is useful in systems that require a fixed primitive type. and that some of the resources utilized extend beyond the usable memory space. optimizations are made automatically that use deeper embedded memory struc- 8 www. one built using the 2kx9 primitive type. Figure 8 depicts two 3kx16 memories.8 multiplexers than the minimum area algorithm. Figure Top x-ref 7 3kx16 Memory 1kx18 5kx17 Memory 1kx18 1kx18 1kx18 1kx18 1kx18 1kx18 1kx18 Figure 7: Examples of the Low Power Algorithm Fixed Primitive Algorithm The fixed primitive algorithm allows the user to select a single block RAM primitive type. The primitive type selected is used to guide the construction of the total user memory space. 1kx18. Whenever possible. The fixed primitive algorithm provides a choice of 16kx1. 512x36 and 256x72 primitives. 2kx9.

8kx2 8kx4. Virtex-II Pro FPGA. the primitive type dimensions are chosen with respect to the A port write width. When using the byte write feature in Virtex-5. Virtex-4. Spartan-3 and its derivatives. and total memory size is limited only by the number of block RAMs on the target device. Table 1 shows the primitives used to construct a memory given the specified architecture and primitive selection. When using data-width aspect ratios. 16kx1 16kx2. 32kx1.com 9 .Block Memory Generator v2. 1kx18. Spartan-32 Virtex-II1.xilinx. Table 1: Memory Primitives Used Based on Architecture Architecture Virtex-II1.8 tures to enhance performance. Virtex-II1. Spartan-32 Virtex-4 Virtex-4 Virtex-4 Virtex-4 Virtex-4 Virtex-4 Virtex-4 Virtex-5 Virtex-5 Virtex-5 Virtex-5 Virtex-5 Virtex-5 256x72 (Single Port configurations only) 32kx1. Spartan-32 Virtex-II1. 1kx18 1kx36 512x36 (Single-port RAMs only) 512x72 (Single and Simple Dual-port RAMs and Single Port ROMs only) Virtex-5 256x72 1. Spartan-32 Spartan-32 16kx1 8kx2 4kx4 2kx9 1kx18 512x36 256x72 16kx1 8kx2 4kx4 2kx9 1kx18 512x36 256x72 16kx1 8kx2 4kx4 2kx9 1kx18 512x36 Primitive Selection 16kx1 8kx2 4kx4 2kx9 1kx18 512x36 Primitives Used Virtex-II1. Note that primitive selection may limit port aspect ratios as described in "Aspect Ratio Limitations" on page 13. and 512kx36 primitive choices are available. 2kx9 2kx18. 2008 Product Specification www. 4kx4 4kx9. The memory is built by concatenating block RAM primitives. and with depths of two or more words. Spartan-32 Virtex-II1. DS512 September 19. Selectable Width and Depth The Block Memory Generator generates memories with widths from 1 to 1152 bits. Spartan-32 Virtex-II1. including Spartan-3E and Spartan-3A/3A DSP devices. 2. only the 2kx9. and Spartan-3A/3A DSP devices. Virtex-II FPGA and its derivative. 16kx1 8kx2 4kx4 2kx9 1kx18 512x36 256x72 (Single Port configurations only) 64kx1.

and Spartan-3A/3A DSP devices. see the block RAM section of the user guide specific to the device family. as shown in Figure 9. This transparent mode offers the flexibility of using the data output bus during a write operation on the same port. For more information about operating modes. data previously stored at the write address appears on the data output. Port A and port B can be configured independently with any one of three write modes: Write First Mode. It is also affected by the optional read-to-write aspect ratio feature in Virtex-5 and Virtex-4 devices. Note that the set/reset function should not be asserted while accessing an out-of-range address as this also results in invalid data on the output. the input data is simultaneously written into memory and driven on the data output. For detailed information. For detailed information about collision behavior. This read-before-write behavior is 10 www. or No Change Mode. while the input data is being stored in memory. Virtex-4. see "Write First Mode Considerations" on page 15.Block Memory Generator v2. • Read First Mode: In READ_FIRST mode. Read First Mode. • Write First Mode: In WRITE_FIRST mode. 2008 Product Specification .com DS512 September 19. Figure Top x-ref 9 CLKA WEA DINA[15:0] ADDRA DOUTA[15:0] ENA DISABLED READ WRITE MEM(bb)= 1111 WRITE MEM(cc)= 2222 READ 0000 aa MEM(aa) 1111 bb 1111 2222 cc 2222 dd MEM(dd) Figure 9: Write First Mode Example Note: The WRITE_FIRST operation is affected by the optional byte-write feature in Virtex-5. see "Collision Behavior" on page 15. These operating modes are described in the sections that follow. while read operations to out-of-range addresses will return invalid data.xilinx.8 Write operations to out-of-range addresses are guaranteed not to corrupt data in the memory. The operating modes have an effect on the relationship between the A and B ports when the A and B port addresses have a collision. Operating Mode The operating mode for each port determines the relationship between the write and read interfaces for that port.

and 32:1. The smaller data words are arranged in little-endian format. DS512 September 19. 1:1. 1:16.xilinx. and DOUTB) can have different widths. 4:1. as illustrated in Figure 12. In Virtex-5 and Virtex-4 FPGA-based memories. as described in Port Aspect Ratios in the following section.com 11 . This allows the port A data width to be different than the port B data width. as described in "Virtex-5 and Virtex-4 Read-to-Write Aspect Ratios" on page 12. 2:1. 1:4. DOUTA. all four data busses (DINA. 16:1. or vice versa. Figure Top x-ref 10 CLKA WEA DINA[15:0] ADDRA DOUTA[15:0] ENA DISABLED READ WRITE MEM(bb)= 1111 WRITE MEM(cc)= 2222 READ 0000 aa MEM(aa) 1111 bb 2222 cc old MEM(bb) dd old MEM(cc) MEM(dd) Figure 10: Read First Mode Example • No Change Mode: In NO_CHANGE mode. the output latches remain unchanged during a write operation. 2008 Product Specification www. Figure Top x-ref 11 CLKA WEA DINA[15:0] ADDRA DOUTA[15:0] ENA DISABLED READ WRITE MEM(bb)= 1111 WRITE MEM(cc)= 2222 READ 0000 aa MEM(aa) 1111 bb 2222 cc dd MEM(dd) Figure 11: No Change Mode Example Data Width Aspect Ratios The Block Memory Generator supports data width aspect ratios. The CORE Generator GUI ensures only valid aspect ratios are selected. Port Aspect Ratios The Block Memory Generator supports port aspect ratios of 1:32. the data output is still the previous read data and is unaffected by a write operation on the same port. 1:2. 1:8. As shown in Figure 11. 8:1. DINB.8 illustrated in Figure 10. The limitations of the data width aspect ratio feature (some of which are imposed by other optional features) are described in "Aspect Ratio Limitations" on page 13.Block Memory Generator v2. The port A data width can be up to 32 times larger than the port B data width.

it is possible for all four data buses (DINA. For the shallower interface. For example. Virtex-5 and Virtex-4 Read-to-Write Aspect Ratio Example Consider a True Dual-port RAM of 64x512. From the perspective of an 8-bit B port. and B0.. 4:1. 0 B0 7 . 0 B2 7 . Table 2: Read-to-Write Aspect Ratio Example Ports Interface Port A Write Port A Read Port B Write Port B Read Data Width 64 16 256 32 Memory Depth 512 2048 128 1024 12 www. The data words are arranged in little-endian format. The maximum ratio between any two data buses is 32:1. The ADDRA bus is 11 bits. B5 B4 Figure 12: Port Aspect Ratio Example Memory Map Virtex-5 and Virtex-4 Read-to-Write Aspect Ratios When implementing RAMs targeting Virtex-5 and Virtex-4 FPGAs.8 Port Aspect Ratio Example Consider a True Dual-port RAM of 32x2048. the read to write data width ratio of that port can be 1:32. 0 B3 7 . Table 2 defines the four data-port widths and their respective depths for this example.Block Memory Generator v2. 16:1. DINB... The data is stored little-endian. if the read interface of port A is twice as wide as the write interface. and DOUTB) of True Dual-port RAMs to have a different width. with respect to the A port. A0 is comprised of B3. which is the A port width and depth.. Because the read and write interfaces of each port can differ. the depth would be 8192. For Single-port RAMs. B1.xilinx. 1:4. . 2:1. as shown in Figure 12. 1:2. 8:1. 1:1.. 2008 Product Specification . 0 A0 = A1 = 7 . as illustrated in Figure 13.. Figure Top x-ref 12 31 0 7 . or 32:1. DINA and DOUTA widths can be independent. the Block Memory Generator allows read and write aspect ratios on either port. 0 B1 7 . 0 B7 B6 . The widest data bus can be no larger than 1152 bits. On each port A and port B. then it is also half as deep. The ratio of the widths is always the inverse of the ratio of the depths. Note that An is the data word at address n.. DOUTA. which is the port A write width and depth. B2. while the ADDRB bus is 13 bits. the least significant bits of the address bus are ignored. 0 7 . 1:16. 0 7 . the memory depth is different with respect to read and write accesses. Bn is the data word at address n with respect to the B port. . the address bus must be large enough to address the deeper of the two depths. Because a single address bus is used for both the write and read interface of a port.com DS512 September 19.. 1:8. If the read and write data widths on a port are different.

where N is the number of bytes in DIN[A|B]. For this reason. read operations utilize the entire ADDRB bus. 2008 Product Specification www.xilinx. it may not DS512 September 19. For example. . read operations utilize the entire ADDRA bus. However. aspect ratios are limited to 32:N and 1:N from the port A write width. the largest data width ratio is port B write words (256 bits) to port A read words (16 bits). and no two data widths can have a ratio greater than 32:1. When using a 9-bit byte size. with the 9th bit of each byte in the data word serving as a parity bit for that byte. and AW0. with no parity. The byte-write feature may be used in conjunction with the data width aspect ratios. AW2. In the same way. In the example above. which may limit the choice of data widths as described in "Data Width Aspect Ratios" on page 11. For this reason. Virtex-4. In the same way. When using an 8-bit byte size. BR0 is made up of AR1 and AR0. Bytes will be stored in memory only if the corresponding bit in the write enable bus is asserted during the write operation. in a little-endian arrangement. Aspect Ratio Limitations In general. while BWn is the write data word at address n with respect to port B. the ADDRB width is determined by the larger of the B port depths (1024). the WE[A|B] bus is N bits wide. Byte-writes are available using either 8-bit or 9-bit byte sizes. and Spartan-3A/3A DSP devices. When using byte-writes. this ratio is 16:1. no two data widths can have a ratio greater than 4:1. each byte includes a parity bit. the other ports may be no more than 8 times (32:4) larger than port A write width and no less than 4 times (1:4) smaller. When 9-bit bytes are selected. the DIN and DOUT data buses are constructed from 9-bit bytes. On port A. On port B. When byte-writes are enabled. AW 1 AW 5 AW 0 AW 4 Figure 13: Read-to-Write Aspect Ratio Example Memory Map BW0 is made up of AW3. Figure Top x-ref 13 255 0 BW 0 = BW 1 = AW 3 AW 7 AW 2 AW 6 . ADDRB is 10 bits wide. Byte-Writes The Block Memory Generator provides byte-write support in Virtex-5. . ADDRA is 11 bits wide. the following optional features further limit data width aspect ratios: • Byte-writes. • Fixed primitive algorithm. The most significant bit in the write enable bus corresponds to the most significant byte in the input word.com 13 . The memory map in Figure 13 shows how port B write words are related to port A write words. However. and AW0 is made up of BR1 and BR0. the DIN and DOUT data buses are constructed from 8-bit bytes. no parity bits are used and the memory width is restricted to multiples of 8 bits.8 The ADDRA width is determined by the larger of the A port depths (2048). no port data width can be wider than 1152 bits. and the memory width is restricted to multiples of 9 bits. while write operations ignore the least significant 2 bits.Block Memory Generator v2. When 8-bit bytes are selected. while write operations ignore the least significant 3 bits. using the 4kx4 primitive type. Note that AWn is the write data word at address n with respect to port A. AW1. When using the fixed primitive algorithm with an N-bit wide primitive.

This is because if a memory configuration uses multiple primitives in width.xilinx. and shows the contents of the RAM at address 0. The byte-write feature also affects the operation of WRITE_FIRST mode. The NO_CHANGE mode does not apply to the other primitives that are not being written to. WEA. Assume all memory locations are initialized to 0. and only one primitive is being written to (using partial byte writes). so these primitives can still be read. consists of 3 bits. The write enable bus. Figure Top x-ref 14 CLKA WEA[2:0] ADDRA[15:0] DINA[23:0] RAM Contents FF EE DD CC BB AA 00 EE DD 99 88 77 00 BB DD b011 b010 b101 0000 66 55 44 99 BB 77 33 22 11 00 FF 00 33 22 77 33 FF 77 b000 b110 b010 Figure 14: Byte-write Example 14 www. Figure 14 illustrates the use of byte-writes. as described in "Write First Mode Considerations" on page 15. Byte-Write Example Consider a Single-port RAM with a data width of 24 bits.com DS512 September 19. or 3 bytes with byte size of 8 bits. 2008 Product Specification . then the NO_CHANGE mode only applies to that single primitive.Block Memory Generator v2.8 be used with the NO_CHANGE operating mode.

The resulting contents of the memory location are unknown.Block Memory Generator v2. • Synchronous Write-Write Collisions. is it possible to have data collisions. 2008 Product Specification www. This clock-to-clock setup time is defined in the device data sheet. Note that write-write collisions affect memory content. Collision Behavior The Block Memory Generator core supports Dual-port RAM implementations.xilinx. RAM contents are corrupted only when both ports attempt to write the same byte. Collisions and Asynchronous Clocks Using asynchronous clocks. In such an arrangement. However. memory contents are not corrupted when separate bytes are written in the same data word. • Using Byte-Writes. the output of the memory cannot be guaranteed. along with other block RAM switching characteristics. as opposed to write-read collisions which only affect data output. Figure 15 illustrates this case. the concurrent read operation shows the newly written data on the output of the core. The ramifications of this behavior are described for both asynchronous and synchronous clocks below.com 15 . Virtex-4. when one port writes data to a memory location. Each port is equivalent and independent.8 Write First Mode Considerations When performing a write operation in WRITE_FIRST mode. described below. when using the byte-write feature in Virtex-5. yet they access the same memory space. the other port must not read or write that location for a specified amount of time. A write-write collision occurs if both ports attempt to write to the same location in memory. Figure Top x-ref 15 CLKA WEA[3:0] WEB[3:0] DINA[31:0] DINB[31:0] RAM Contents b1100 b0011 7654 FFFF FFFF 3210 b0101 b1010 AAAA AAAA BBBB BBBB 7654 3210 b1110 b0011 7777 7777 0000 0000 BBAA BBAA b0110 AAAA AAAA BBBB BBBB 7777 XX00 b1111 b1111 1111 1111 2222 2222 AAXX XXAA XXXX XXXX Figure 15: Write-write Collision Example DS512 September 19. When using byte-writes. Assume ADDRA = ADDRB = 0. and Spartan-3A/3A DSP devices or the read-to-write aspect ratio feature in Virtex-5 and Virtex-4 devices. Collisions and Synchronous Clocks Synchronous clocks cause a number of special case collision scenarios.

port B is always reading. the validity of the output data depends on the write port operating mode.8 • Synchronous Write-Read Collisions. The Simple Dual-port RAM is like a true dual-port RAM. Figure 16 illustrates write-read collisions and the effects of byte-writes. The operating modes define the write-to-read relationship of the A or B ports. Figure Top x-ref 16 CLKA WEA[3:0] DINA[31:0] DOUTBARF DOUTBAWF RAM Contents b0000 b0101 AAAA AAAA 0000 0000 0000 0000 0000 0000 00XX 00XX b0000 b1100 3322 1100 00AA 00AA 00AA 00AA XXXX 00AA 3322 00AA b1111 1111 1111 3322 00AA XXXX XXXX 1111 1111 1111 1111 b0000 00AA 00AA 1111 1111 Figure 16: Write-read Collision Example Collisions and Simple Dual-port RAM For Simple Dual-port RAM. only bytes which are updated will be invalid on the read port output.In the case of byte-writes. but are fixed as READ_FIRST.If the write port is in WRITE_FIRST or NO_CHANGE mode. . 16 www. The RAM contents are never corrupted in write-read collisions.Block Memory Generator v2. While memory contents are not corrupted in write-read collisions. and all memory locations are initialized to 0. . For detailed information about this behavior.xilinx. and only impact the relationship between A and B ports during an address collision. DOUTB is shown for when port A is in WRITE_FIRST mode and READ_FIRST mode. . the operating modes are not selectable. the other port can reliably read the old memory contents. As a result. data on the output of the read port is invalid.If the write port is in READ_FIRST mode. see "Collision Behavior" on page 15. Assume ADDRA = ADDRB = 0. the write mode of port A can be configured such that the read operation on port B either produces data (it acts like READ_FIRST). where only the write interface of the A port and the read interface of B port are connected. the core is hard-coded to produce the READ_FIRST-like behavior when configured as a Simple Dual-port RAM. or produces undefined data (Xs).com DS512 September 19. During a collision. 2008 Product Specification . A synchronous write-read collision may occur if a port attempts to write a memory location and the other port reads the same location.

xilinx.Block Memory Generator v2. 2008 Product Specification www.8 Optional Output Registers The Block Memory Generator allows optional output registers. Each of the two optional register stages can be chosen for port A and port B separately.com 17 . The user may choose to include register stages at two places–at the output of the block RAM primitives and at the output of the core. Note that each optional register stage used adds an additional clock cycle of latency to the read operation. Figure 17 shows a memory configuration with registers at the output of the memory primitives and at the output of the core for one of the ports. Registers at the output of the core isolate the delay through the output multiplexers. which may improve the performance of the core. Figure Top x-ref 17 Block Memory Generator Core Block RAM Primitives Block RAM Primitive Output Registers D CE Q Block RAM Latches Block RAM Latches D CE Q Core Output Registers MUX D CE S* Q DOUT Latches D CE Q CLK Use REGCE Pin EN REGCE SSR FALSE TRUE S* : The synchronous reset (S) of the flop is gated by CE Figure 17: Virtex-II Block Memory: Register Port [A|B] Outputs of Memory Primitives and Memory Core Options Enabled DS512 September 19. Registers at the output of the block RAM primitives reduce the impact of the clock-to-out delay of the primitives. improving the clock-to-out delay of the Block Memory Generator core.

xilinx. Virtex-4. All other register stages are implemented in FPGA fabric. To force the core to use the embedded output registers in Spartan-3A DSP device. Figure 18 shows an example of a Virtex-4 or Virtex-5-based memory that has been configured using both output register stages for one of the ports. For a complete description of the supported output options.8 For Virtex-5. the Register Port [A|B] Output of Memory Primitives option may be implemented using the embedded block RAM registers. the RAMB16BWER Reset Behavior option is provided. 18 www. 2008 Product Specification . requiring no further FPGA resources. By default.com DS512 September 19. the behavior of the embedded output registers in the Spartan-3A DSP FPGA differs slightly from the configuration shown in Figure 18.Block Memory Generator v2. and Spartan-3A DSP FPGAs. the Block Memory Generator builds the memory output register in the FPGA fabric to maintain functionality compatibility with Virtex-4 and Virtex-5 FPGA configurations. Figure Top x-ref 18 Block Memory Generator Core Block RAM Primitives Block RAM Block RAM LaL tche atche s s Embedded Output Registers Embedded Output Registers Embedded Output Registers Core Output Registers MUX D CE S* Q Block RAM Latches Latches DOUT SSR* D CE SSR* CE Latches Q CE CLK Use REGCE Pin EN REGCE SSR FALSE TRUE S* : The synchronous reset (S) of the flop is gated by CE Figure 18: Virtex-5 and Virtex-4 Block Memory with Register Port [A|B] Output of Memory Primitives and Register Port [A|B] Output of Memory Core Options Enabled When using the Synchronous Reset Input (SSR). see "Output Register Configurations" on page 47.

Users can add up to three pipeline stages within the MUX. See "Pipeline Stages within Mux" on page 31 for detailed information. 2.8 Optional Pipeline Stages The Block Memory Generator core allows optional pipeline stages within the MUX. excluding the registers at the output of the core. Note that each pipeline stage adds an additional clock cycle of latency to the read operation. The MUX size displayed in the GUI can be used to determine the number of pipeline stages to use within the MUX. so that a MUX is needed on the output. This optional pipeline stages option is available only when the registers at the output of the memory core are enabled and when the constructed memory has more than one primitive in depth. DS512 September 19. If the configuration has ECC. 2008 Product Specification www.xilinx. or 3 if the Register Output of Memory Core option is selected in the GUI for both port A and port B. Figure 19 shows a memory configuration with an 8:1 MUX and two pipeline stages within the MUX. The pipeline stages are common for port A and port B and can be a value of 1.com 19 . which may improve core performance. This figure explains how the 8:1 MUX is pipelined internally with two register stages.Block Memory Generator v2. the SBITERR and DBITERR outputs are delayed to align with DOUT. Note that adding pipeline stages within the MUX improves performance only if the critical path in the design is the data through the MUX.

When using the REGCE pin. However. when the Use REGCEA/REGCEB Pin option is selected.xilinx.Block Memory Generator v2.8 Figure Top x-ref 19 8:1 MUX block RAMs 2:1 (After pipelining) Pipeline Stage 1 D v Pipeline Stage 2 Q 2:1 D Q 2:1 D v > Q Core Output Registers 2:1 D CE Q DOUT > 2:1 D Q S* v 2:1 D Q > 2:1 D v Q Use REGCE Pin CLK EN REGCE SSR S*: Synchronous reset (S) of the flop is gated by CE False True Figure 19: Memory Configuration with 8:1 MUX and Two Pipeline Stages within the MUX Optional Register Clock Enable Pins The optional output registers are enabled by the EN signal by default. the output register stage of the corresponding port is controlled by the REGCEA/REGCEB pins. 20 www. the data output from the core can be controlled independent of the flow of data through the rest of the core. the last output register operates independently of the EN signal.com DS512 September 19. 2008 Product Specification .

and register enable (REGCE) pins allow a wide range of data flows in the output stage. 2008 Product Specification www. the data on the output of that port is driven to the reset value defined in the CORE Generator GUI. Figure Top x-ref 20 CLKA ADDRA[7:0] LATCH REG1 SSR DOUT FFFF data(AA) FFFF data(BB) data(CC) FFFF AA data(AA) data(AA) BB CC data(BB) data(CC) data(BB) data(CC) DD data(DD) data(DD) Figure 20: Flow Control Using SSR DS512 September 19. The data on the block RAM memory latch is labeled LATCH. Figure 20 depicts how SSR can be used to control the data output to allow only intended data through. the synchronous set/reset behavior differs when the RAMB16BWER reset behavior option is selected.com 21 . (The reset occurs on SSR and EN when the Use REGCE Pin option is not selected.8 Optional Synchronous Set/Reset Pins The synchronous set/reset pins (SSRA and SSRB) control the reset operation of the last register in the output stage. this option saves resources by using the embedded output registers available in Spartan-3A DSP RAMB16BWER primitives. When SSR and REGCE are asserted on a given port. DOUT.xilinx. See "Output Register Configurations" on page 47 for more information. • For Spartan-3A DSP FPGAs. reset (SSR).Block Memory Generator v2.) • For Virtex-4 FPGAs. and that EN and REGCE are always asserted. For memories with no output registers. The output of the last register is the output of the core. Assume that both output registers are used for port A. However. Figure 20 and Figure 21 are examples on how this can be accomplished. Keep in mind that the SSR and REGCE pins apply only to the last register stage. if the option to use the synchronous set/reset pin is selected in conjunction with memory primitive registers and without core output registers. while the output of the block RAM embedded register is labeled REG1. the port A reset value is 0xFFFF. Memory Output Flow Control Examples The combination of the enable (EN). the reset pins control the memory output latches. the Virtex-4 embedded block RAM registers are not utilized for the corresponding port and are implemented in the FPGA logic instead.

xilinx. single error corrected. The data on the block RAM memory latch is labeled latch. This operation is transparent to the user. the Block Memory Generator core supports built-in Hamming Error Correction Capability (ECC) for the block RAM primitives. and that EN is always asserted and SSR is always deasserted. The 512x64 primitives are used to build memory sufficient for the desired user memory space. These bits are used during each read operation to correct any single bit error. or to detect (but not correct) any double bit error.8 Figure 21 depicts how REGCE can be used to latch the data output to allow only intended data through. The ECC memory block is 512x64. Figure Top x-ref 21 CLKA ADDRA[7:0] LATCH REGCE DOUT data(AA) data(BB) data(CC) data(DD) AA data(AA) BB CC data(BB) data(CC) DD data(DD) Figure 21: Flow Control Using REGCE Built-in Error Correction Capability For Virtex-5 devices. ECC is only available when the following options are chosen: • Virtex-5 FPGA • Single-port RAM or Simple Dual-port RAM memory type When using ECC. For single-bit errors. Assume that only the memory primitive registers are used for port A. Two status outputs (SBITERR and DBITERR) indicate the three possible read results: no error. 2008 Product Specification . which are stored with the data in memory. the read operation does not correct the error in the memory array. other limited core options include the following: • Byte-write enable is not available • All port widths must be identical • Only Read First Operating Mode is supported • Synchronous Reset (SSR) and the Output Reset Value options are not available • Memory Initialization is not supported • No Algorithm selection is available 22 www. When using ECC.com DS512 September 19. DOUT.Block Memory Generator v2. Each write operation generates 8 protection bits for every 64 bits of data. while the output of the last register. it only presents corrected data on DOUT. the block RAM embedded register. is the core output. and double error detected. the Block Memory Generator constructs the memory from special primitives available in Virtex-5 FPGA architectures. and is composed of two 18k block RAMs combined with dedicated ECC encoding and decoding hardware.

Simulation Models The Block Memory Generator core provides two types of functional simulation models: • Behavioral Simulation Models (VHDL and Verilog) • Structural/Unisim based Simulation Models (VHDL and Verilog) The behavioral simulation models provide a simplified model of the core while the structural simulation models (UniSim) are an accurate modeling of the internal structure of the core. Table 3 defines the differences between the two functional simulation models.8 Figure 22 illustrates a typical write and read operation for a Virtex-5 FPGA Block Memory Generator core in Simple Dual-port RAM with ECC enabled. and flags a warning message Flags all byte-write collisions Structural Models (Unisim) Generates ‘X’ to match core Generates ‘X’ Generates ‘X’ to match core Does not flag collisions if byte-writes do not overlap DS512 September 19. For this reason. The Simulation Files options in the CORE Generator Project Options determine the type of functional simulation models generated. CLKB WEA DINA ADDRA ENA ADDRB DOUTB DBITERR SBITERR ENB 00 aa ac 1111 aa 2222 Figure 22: Read and Write Operation with ECC in Virtex-5 The Block Memory Generator core does not support the insertion of errors for correction by ECC in simulation. The structural simulation model uses primitive instantiations to model the behavior of the core more precisely. 2008 Product Specification www.com 23 . making it easier to probe contents of the memory. The behavioral simulation models are written purely in RTL and simulate faster than the structural simulation models and are ideal for functional debugging. Moreover. Table 3: Differences between Simulation Models When core output is undefined Out-of-range address access Collision behavior Byte-write collision behavior Behavioral Models Never generates ‘X’ Optionally flags a warning message Does not generate ‘X’ on output. the memory is modeled in a two-dimensional array. the simulated functionality of ECC is identical to non-ECC behavior with the SBITERR and DBITERR outputs always equal to 0. Use the structural simulation model to accurately model memory collision behavior and 'x' output generation. Note that simulation time is longer and debugging may be more difficult.Block Memory Generator v2.xilinx. and no additional output registers. Figure Top x-ref 22 CLKA.

WEA and WEB widths depend on the byte size and write data widths selected in the GUI. Available in all configurations. Available in dual-port configurations. write. Available in Dual-port RAM configurations. The widths of the data ports (DINA. Available in dual-port configurations. Port A Data Output: Data output from read operations via port A. Port A Write Enable: Enables write operations via port A. Optional in all configurations with port A output registers. and DOUTB) are selected by the user in the CORE Generator GUI. Port A Register Enable: Enables the last output register of port A. For synchronous operation. Port A Data Input: Data input to be written into the memory via port A. Port B Data Output: Data output from read operations via Port B. Port B Synchronous Set/Reset: Resets the Port B memory output latch or output register. Port A Address: Addresses the memory space for port A read and write operations. When byte-writes are enabled. The write enable ports (WEA and WEB) are busses of width 1 when byte-writes are disabled. CLKB Input ADDRB DINB DOUTB ENB WEB SSRB Input Input Output Input Input Input 24 www. DINB.8 Signal List Table 4 provides a description of the Block Memory Generator core signals.com DS512 September 19. and reset operations via port A. Available in all RAM configurations. 2008 Product Specification . Available in all configurations except Simple Dual-port RAM. DOUTA. The address port (ADDRA and ADDRB) widths are determined by the memory depth with respect to each port. and reset operations via Port B. Port B Clock: Port B operations are synchronous to this clock. write. Port B Data Input: Data input to be written into the memory via port B. For synchronous operation. Available in dual-port configurations. Port A Synchronous Set/Reset: Resets the port A memory output latch or output register. Optional in all configurations. as selected by the user in the GUI. this must be driven by the same signal as CLKA. Optional in all configurations.xilinx. Optional in dual-port configurations. this must be driven by the same signal as CLKB. Port B address: Addresses the memory space for port B read and write operations. Port A Clock Enable: Enables read. Available in True Dual-port RAM configurations. Port B Clock Enable: Enables read. Port B Write Enable: Enables write operations via Port B. Optional in dual-port configurations.Block Memory Generator v2. Available in all RAM configurations. Table 4: Core Signal Pinout Name CLKA ADDRA DINA DOUTA ENA WEA SSRA REGCEA Direction Input Input Input Output Input Input Input Input Description Port A Clock: Port A operations are synchronous to this clock.

DS512 September 19.com 25 . Double Bit Error : Flags the presence of a double-bit error in memory. Generating the Core The Block Memory Generator is available from the CORE Generator software. do the following: Click View by Function > Memories & Storage Elements> RAMs & ROMs The following section defines the Block Memory Generator GUI screens and available customization options. 2008 Product Specification www. all the screens share common tabs and buttons to provide information about the core and to navigate the Block Memory Generator GUI.8 Table 4: Core Signal Pinout (Continued) Name REGCEB SBITERR DBITERR Direction Input Output Output Description Port B Register Enable: Enables the last output register of port B.xilinx. To open the Block Memory core from the main CORE Generator window.Block Memory Generator v2. Optional in dual-port configurations with port B output registers. Double-bit errors cannot be auto-corrected by the built-in ECC decode module. CORE Generator Parameter Screens The Block Memory Generator GUI includes five main screens: • Block Memory Generator Main Screen • Port A Options Screen • Port B Options Screen • Output Registers and Memory Initialization Screen • Simulation Model Options and Information Screen In addition. SIngle Bit Error : Flags the presence of a single-bit error in memory which has been auto-corrected on the output bus.

xilinx. and “_”.Block Memory Generator v2.com DS512 September 19. 2008 Product Specification . Names can not be Verilog or VHDL reserved words. 0 to 9.8 Block Memory Generator Main Screen Figure Top x-ref 23 Figure 23: Block Memory Generator Main Screen Component Name The base name of the output files generated for the core. Names must begin with a letter and be composed of any of the following characters: a to z. • Single-port RAM • Simple Dual-port RAM • True Dual-port RAM • Single-port ROM • Dual-port ROM 26 www. Memory Type Select the type of memory to be generated.

the ECC options become available. See "Built-in Hamming Error Correction Capability" on page 4 for more information. When using ECC. Algorithm Select the algorithm used to implement the memory: • Minimum Area Algorithm: Generates a core using the least number of primitives. Choose which primitive type to use in the drop-down list.Block Memory Generator v2. or Spartan-3A/3A DSP devices. Selecting ECC enables built-in Hamming error correction for the Virtex-5 FPGA architecture.8 ECC Options When targeting Virtex-5 devices.com 27 . • Low Power Algorithm: Generates a core such that the minimum number of block RAM primitives are enabled during a read or write operation. • Fixed Primitive Algorithm: Generates a core that concatenates a single primitive type to implement the memory. The data width of the memory will be multiples of the selected byte-size. 2008 Product Specification www. the following options are limited: • Byte-write Enable is not available • All port widths must be identical • Only Read First Operating mode is supported • Synchronous Reset (SSR) and the Output Reset Value options are not available • Memory Initialization is not supported • No algorithm selection is available Write Enable When targeting Virtex-5. and when either Single-port RAM or Simple dual-port RAM memory type is selected. select whether to use the byte-write enable feature.xilinx. Byte size is either 8-bits (no parity) or 9-bits (including parity). Virtex-4. DS512 September 19.

Block Memory Generator v2.com DS512 September 19.8 Port A Options Screen Figure Top x-ref 24 Figure 24: Port A Options Memory Size (Port A) Specify the port A write width and depth. The read depth is calculated automatically. • READ_FIRST • WRITE_FIRST • NO_CHANGE Enable (Port A) Select the enable type: • Always enabled (no ENA pin available) • Use ENA pin 28 www. Select the port A read width from the drop-down list of valid choices. Operating Mode (Port A) Specify the port A operating mode.xilinx. 2008 Product Specification .

Operating Mode (Port B) Specify the port B write mode. 2008 Product Specification www. These values are with respect to the read port widths. Port B Options Screen Figure Top x-ref 25 Figure 25: Port B Options Memory Size (Port B) Select the port B write and read widths from the drop-down list of valid choices. The read depth is calculated automatically. • READ_FIRST • WRITE_FIRST • NO_CHANGE DS512 September 19.8 Output Reset (Port A) Specify the reset value of the memory output latch and output registers.Block Memory Generator v2. Choose whether a set/reset pin (SSRA) is needed.com 29 .xilinx.

Select to insert output register after the memory primitives for port A and port B separately.xilinx.Block Memory Generator v2. Choose whether a set/reset pin (SSRB) is needed. For other architectures. When targeting Virtex-4 or Virtex-5 FPGAs. Output Registers and Memory Initialization Screen Figure Top x-ref 26 Figure 26: Output Registers and Memory Initialization Screen Optional Output Registers Select the output register stages to include: • Register Port [A|B] Output of Memory Primitives. the registers in the FPGA slices are 30 www.com DS512 September 19. 2008 Product Specification .8 Enable (Port B) Select the enable type: • Always enabled (no ENB pin available) • Use ENB pin Output Reset (Port B) Specify the reset value of the memory output latch and output registers. These values are with respect to the read port widths. the embedded output registers in the block RAM primitives are used if the user chooses to register the output of the memory primitives.

Select for each port (A or B) to insert a register on the output of the memory core for that port. the COE file and the default value are with respect to the port A write width. Note that in Virtex-4 devices. 1. and whether to initialize the remaining memory contents with a default value. When selected. or 3 from the drop-down list. Select to use a separate REGCEA or REGCEB input pin to control the enable of the last output register stage in the memory. Available only when the Register Output of Memory Core option is selected for both port A and port B and when the constructed memory has more than one primitive in depth.com 31 . The MUX size displayed in the GUI can be used to determine the number of pipeline stages to use within the MUX. Select a value of 0. • Register Port [A|B] Output of Memory Core. all register stages are enabled by ENA/ENB. Memory Initialization Select whether to initialize the memory contents using a COE file. When using asymmetric port widths or data widths. registers are implemented using FPGA slices to register the core's output. DS512 September 19. so that a MUX is needed at the output.Block Memory Generator v2. 2. • Pipeline Stages within Mux.xilinx. See "Output Register Configurations" on page 47 for more information. When unselected. however. • Use REGCE [A|B] Pin. Select the appropriate number of pipeline stages for your design based on the device architecture. the use of the SSR input prevents the core from using the embedded output registers. See "Output Register Configurations" on page 47 for more information. Selecting this option causes the Block Memory Generator to use the embedded output registers in the Spartan-3A DSP RAMB16BWER primitives. • Use Reset Behavior from RAMB16BWER Primitive. 2008 Product Specification www. it also changes the behavior of the core during reset.8 used.

2008 Product Specification . Behavioral Simulation Model Options Select the type of warning messages generated by the behavioral simulation model. each 36k block RAM primitive is counted as two 18k block RAMs. Information Section This section displays an informational summary of the selected core options. Select whether the model should assume synchronous clocks for collision warnings. • Memory Type: Reports the selected memory type.com DS512 September 19. This value is 32 www. For Virtex-5 devices.xilinx.Block Memory Generator v2.8 Simulation Model Options and Information Screen Figure Top x-ref 27 Figure 27: Simulation Model Options and Information Screen Structural/UNISIM Simulation Model Options Select the type of warning messages and outputs generated by the structural simulation model in the event of collisions. • Block RAM Resources (18k Block RAMs): Reports the exact number of 18k block RAM primitives which will be used to construct the core. • Total Port A Read Latency: The number of clock cycles for a read operation for port A.

com 33 . for a memory configuration of 2kx72. . more primitives are needed to cover the remaining width. For example. Sample initialization file for a . To estimate this value when using the fixed primitive algorithm. A COE is a text file which specifies two parameters: • memory_initialization_radix: The radix of the values in the memory_initialization_vector. This number is always given as the number of 18k block RAM primitives used. separated by a space. Specifying Initial Memory Contents The Block Memory Generator core supports memory initialization using a memory coefficient (COE) file or the default data option in the CORE Generator GUI. The following is an example COE file. • memory_initialization_vector: Defines the contents of each memory element. 32-bit wide by 16 deep RAM memory_initialization_radix = 16. To estimate block RAM usage when using the low power algorithm requires a few more calculations: • If the memory width is an integral multiple of the width of the widest available primitive for the chosen architecture. COE files and default data is formatted with respect to the port A write width (or port A read width for ROMs).Block Memory Generator v2. The COE file can specify the initial contents of each memory location. Block RAM Usage The Information panel (screen 5 of the Block Memory Generator GUI) reports the actual number of block RAM blocks to be used. • Address Width: The actual width of the address bus to each port. and assumed to be in the radix defined by memory_initialization_radix. 10. the COE file can specify a portion of the memory space. or a combination of both. 2008 Product Specification www. Note that semi-colon is the end of line character. This value is controlled by the optional output registers options for port B on the previous screen. • If the memory width is greater than an integral multiple of the widest primitive. the total available primitives used is 8.xilinx. the width ratio is 2 and the depth ratio is 4 using the widest primitive of 512x36. Valid choices are 2. When used in tandem. where the width ratio is the width of the memory divided by the width of the selected primitive. As a result. then the number of primitives used is calculated in the same way as the fixed primitive algorithm. and the depth ratio is the depth of the memory divided by the depth of the primitive selected. while default data specifies the contents of all memory locations. Each value is LSB-justified. The width and depth ratios are calculated using the width and depth of the widest primitive. the number of block RAM primitives used is equal to the width ratio (rounded up) multiplied by the depth ratio (rounded up). • Total Port B Read Latency: The number of clock cycles for a read operation for port B.8 controlled by the optional output registers options for port A on the previous screen. then in addition to the above calculated primitives. This additional number is obtained by dividing the memory depth by the depth of the additional DS512 September 19. memory_initialization_vector = 0 1 2 3 4 5 6 7 8 9 A B C D E F. while default data fills the rest of the remaining memory space. or 16.

which are implemented in the FPGA fabric. Given that this algorithm packs block RAMs very efficiently. Better performance may be possible with higher speed grades. the number of primitives cascaded in depth to implement a memory determines the size of the output multiplexer and the size of the input decoder. Particularly. this estimate is often very accurate for most memories. The optimistic estimate is total memory bits divided by 18k (the total number of bits per primitive) rounded up. performance may vary depending on the user design. When using the minimum area algorithm. it is not as easy to determine the exact block RAM count. As a result. Note: Although the primary goal of the minimum area algorithm is to use the minimum number of block RAM primitives. 34 www. and the subsequent performance improvement that may result. To cover the depth of 17K. In the benchmark designs described below. and a Virtex-5 FPGA in the -1 speed grade (5vlx30-ff324-1). This is because the actual algorithms perform complex manipulations to produce optimal solutions. • If the memory width is less than the width of the widest primitive.xilinx. 34 512x36 primitives and 2 16kx1 primitives are needed. Each section highlights the effects of a specific feature on resource utilization and performance. the total number of primitives used for this configuration is 36. the core was encased in a wrapper with input and output registers to remove the effects of IO delays from the results. the chosen primitive is 512x36. Benchmarks were performed targeting a Virtex-II Pro FPGA in the -5 speed grade (2vp30-ff1152-5).Block Memory Generator v2. For example. then the smallest possible primitive that covers the memory width is chosen for the solution. and an additional 16kx1 primitive to cover the remaining width of 1. The minimum area algorithm was used unless otherwise noted. The examples below highlight the use of embedded registers in Virtex-5 and Virtex-4 devices. which is 4. Resource Utilization and Performance Examples The following tables provide examples of actual resource utilization and performance for Block Memory Generator implementations.8 primitive chosen to cover the remaining width. LUT Utilization and Performance The LUT utilization and performance of the core are directly related to the arrangement of primitives and the selection of output registers. For example. 2008 Product Specification . for a memory configuration of 2kx32.com DS512 September 19. and the total number of primitives used is 2k divided by 512. and a Virtex-4 FPGA in the -10 speed grade (4vlx60-ff1148-10). it has a secondary goal of maximizing performance – as long as block RAM usage does not increase. a memory configuration of 17kx37 requires one 512x36 primitive to cover the width of 36. The total number of primitives used is obtained by dividing the memory depth by the depth of the chosen primitive.

com 35 . DS512 September 19. 2008 Product Specification www. and do not reflect the number of LUTs used as a route-through. Table 5 and Table 6 define performance data for single-primitive memories.xilinx.Virtex-5 Memory Type Options Width x Depth 36x512 9x2k Resource Utilization Block RAMs 1 1 1 1 Performance (MHz) Virtex-5 300 300 395 455 Shift Regs 0 0 0 0 FFs 0 0 0 0 LUTs1 0 0 0 0 True Dual-port RAM Virtex-4 or Virtex-5 Embedded Output Registers 36x512 9x2k 1.8 Single Primitive The Block Memory Generator does not add additional logic if the memory can be implemented in a single block RAM primitive. LUTs are reported as the number of 4-input LUTs. and do not reflect the number of LUTs used as a route-through. Table 6: Single Primitive Examples .Virtex-4 and Virtex-II Pro Memory Type Options Width x Depth 36x512 9x2k Resource Utilization Block RAMs 1 1 1 1 Performance (MHz) Virtex-II Pro 330 345 N/A N/A Shift Regs 0 0 0 0 FFs 0 0 0 0 LUTs1 0 0 0 0 Virtex-4 310 335 385 395 True Dual-port RAM Virtex-4 or Virtex-5 Embedded Output Registers 36x512 9x2k 1. LUTs are reported as the number of 4-input LUTs. Table 5: Single Primitive Examples .Block Memory Generator v2.

the performance of shift registers is worse than flip flops. In a full-scale user design. when output registers are used. For Virtex-II Pro devices. reducing the FPGA fabric resources required to create the registers.com DS512 September 19. LUTs are reported as the number of 4-input LUTs. Table 7: Virtex-II Pro Output Register Examples Memory Type Width x Depth Output Register Option Virtex-II Pro Block RAMs 5 Shift Regs 0 6 6 6 0 3 0 2 FFs 6 92 40 126 3 46 22 66 LUTs1 60 66 142 148 30 33 30 32 Performance (MHz) 325 300 300 300 325 300 350 300 True Dual-port RAM Primitive 17x5k Core Primitive. Table 8: Virtex-4 Output Register Examples Memory Type Width x Depth Output Register Option Virtex-4 Block RAMs 5 Shift Regs 0 6 0 6 0 3 0 2 FFs 6 6 40 40 3 3 20 22 LUTs1 60 66 142 148 30 33 30 32 Performance (MHz) 275 425 250 375 275 425 275 450 True Dual-port RAM Primitive 17x5k Core Primitive. 36 www. core output registers may improve performance notably. Core 5 5 5 1.8 Output Registers The Block Memory Generator optional output registers increase the performance of memories by isolating the block RAM primitive clock-to-out delays and the data output multiplexer delays. and do not reflect the number of LUTs used as a route-through. In Virtex-4 architectures. For this reason. Core 5 5 5 5 Single-port RAM Primitive 17x5k Core Primitive. So. The output registers are only implemented for output ports. Core 5 5 5 5 Single-port RAM Primitive 17x5k Core Primitive. LUTs are reported as the number of 4-input LUTs. Note that the effects of the core output registers are not fully illustrated due to the simple register wrapper used.Block Memory Generator v2. and do not reflect the number of LUTs used as a route-through. Core 5 5 5 1.xilinx. the embedded block RAM may be utilized. a Single-port RAM requires fewer resources than a True Dual-port RAM. 2008 Product Specification . and a configuration with no output registers gives a slightly better performance than a configuration with output registers. the shift registers used for registering the MUX select lines is the main performance bottleneck.

which can reduce packing efficiency. because aspect ratios limit the primitive types available to the algorithm. write port is 17x5k. 2. and do not reflect the number of LUTs used as a route-through. and do not reflect the number of LUTs used as a route-through. 3.xilinx. DS512 September 19. write port is 136x640. the embedded block RAM may be used to reduce the FPGA fabric resources required to create the registers. Read port is 17x5k.8 In Virtex-5 FPGA architectures. and do not reflect the number of LUTs used as a route-through. LUTs are reported as the number of 4-input LUTs. such as 1:32. 2. Read port is 136x640.com 37 .Block Memory Generator v2. have a greater impact than small aspect ratios. Core 3 3 3 1. B port is 17x5k. Core 3 3 3 3 Single-port RAM Primitive 17x5k Core Primitive. Large aspect ratios. Table 11: Virtex-4 Aspect Ratio Memory Type Width x Depth Data Width Aspect Ratio 1:1 Virtex-4 Block RAMs 5 9 9 Shift Regs 0 0 0 FFs 3 0 0 LUTs1 30 0 0 Performance (MHz) 275 300 350 Single-port RAM 17x5k 136x640 1:82 8:13 1. A port is 136x640. Table 9: Virtex-5 Output Register Examples Memory Type Width x Depth Output Register Options Virtex-5 Block RAMs 3 Shift Regs 0 6 0 6 0 3 0 3 FFs 6 6 40 40 3 3 20 20 LUTs1 36 42 36 42 18 21 18 21 Performance (MHz) 300 525 300 500 275 475 300 500 True Dual-port RAM Primitive 17x5k Core Primitive. LUTs are reported as the number of 4-input LUTs. Table 10: Virtex-II Pro Aspect Ratio Memory Type True Dual-port RAM Width x Depth 17x5k 136x640 Port Aspect Ratio 1:1 1:82 Virtex-II Pro Block RAMs 5 9 Shift Regs 0 0 FFs 6 0 LUTs1 60 0 Performance (MHz) 275 275 1. Aspect Ratios The Block Memory Generator selectable port and data width aspect ratios may increase block RAM usage and affect performance. Note that width and depth are reported with respect to the port A write interface. LUTs are reported as the number of 4-input LUTs. 2008 Product Specification www.

Algorithm The differences between the minimum area. Read port is 17x5k. LUTs are reported as the number of 4-input LUTs.8 Table 12: Virtex-5 Aspect Ratio Memory Type Width x Depth Virtex-5 Aspect Ratio 1:1 Block RAMs 3 5 5 Shift Regs 0 0 0 FFs 3 0 0 LUTs1 18 0 0 Performance (MHz) 275 275 2754 Single-port RAM 17x5k 136x640 1:82 8:13 1. Table 13: Memory Algorithm Examples Virtex-II Pro and Virtex-4 Memory Type Width x Depth Algorithm Type Minimum area Resource Utilization Block RAM 5 5 5 8 8 8 Performance (MHz) Virtex-II Pro 300 225 225 300 225 225 Shift Regs 0 0 0 0 0 0 FFs 3 3 3 1 3 3 LUTs1 30 57 57 36 152 152 Virtex-4 275 225 225 300 225 225 17x5k Fixed Primitive using 18x1k block RAM Low power Minimum area Single-por t RAM 36x4k Fixed Primitive using 36x512 block RAM Low power 1. 2. low power and fixed primitive algorithms are discussed in detail in "Selectable Memory Algorithm" on page 2. write port is 17x5k.Block Memory Generator v2. and do not reflect the number of LUTs used as a route-through. 2008 Product Specification . 3. 38 www. Read port is 136x640. 4.xilinx.com DS512 September 19. and do not reflect the number of LUTs used as a route-through. This configuration was generated using the xc5vlx50-ff676-1 part. Table 13 shows examples of the resource utilization and the performance difference between them for two selected configurations for Virtex-II Pro and Virtex-4 FPGA architectures. write port is 136x640. LUTs are reported as the number of 4-input LUTs.

Block Memory Generator v2.8 Table 14 shows examples of the resource utilization and the performance difference between them for two selected configurations for Virtex-5 FPGA architecture. 2008 Product Specification www.com 39 . and do not reflect the number of LUTs used as a route-through.xilinx. DS512 September 19. Table 14: Memory Algorithm Examples Virtex-5 Memory Type Width x Depth Algorithm Type Minimum area Resource Utilization Block RAM 3 3 3 4 4 4 Performance (MHz) Virtex-5 275 300 300 300 275 275 Shift Regs 0 0 0 0 0 0 FFs 3 3 3 0 2 2 LUTs1 18 30 20 0 40 40 17x5k Fixed Primitive using 18x1k block RAM Low power Minimum area Single-por t RAM 36x4k Fixed Primitive using 36x512 block RAM Low power 1. LUTs are reported as the number of 4-input LUTs.

com DS512 September 19. handshaking. To help you migrate designs containing legacy LogiCORE IP v6. • Dual Port Block Memory core and the Block Memory Generator do not have the same reset pin name. • Construction of Smaller Memories: Explains the process of creating shallower or wider memories using dual port block memory. write-only. • Pin polarity. Some of these combination are only available in the Block Memory Generator by manually tying-off unused ports of a True Dual-port RAM. • Single Port Block Memory core and the Block Memory Generator do not have the same port names for a single-port memory configuration. and input register features supported by the previous memory cores are not supported in the Block Memory Generator.x) Cores generated by the Block Memory Generator are not drop-in replacements for the v6. • The Dual-port Block Memory core supports all combinations of read-only. 40 www. The new Block Memory Generator is not backward compatible with the Single and Dual Port Block Memory core in several aspects.Block Memory Generator v2. • XCO files for the previous memory cores are NOT compatible with the Block Memory Generator. Compatibility with Older Memory Cores This section contains important information for users working with a previous version of the Block Memory Generator core. Xilinx provides the Block Memory Generator Migration Kit to manage migration-related tasks without manually editing your design.x cores listed above as there are a number of feature and interface changes in the Block Memory Generator. • The behavior of set/reset pin (SSR) and the enable pin (EN) in the Block Memory Generator will differ from previous cores when using optional output registers. Differences Between Cores This section describes the differences between the Single and Dual Port Block Memory cores and the Block Memory Generator. 2008 Product Specification . For information about using the Migration Kit.x) • Single Port Block Memory (v6.xilinx. • Compatibility with Older Memory Cores: Defines the differences between older memory cores and the Block Memory Generator core. • SIM Parameters: Defines the SIM parameters used to specify the core configuration. Using the Block Memory Generator Migration Kit The Block Memory Generator core replaces the following legacy cores: • Dual Port Block Memory (v6.x Dual and Single Port Block Memory cores to the new Block Memory Generator core. and read/write ports for A & B ports. see the Block Memory Generator Migration Kit Product Page. • Output Register Configurations: Provides information optional output registers used to improve core performance.8 Supplemental Information The following sections provide additional information about working with the Block Memory Generator core.

2008 Product Specification www.8 Note: The Block Memory Migration Kit automatically ties-off the appropriate ports when used to migrate from a Dual-port Block Memory core. users can invert the signals prior to the input of the core. DS512 September 19.xilinx. Single Port Configuration) DIN ADDR EN WE SINIT CLK DOUT ND RFD RDY DINA ADDRA ENA WEA SSRA CLKA DOUTA Not supported Not supported Not supported Table 16: Port Name Changes from Dual Port Block Memory Core Dual Port Block Memory v6. RFD[A|B] and RDY[A|B].2 (Old core) Block Memory Generator v2. Table 15 and Table 16 reflect the changes in port names. the port names have been changed from the older Single Port Block Memory and Dual Port Block Memory cores to reflect the actual ports on the block RAM primitives. Port Memory Pin Names In the Block Memory Generator.1 (New Core. Single Port Configuration) SINITA SINITB ND [A|B] RFD [A|B] RDY [A|B] SSRA SSRB Not supported Not supported Not supported Obsolete Features Pin Polarity Option The Block Memory Generator does not support pin polarity options on the clock.com 41 .2 (Old core) Block Memory Generator v2. enable. When active low signaling is desired. write enable and set/reset input pins.Block Memory Generator v2. Handshaking Pins The Block Memory Generator does not support handshaking pins: ND[A|B].1 (New Core. Table 15: Port Name Changes from Single Port Block Memory Core Single Port Block Memory v6.

Use a True Dual-port RAM type and manually tie-off unused ports to achieve configurations with only one write-only or read-only port. This feature can be used only for memories that are atmost one primitive deep. and read/write ports for ports A & B. write-only. Table 17: Old and New Core Differences Single (or Dual) Port Block Memory v6. In the Block Memory Generator. Modified Behaviors Enable Pin Table 17 illustrates the difference in enable behavior between previous cores and the Block Memory Generator. In this configuration. When there are no output register stages present.2 Block Memory Generator v2. the MSB of ADDRA is connected to ’0’ and the MSB of ADDRB is connected to ’1’.1 Two optional enable pins provided: Single enable pin that controls the enables of all registers and memories • REGCE—optionally controls the enables of the registers in the last output stage • EN—controls the enables of all other registers and memory Synchronous Reset Pin In the previous memory cores.com DS512 September 19. 2008 Product Specification . and port B is a single-port memory addressing memory locations 128-255. the input COE file should contain 256 32-bit 42 www. it will initialize the memory latches. While initializing such a memory. consider the construction of two independent 128x32 memories using a single 256x32 memory. where port A is a single-port memory addressing memory locations 0-127.8 Input Registers The Block Memory Generator does not support input registers on the DIN. the synchronous set/reset (SSR pin) only resets the registers in the last output stage. This effectively turns a True Dual Port 256x32 memory (with both A and B ports sharing the same memory space) into two single-port 128x32 memories. the synchronous reset (SINIT pin) initializes all memory latches and output registers. in a single block RAM primitive.Block Memory Generator v2. Note: The Block Memory Generator Migration Kit automatically ties-off appropriate ports when used to migrate from a Dual-port Block Memory core. and WE input ports. This can be achieved by tying the MSB of the address of one port to ’0’ and the MSB of the address of the second port to ’1’. Construction of Smaller Memories A single memory of a given depth can be used to construct two independent memories of half the depth. Generate a 256x32 True Dual Port memory core in Core Generator using the desired parameters. Once generated. Read/Write Ports The Block Memory Generator does not support all combinations of read-only. As an example.xilinx. the two 128x32 memories function completely independent of each other. ADDR.

as shown in Figure 28. Alternately. DS512 September 19.com 43 .xilinx. 2008 Product Specification www. for example 23 words. the widths of both ports A and B can be set to 19 in the Core Generator GUI. The COE entries must then be just 19 bits wide. simply use the first 23 entries in the memory. For construction of memories shallower than 128 words. Figure Top x-ref 28 32 0 8 7 DINA ADDRA WEA ENA CLKA 32 32 DOUTA 256x32 32 1 8 7 DINB ADDRB WEB ENB CLKB DOUTB 256x32 Figure 28: Construction of two independent 128x32 memories using a single 256x32 memory For construction of memories narrower than 32-bits. a 32-bit wide memory may be generated.8 wide entries. The first 128 entries initialize memory A. while the second 128 entries initialize memory B. Alternately. and only the least significant 19 bits may be used. use the same strategy as above to turn a True Dual Port 64-word deep memory into two 32-word deep memories. tying off the unused address bits to ’0’. The cores are then connected the same way.Block Memory Generator v2. for example 19 bits. COE entries in this case will be trimmed or padded with 0s automatically to fill the appropriate number of bits.

1 (minimum area). determines which type of primitive to use to build memory 6 7 C_BYTE_SIZE C_SIM_COLLISION_CHECK Integer String Defines size of a byte: 9 bits or 8 bits Defines warning collision checks in structural/unisim simulation model Determines whether to optimize behavioral model collision check by assuming clocks are synchronous Disables the behavioral model from generating warnings due to read-write collisions Disables the behavioral model from generating warnings due to address out of range Defined whether to load initialization file Name of initialization file (MIF format) Determines whether to use default data for the memory Defines a default data for the memory 8 C_COMMON_CLOCK Integer 9 C_DISABLE_WARN_BHV_COLL Integer 0. 1 10 C_DISABLE_WARN_BHV_RANGE Integer 0. single-port only) 9.Block Memory Generator v2. 1 “…” 44 www. Generate_X. Warnings_only 0. All. This parameter list does not apply to users that generate the core using the CORE Generator GUI. 1 “…” 0. 1 11 12 13 14 C_LOAD_INIT_FILE C_INIT_FILE_NAME C_USE_DEFAULT_DATA C_DEFAULT_DATA Integer String Integer String 0.xilinx. These parameters are only used to manually instantiate the core in HDL.com DS512 September 19. 2 (low power) 0 (1-bit wide) 1 (2-bit wide) 2 (4-bit wide) 3 (9-bit wide) 4 (18-bit wide) 5 (36-bit wide) 6 (72-bit wide. 2008 Product Specification . Table 18: SIM Parameters SIM Parameter 1 C_FAMILY Type String Values “Virtex2” “Virtex4” “Virtex5” "Virtex-II" "Virtex-II Pro" "Virtex4" "Virtex5" "Spartan-3A" "Spartan-3A DSP" 0: Single Port RAM 1: Simple Dual Port RAM 2: True Dual Port RAM 3: Single Port ROM 4: Dual Port RAM 0 (selectable primitive). calling the CORE Generator dynamically. 1 Description Target device family 2 C_XDEVICEFAMILY String Finest resolution target family derived from the parent C_FAMILY 3 C_MEM_TYPE Integer Type of memory 4 C_ALGORITHM Integer Type of algorithm 5 C_PRIM_TYPE Integer If fixed primitive algorithm is chosen.8 SIM Parameters Table 18 defines the SIM parameters used to specify the configuration of the core. 8 None.

1 31 32 33 34 35 36 C_WEA_WIDTH C_WRITE_WIDTH_B C_READ_WIDTH_B C_WRITE_DEPTH_B C_READ_DEPTH_B C_ADDRB_WIDTH Integer Integer Integer Integer Integer Integer 1 to 128 1 to 1152 1 to 1152 2 to 9011200 2 to 9011200 1 to 24 DS512 September 19.2.1 19 20 21 22 23 24 25 C_MUX_PIPELINE_STAGES C_WRITE_WIDTH_A C_READ_WIDTH_A C_WRITE_DEPTH_A C_READ_DEPTH_A C_ADDRA_WIDTH C_WRITE_MODE_A Integer Integer Integer Integer Integer Integer String 0. 2008 Product Specification www.com 45 . since there is only a single byte write enable option provided Defines width of WEA pin for port A Defines width of write port B Defines width of read port B Defines depth of write port B Defines depth of read port B Defines the width of address B 16 C_HAS_MEM_OUTPUT_REGS_B Integer 0.3 1 to 1152 1 to 1152 2 to 9011200 2 to 9011200 1 to 24 Write_First. 1 Values Description Determines whether port A has a register stage added at the output of the memory latch Determines whether port B has a register stage added at the output of the memory latch Determines whether port A has a register stage added at the output of the memory core Determines whether port B has a register stage added at the output of the memory core Determines the number of pipeline stages within the MUX for both port A and port B Defines width of write port A Defines width of read port A Defines depth of write port A Defines depth of read port A Defines the width of address A Defines the write mode for port A Determines whether port A has an enable pin Determines whether port A has an enable pin for its output register Determines whether port A has an synchronous reset pin Defines initialization/power-on value for port A output Determines whether byte-write feature is used on port A For True Dual Port configurations. 1 0.1.1 17 C_HAS_MUX_OUTPUT_REGS_A Integer 0. Read_first. 1 “…” 26 27 28 29 C_HAS_ENA C_HAS_REGCEA C_HAS_SSRA C_SINITA_VAL Integer Integer Integer String 30 C_USE_BYTE_WEA Integer 0. No_change 0. this value is the same as C_USE_BYTE_WEB.8 Table 18: SIM Parameters (Continued) SIM Parameter 15 C_HAS_MEM_OUTPUT_REGS_A Type Integer 0.Block Memory Generator v2.xilinx.1 18 C_HAS_MUX_OUTPUT_REGS_B Integer 0. 1 0.

1 0.xilinx. Read_first.1 45 C_USE_RAMB16BWER_RST_BHV Integer 0. 2008 Product Specification . 1 “…” Description Defines the write mode for port B Determines whether port B has an enable pin Determines whether port B has an enable pin for its output register Determines whether port B has an synchronous reset pin Defines initialization/power-on value for port B output Determines whether byte-write feature is used on port B This value is the same as C_USE_BYTE_WEA. No_change 0. 1 43 44 C_WEB_WIDTH C_USE_ECC Integer Integer 1 to 128 0.Block Memory Generator v2.com DS512 September 19.1 46 www. since there is only a single byte write enable provided Defines width of WEA pin for port B Determines ECC options 0 = No ECC 1 = ECC Determines if the embedded registers in Spartan-3A DSP RAMB16BWER primitives are used 38 39 40 41 C_HAS_ENB C_HAS_REGCEB C_HAS_SSRB C_SINITB_VAL Integer Integer Integer String 42 C_USE_BYTE_WEB Integer 0. 1 0.8 Table 18: SIM Parameters (Continued) SIM Parameter 37 C_WRITE_MODE_B Type String Values Write_First.

8 Output Register Configurations The Block Memory Generator core provides optional output registers that can be selected for port A and port B separately. Figure Top x-ref 29 Port A Options Port B Options Figure 29: Optional Output Registers Section DS512 September 19. and Spartan-3A DSP FPGA block RAM primitives have embedded output registers that previous architectures did not support.Block Memory Generator v2. the configurations described in the sections that follow are separated into Virtex-4 and Virtex-5 devices. and that may improve the performance of the core. Figure 29 shows the Optional Output Registers section of the Block Memory Generator GUI.com 47 . and Virtex-II device and implementations.xilinx. Virtex-4. Because Virtex-5. 2008 Product Specification www. Spartan-3A DSP device.

Port A or Port B Register Port A Output of Memory Primitives Register Port A Output of Memory Core Figure Top x-ref 30 Register Port B Output of Memory Primitives Register Port B Output of Memory Core Block Memory Generator Core Block RAM Primitives Block RAM Block RAM LaL tche atche s s Embedded Output Registers Embedded Output Registers Embedded Output Registers Core Output Registers MUX D CE S* Q Block RAM Latches Latches DOUT SSR* D CE SSR* CE Latches Q CE CLK Use REGCE Pin EN REGCE SSR FALSE TRUE S* : The synchronous reset (S) of the flop is gated by CE Figure 30: Virtex-4 or Virtex-5 FPGA Block Memory Generated with Register Port [A|B] Output of Memory Primitives and Register Port [A|B] Output of Memory Core Enabled 48 www. Figures 30 through 35 illustrate the Virtex-5 and Virtex-4 FPGA output register configurations.xilinx. are provided. Similarly. one each for port A and port B.com DS512 September 19. a memory core is generated with both the Virtex-4 or Virtex-5 FPGA embedded output registers and a register on the output of the core for the selected port(s).8 Virtex-5 and Virtex-4 FPGA: Output Register Configurations To tailor register options for Virtex-5 and Virtex-4 FPGA configurations.Block Memory Generator v2. as shown in Figure 30. two selections. registers at the output of the core are enabled for the corresponding port(s) by selecting Register Port [A|B] Output of Memory Core. This configuration may provide improved performance for building large memory constructs. The embedded output registers are enabled for the corresponding port(s) when Register Port [A|B] Output of Memory Primitives is selected. 2008 Product Specification . Virtex-5 and Virtex-4 FPGA: Memory with Primitive and Core Output Registers With both Register Output of Memory Primitives and Register Output of Memory Core options selected.

xilinx. these registers are always implemented using the output registers embedded in the Virtex-5 FPGA block RAM architecture. 2008 Product Specification www. a memory core that registers the output of the block RAM primitives for the selected port(s) is generated. The output of any multiplexing that may be required to combine multiple primitives is not registered in this configuration. Port A or Port B Register Port A Output of Memory Primitives Register Port A Output of Memory Core Figure Top x-ref 31 Register Port B Output of Memory Primitives Register Port B Output of Memory Core Block Memory Generator Core Block RAM Primitives Block RAM Block RAM LaL tche atche s s Embedded Output Registers Embedded Output Registers Embedded Output Registers Block RAM Latches Latches MUX DOUT SSR* D CE SSR* S* CE Latches Q CE CLK Use REGCE Pin EN REGCE SSR FALSE TRUE S* : The synchronous reset (S) of the flop is gated by CE Figure 31: Virtex-5 FPGA Block Memory Generated with Register Port [A|B] Output of Memory Primitives Enabled DS512 September 19. as shown in Figure 31.com 49 .Block Memory Generator v2.8 Virtex-5 FPGA: Memory with Primitive Output Registers When Register Port [A|B] Output of Memory Primitives is selected. In Virtex-5 devices.

Block Memory Generator v2.8

Virtex-4 FPGA: Memory with Primitive Output Registers without SSR When Register Port [A|B] Output of Memory Primitives is selected and the corresponding Use SSR [A|B] Pin (set/reset pin) is unselected, a memory core that registers the output of the block RAM primitives for the selected port(s) using the output registers embedded in Virtex-4 FPGA architecture is generated. The output of any multiplexing that may be required to combine multiple primitives is not registered in this configuration, as shown in Figure 32.
Port A or Port B

Register Port A Output of Memory Primitives Register Port A Output of Memory Core Use SSRA Pin (set/reset pin)
Figure Top x-ref 32

Register Port B Output of Memory Primitives Register Port B Output of Memory Core Use SSRB Pin (set/reset pin)

Block Memory Generator Core Block RAM Primitives Block RAM Block RAM
LaL tche atche s s Embedded Output Registers Embedded Output Registers Embedded Output Registers

Block RAM
Latches Latches

MUX

D

SSR* SSR*
D

CE

Latches

CE

Q

CE

CLK

Use REGCE Pin

EN REGCE

FALSE TRUE

Figure 32: Virtex-4 Block Memory Generated with only Register Port [A | B] Output of Memory Primitives Enabled

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DS512 September 19, 2008 Product Specification

Block Memory Generator v2.8

Virtex-4 FPGA: Memory with Primitive Output Registers with SSR If either Use SSRA Pin (set/reset pin) or Use SSRB Pin (set/reset pin) is selected from the Output Reset section of the Port Options screen(s), the Virtex-4 embedded block RAM registers cannot be used for the corresponding port(s). The primitive output registers are built from FPGA fabric, as shown in Figure 33.
Port A or Port B

Register A Output of Memory Primitives Register A Output of Memory Core Use SSRA Pin (set/reset pin)
Figure Top x-ref 33

Register B Output of Memory Primitives Register B Output of Memory Core Use SSRB Pin (set/reset pin)

Block Memory Generator Core Block RAM Primitives Block RAM Block RAM
Latches Latches Embedded Output Registers N/A Embedded Output Registers N/A Embedded Output Registers N/A

Primitive Output Registers
D CE S* D CE S* Q Q

Block RAM
Latches Latches

MUX

DOUT

SSR*

CE

SSR*

CE

Latches

D CE S*

Q

CLK

Use REGCE Pin

EN REGCE SSR

FALSE TRUE

S* : The synchronous reset (S) of the flop is gated by CE

Figure 33: Virtex-4 Block Memory Generated with Register Output of Memory Primitives and Use SSR[A|B] Pin Options Enabled

DS512 September 19, 2008 Product Specification

www.xilinx.com

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Block Memory Generator v2.8

Virtex-5 and Virtex-4 FPGA: Memory with Core Output Registers When only Register Port [A|B] Output of Memory Core is selected, the Virtex-5/Virtex-4 device’s embedded registers are disabled for the selected ports in the generated core, as shown in Figure 34.
Port A or Port B

Register Port A Output of Memory Primitives Register Port A Output of Memory Core
Figure Top x-ref 34

Register Port B Output of Memory Primitives Register Port B Output of Memory Core

Block Memory Generator Core Block RAM Primitives Block RAM Block RAM
Latches Latches Embedded Output Registers N/A Embedded Output Registers N/A Embedded Output Registers N/A

Core Output Registers MUX
D CE S* Q

Block RAM
Latches Latches

DOUT

SSR*

CE

Latches

CLK

SSR*
Use REGCE Pin

EN REGCE SSR

CE

FALSE TRUE

S* : The synchronous reset (S) of the flop is gated by CE

Figure 34: Virtex-4 or Virtex-5 FPGA Block Memory Generated with Register Port [A|B] Output of Memory Core Enabled

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DS512 September 19, 2008 Product Specification

2008 Product Specification www. but the clock-to-out delay for a read operation can impact design performance.xilinx. there are no additional clock cycles of latency. output of the memory primitives is driven directly from the RAM primitive latches. as shown in Figure 35.8 Virtex-5 and Virtex-4 FPGA: Memory with No Output Registers If neither of the output registers is selected for ports A or B.Block Memory Generator v2.com SSR* CE 53 . In this configuration. Port A or Port B Register Port A Output of Memory Primitives Register Port A Output of Memory Core Figure Top x-ref 35 Register Port B Output of Memory Primitives Register Port B Output of Memory Core Block Memory Generator Core Block RAM Primitives Block RAM Block RAM Latches Latches Embedded Output Registers N/A Embedded Output Registers N/A Embedded Output Registers N/A SSR* CE Block RAM Latches Latches MUX DOUT Latches CLK EN SSR Figure 35: Virtex-4 or Virtex-5 Block Memory Generated with No Output Registers Enabled DS512 September 19.

two selections each. For detailed information. but changes the behavior of the core. Selecting this option forces the core to use the Spartan-3A DSP embedded output registers. 2008 Product Specification . for port A and port B. Figures 36 through 41 illustrate the Spartan-3A DSP output register configurations. Similarly. The embedded output registers for the corresponding port(s) are enabled when Register Port [A|B] Output of Memory Primitives is selected.8 Spartan-3A DSP FPGA: Output Register Configurations To tailor register options for Spartan-3A DSP device configurations. the User Reset Behavior from RAMB16BWER Primitive becomes available.xilinx. are provided on screen 4 of the CORE Generator GUI in the Optional Output Registers section. see the sections that follow. When only Register Port [A|B] Output of Memory Primitives and the corresponding Use SSR[A|B] Pin (set/reset pin) is selected.Block Memory Generator v2. 54 www. registers at the output of the core for the corresponding port(s) are enabled by selecting Register Port [A|B] Output of Memory Core.com DS512 September 19.

as shown in Figure 36. a memory core is generated with both the Spartan-3A DSP embedded output registers and a register on the output of the core for the selected port(s). Port A or Port B Register Port A Output of Memory Primitives Register Port A Output of Memory Core Figure Top x-ref 36 Register Port B Output of Memory Primitives Register Port B Output of Memory Core Block Memory Generator Core Block RAM Primitives Block RAM Block RAM LaL tche atche s s Embedded Output Registers Embedded Output Registers Embedded Output Registers Core Output Registers MUX D CE S* Q Block RAM Latches Latches DOUT SSR* D CE SSR* CE Latches Q CE CLK Use REGCE Pin EN REGCE SSR FALSE TRUE S* : The synchronous reset (S) of the flop is gated by CE Figure 36: Spartan-3A DSP Block Memory Generated with Register Port [A|B] Output of Memory Primitives and Register Port [A|B] Output of Memory Core Enabled DS512 September 19. This configuration may improve performance when building a large memory construct.xilinx.8 Spartan-3A DSP FPGA: Memory with Primitive and Core Output Registers With both Register Port [A|B] Output of Memory Primitives and the corresponding Register Port [A|B] Output of Memory Core selected.Block Memory Generator v2.com 55 . 2008 Product Specification www.

Block Memory Generator v2. a memory core that registers the output of the block RAM primitives for the selected port using the output registers embedded in Spartan-3A DSP FPGA architecture is generated.com DS512 September 19. and the corresponding Use SSR Pin (set/reset pin) is not selected.xilinx. The output of any multiplexing that may be required to combine multiple primitives is not registered in this configuration (Figure 37). 2008 Product Specification . Port A or Port B Register Port A Output of Memory Primitives Register Port A Output of Memory Core Use SSRA Pin (set/reset pin) Figure Top x-ref 37 Register Port B Output of Memory Primitives Register Port B Output of Memory Core Use SSRB Pin (set/reset pin) Block Memory Generator Core Block RAM Primitives Block RAM Block RAM LaL tche atche s s Embedded Output Registers Embedded Output Registers Embedded Output Registers Block RAM Latches Latches MUX DOUT SSR* SSR* D CE Latches CE Q CE CLK Use REGCE Pin EN REGCE FALSE TRUE Figure 37: Spartan-3A DSP Block Memory Generated with Register Port [A|B] Output of Memory Primitives Enabled (No SSR) 56 www.8 Spartan-3A DSP FPGA: Memory With Primitive Output Registers – Without SSR Pin When Register Port [A|B] Output of Memory Primitives is selected.

xilinx.8 Spartan-3A DSP FPGA: Memory with Primitive Output Registers. Port A or Port B Register Port A Output of Memory Primitives Register Port A Output of Memory Core Use SSRA Pin (set/reset pin) Use Reset Behavior from RAMB16BWER Primitive Figure Top x-ref 38 Register Port B Output of Memory Primitives Register Port B Output of Memory Core Use SSRB Pin (set/reset pin) Use Reset Behavior from RAMB16BWER Primitive Block Memory Generator Core Block RAM Primitives Block RAM Block RAM Latches Latches Embedded Output Registers N/A Embedded Output Registers N/A Embedded Output Registers N/A Primitive Output Registers D CE S* D CE S* Q Q Block RAM Latches Latches MUX DOUT SSR* CE SSR* CE Latches D CE S* Q CLK Use REGCE Pin EN REGCE SSR FALSE TRUE S* : The synchronous reset (S) of the flop is gated by CE Figure 38: Spartan-3A DSP Block Memory Generated with Register Port [A|B] Output of Memory Primitives. Virtex-5. Note: This behavior is the same as that of Spartan-3A. as illustrated in Figure 38. the Spartan-3A DSP embedded block RAM registers cannot be used. Use SSR[A|B] Pin Options (With SSR).com 57 . SSR – Without RAMB16BWER Reset Behavior If Use SSRA Pin (set/reset pin) or Use SSRB Pin (set/reset pin) is selected. 2008 Product Specification www. and Use Reset Behavior from RAMB16BWER Primitive is not selected.Block Memory Generator v2. without RAMB16BWER Reset Behavior DS512 September 19. Virtex-4. The primitive output registers are built from FPGA fabric. and Virtex-II devices.

and Use Reset Behavior from RAMB16BWER Primitive are selected. Port A or Port B Register Port A Output of Memory Primitives Register Port A Output of Memory Core Use SSRA Pin (set/reset pin) Use Reset Behavior from RAMB16BWER Primitive Figure Top x-ref 39 Register Port B Output of Memory Primitives Register Port B Output of Memory Core Use SSRB Pin (set/reset pin) Use Reset Behavior from RAMB16BWER Primitive Block Memory Generator Core Block RAM Primitives Block RAM Block RAM LaL tche atche s s Embedded Output Registers Embedded Output Registers Embedded Output Registers Block RAM Latches Latches MUX DOUT SSR* D CE SSR* S* CE Latches Q CE CLK Use REGCE Pin EN REGCE SSR FALSE TRUE S* : The synchronous reset (S) of the flop is gated by CE Figure 39: Spartan-3A DSP Block Memory Generated with Register Port [A|B] Output of Memory Primitives. the Spartan-3A DSP’s embedded output registers are used. 2008 Product Specification .com DS512 September 19. but the reset behavior of the core changes. If EN and REGCE are held high. the synchronous reset for both the latches and the embedded output registers are gated by the EN input to the core. the Spartan-3A DSP embedded registers are enabled for the selected port in the generated core. In addition. the output value is set to the reset value for two clock cycles following a reset. as displayed in Figure 39. This differs from all other configurations of the Block Memory Generator where SSR is typically gated by REGCE. Use SSR[A|B] Pin Options (With SSR). Use SSRA Pin (set/reset pin) or Use SSRB Pin (set/reset pin).8 Spartan-3A DSP FPGA: Memory with Primitive Output Registers.xilinx.Block Memory Generator v2. If Use Reset Behavior from RAMB16BWER Primitive is selected. and RAMB16BWER Reset Behavior Enabled 58 www. The functional differences between this and other implementations are that the SSR[A|B] input resets both the embedded output registers and the block RAM output latches. independent of the state of REGCE. SSR. and RAMB16BWER Reset Behavior When Register Port [A|B] Output of Memory Primitives. Figure 39 illustrates how the memory is constructed in this case.

the Spartan-3A DSP FPGA embedded registers are disabled in the generated core.Block Memory Generator v2. 2008 Product Specification www. Port A or Port B Register Port A Output of Memory Primitives Register Port A Output of Memory Core Use SSRA Pin (set/reset pin) Figure Top x-ref 40 Register Port B Output of Memory Primitives Register Port B Output of Memory Core Use SSRB Pin (set/reset pin) Block Memory Generator Core Block RAM Primitives Block RAM Block RAM Latches Latches Embedded Output Registers N/A Embedded Output Registers N/A Embedded Output Registers N/A Core Output Registers MUX D CE S* Q Block RAM Latches Latches DOUT SSR* CE Latches CLK SSR* Use REGCE Pin EN REGCE SSR CE FALSE TRUE S* : The synchronous reset (S) of the flop is gated by CE Figure 40: Spartan-3A DSP Block Memory Generated with Register Port [A|B] Output of Memory Core Enabled DS512 September 19.8 Spartan-3A DSP FPGA: Memory with Core Output Registers When Register Port [A|B] Output of Memory Core is selected.com 59 . as illustrated in Figure 40.xilinx.

output of the memory primitive is driven directly from the RAM primitive latches. Port A or Port B Register Port A Output of Memory Primitives Register Port A Output of Memory Core Figure Top x-ref 41 Register Port B Output of Memory Primitives Register Port B Output of Memory Core Block Memory Generator Core Block RAM Primitives Block RAM Block RAM Latches Latches Embedded Output Registers N/A Embedded Output Registers N/A Embedded Output Registers N/A SSR* CE Block RAM Latches Latches MUX DOUT Latches CLK EN SSR Figure 41: Spartan-3A DSP Block Memory Generated with No Output Port Registers Enabled 60 www. In this configuration.com SSR* CE DS512 September 19.8 Spartan-3A DSP FPGA: Memory with No Output Registers If no output registers are selected for port A or B.xilinx. but the clock-to-out delay for a read operation can impact design performance. as shown in Figure 41. 2008 Product Specification .Block Memory Generator v2. there are no additional clock cycles of latency.

registering the output of the core is enabled by selecting Register Port [A|B] Output of Memory Core. Register Output of Memory Primitives is selected. Port A or Port B Register Port A Output of Memory Primitives Register Port A Output of Memory Core Figure Top x-ref 42 Register Port B Output of Memory Primitives Register Port B Output of Memory Core Block Memory Generator Core Block RAM Primitives Block RAM Primitive Output Registers D CE Q Block RAM Latches Block RAM Latches D CE Q Core Output Registers MUX D CE S* Q DOUT Latches D CE Q CLK Use REGCE Pin EN REGCE SSR FALSE TRUE S* : The synchronous reset (S) of the flop is gated by CE Figure 42: Virtex-II Block Memory Generated with Register Port [A|B] Output of Memory Primitives and Register Port [A|B] Output of Memory Core Options Enabled DS512 September 19. are provided in the CORE Generator GUI on screen 4 in the Optional Output Registers section. two selections each. 2008 Product Specification www. for port A and port B.com 61 . Selecting this configuration may provide improved performance for building large memory constructs. In the same way.Block Memory Generator v2. Four implementations are available for each port. Virtex-II FPGA: Memory with Primitive and Core Output Registers With Register Port [A|B] Output of Memory Primitives and the corresponding Register Port [A|B] Output of Memory Core selected. Figures 42 through 45 illustrate the Virtex-II FPGA output register configurations. a memory core is generated with registers on the outputs of the individual RAM primitives and on the core output. as displayed in Figures 42. For implementing registers on the outputs of the individual block RAM primitives.8 Virtex-II FPGA: Output Register Configurations To tailor register options for Virtex-II FPGA architectures.xilinx.

com DS512 September 19.Block Memory Generator v2. Port A or Port B Register Port A Output of Memory Primitives Register Port A Output of Memory Core Figure Top x-ref 43 Register Port B Output of Memory Primitives Register Port B Output of Memory Core Block Memory Generator Core Block RAM Primitives Block RAM Primitive Output Registers D CE S* Q Block RAM Latches Block RAM Latches D CE S* Latches D CE S* Q Q MUX DOUT CLK Use REGCE Pin EN REGCE SSR FALSE TRUE S* : The synchronous reset (S) of the flop is gated by CE Figure 43: Virtex-II Block Memory Generated with Register Port [A|B] Output of Memory Primitives Enabled 62 www.8 Virtex-II FPGA: Memory with Primitive Output Registers When Register Port [A|B] Output of Memory Primitives is selected. as shown in Figure 43. 2008 Product Specification . Note that the output of any multiplexing required to combine multiple primitives are not registered in this configuration. a core that only registers the output of the RAM primitives is generated.xilinx.

Block Memory Generator v2. 2008 Product Specification www.com 63 .8 Virtex-II FPGA: Memory with Core Output Registers Figure 44 illustrates a memory configured with Register Port [A|B] Output of Memory Core selected.xilinx. Port A or Port B Register Port A Output of Memory Primitives Register Port A Output of Memory Core Figure Top x-ref 44 Register Port B Output of Memory Primitives Register Port B Output of Memory Core Block Memory Generator Core Block RAM Primitives Block RAM Block RAM Latches Block RAM Latches Core Output Registers MUX D CE S* Q DOUT Latches CLK Use REGCE Pin EN REGCE SSR FALSE TRUE S* : The synchronous reset (S) of the flop is gated by CE Figure 44: Virtex-II Block Memory Generated with Register Port [A|B] Output of Memory Core Enabled DS512 September 19.

2008 Product Specification . but the clock-to-out delay for a read operation can impact design performance. In this configuration. the output of the memory primitive is driven directly from the memory latches.com DS512 September 19.8 Virtex-II FPGA: Memory with No Output Registers When no output register options are selected for either port A or port B.xilinx. there are no additional clock cycles of latency.Block Memory Generator v2. See Figure 45. Port A or Port B Register Port A Output of Memory Primitives Register Port A Output of Memory Core Figure Top x-ref 45 Register Port B Output of Memory Primitives Register Port B Output of Memory Core Block Memory Generator Core Block RAM Primitives Block RAM Block RAM Latches Block RAM Latches MUX DOUT Latches CLK EN SSR Figure 45: Virtex-II Block Memory Generated with No Output Registers Enabled 64 www.

You are responsible for obtaining any rights you may require for any implementation based on the Information. posted.6. photocopying.3 release Updated for v2.2 release Updated for the v2. but not limited to.5. All specifications are subject to change without notice. express or implied. Resource Utilization and Performance The resource utilization and performance of the Block Memory Generator core is highly dependent on user selections. Information about additional Xilinx LogiCORE IP modules is available on the Xilinx IP Center.xilinx. and memory size. ISE version.8 Verification The Block Memory Generator core and the simulation models delivered with it are rigorously verified using advanced verification techniques. is free from any claims of infringement. Ordering Information The Block Memory Generator core is free of charge and is included with the Xilinx ISE CORE Generator system. Updates to the core are bundled with ISE IP Updates. Use of a Xilinx product in such application without the written consent of the appropriate Xilinx officer is prohibited. Updated core to version 2. devices.8. the "Information") to you "AS IS" with no warranty of any kind. Xilinx makes no representation that the Information.0 Initial Xilinx release Updated for Virtex-5 support Revision Updated primitives information in Table 1.0 5. Revision History Date 1/11/06 4/12/06 7/13/06 9/21/06 11/15/06 2/15/07 4/02/07 8/08/07 10/10/07 3/24/08 9/19/08 Version 1.2i. reproduced. Updated core to version 2. or any particular implementation thereof. replaced GUI screens.7. which are accessible from the Xilinx Download Center. none of the Information may be copied.1.4 release. electronic.0 2.5 6.0 4.5 7. please contact your local Xilinx sales representative. To order Xilinx software. downloaded. Xilinx tools v9. recording.Block Memory Generator v2. added support for ECC. or otherwise. republished. DS512 September 19. or transmitted in any form or by any means including. INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF INFRINGEMENT AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. mechanical. such as algorithm. XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE INFORMATION OR ANY IMPLEMENTATION BASED THEREON.0 3. including a constrained random configuration generator and a cycle-accurate bus functional model.com 65 . Minor updates for v2. Notice of Disclaimer Xilinx is providing this information (collectively. Except as stated herein. displayed. Added support for Spartan-3A DSP devices. ISE tools 10. 2008 Product Specification www.0 4. without the prior written consent of Xilinx. optional output registers.0 6. Updated core to v2.0 8. Updated core to v2.5 5. distributed. or systems. Related Information Xilinx products are not intended for use in life-support appliances. release date.