Regulation-2008

Academic Year -2013-2014

T.J INSTITUTE OF TECHNOLOGY KARAPAKKAM, CHENNAI-97
DEPARTMENT OF ECE

Question Bank
SUBJECT CODE SUBJECT NAME : EC235 : VLS !"S #$ SEM : !I YEAR : III

"#$$% T&'()*+
UNIT ! SPECIFICATION USING !ERILOG HDL Basic conce,ts- identi.iers- gate ,rimiti)es? gate dela0s? o,erators? timing controls? ,rocedural assignments conditional statements? !ata .lo+ and R7L? structural gate le)el s+itc' le)el modeling? !esign 'ierarc'ies? Be'a)ioral and R7L modeling? 7est (enc'es? Structural gate le)el descri,tion o. decoder? e6ualit0 detector? com,arator? ,riorit0encoder? 'al. adder? .ull adder? Ri,,le carr0 adder? ! latc' and ! .li, .lo,

#. E,-./01 2)0'3.* /2(45 2'&/60(4)/. 7(8'..019:

"#;+ "# 507'+ "Apr’10)

1% &'at is (e'a)ioural modelling* 2% &'at are t'e t+o statements used in ,rocedural constructs* 3% &'at is initial statement* 4% &rite one e-am,le .or initial statement* /% !e.ine al+a0s statement% 1% &'at is timing control* 2% &'at are t'e t'ree .orms in timing control* "N(6<##+ 8% !e.ine dela0 control% 3% !e.ine intra-assignment dela0 control% 10% !e.ine e)ent control% 11% &'at is le)el sensiti)e timing control* 12% &rite a(out !44 design e-am,le% 13% !esign !44 using (e'a)ioural modelling% 14% &rite a(out u,-counter% 1/% !esign u,-counter using (e'a)ioural modelling* 11% &rite a(out do+n-counter% 12% !esign do+n-counter using (e'a)ioural modelling% 18% &rite a(out simulation result o. u,-do+n counter 13% &rite a(out (lock statement% 5N(6<#$+ 20% #i)e notes on se6uential (lock% 21% &rite a(out ,arallel (lock% 22% &rite a(out out,ut node% 23% &rite a(out timing ,eriod%
78 79":"9;nit-V9<r%=R"<>;<AR? <rs%SAS >ALA9 !"S #$9QB9Version1%1 Year9V sem9":23/49VLS 1

% 13% #i)e notes on re.ore)er loo.or-loo.or-loo. statements% 2% !e.rocedural continuous assignments* 24% &rite a(out assign-de assign* 2/% &rite a(out .rocedural assignment* 2% &'at are t'e t+o kinds o. statement* 18% &rite an e-am.rocedural assignments* 4% &'at is non-(locking assignments* (Nov’09) /% &'at is conditional statement* 1% !e.ine i.% 12% &rite s0nta.o. .-. =(15014(4> />>0917'15.. s.arts o. /2(45 -)(='84)/. continuous assignments* &'at is im.+ "# 507'+ "A-)<$9+ 1% 2% 3% 4% /% 1% 2% 8% 3% !e. =(18050(1/. assign-de assign* 21% &rite a(out a(solute dela0% 22% &rite a(out .% 12% &rite a(out . case statement% 3% !e.019: "#.ine case statement% 8% &rite s0nta. statements* 11% !e.(? 7(8'.rocedural assignments* 3% &'at is (locking .0ing dela0s* !e.or@loo.uts% 2/% &rite a(out un(ounded state% Academic Year -2013-2014 2.our .eat@loo.eat@loo. loo.o. .o.o.ine .orce-release* 3. /18 -)(='84)/. >5/5'7'15 01 2'&/60(4)/./01 01 8'5/0.019: "#.% (Apr’09) 1/% &rite a(out +'ile@loo.Regulation-2008 24% &rite a(out (ista(le de)ice in.* 20% &rite an e-am.ine data.lo+ modelling* 5Apr’10) &'at is continuous assignment* &rite s0nta.licit continuous assignment* &'at is im. 7(8'. statement% 11% &rite s0nta. continuos assignments* &'at are t'e c'aracteristics o. .ine loo.+ 1% &'at is .le o.ine dela0* &'at are t'e t'ree +a0s o.<AR? <rs%SAS >ALA9 !"S #$9QB9Version1%1 .eci.ine regular assignment dela0* (Nov’10) Year9V sem9":23/49VLS 2 78 79":"9.nit-V9<r%=R"<>. +'ile@loo.our kinds o. statements% 14% &rite t'e s0nta. .le o. ./01 01 8'5/0. E.o.-. re. E. statement% 10% &'at are t'e .* 13% &'at are t'e . /2(45 8/5/ 3.licit net declaration* !e.rocedural continuous assignment* 23% List out t'e kinds o.ore)er loo..

e* 22% &rite a(out B:! adder circuit using data .ered (0 modern tester% 2/% &rite a(out concatenation o.ro(lem su.lo+ model* 23% &rite a(out t'e .ression* 13% &'at is o.uts in cmos* 8% !ra+ cmos s+itc'% 3% !esign o.. Write about structure methods.erator t0.e* 13% &rite a(out logical o.ine e-.o+er and ground* &'at is resisiti)e s+itc'es* &'at is .+ "# 507'+ "A-)<$9+ 1% !e.<AR? <rs%SAS >ALA9 !"S #$9QB9Version1%1 Year9V sem9":23/49VLS 3 .erator t0.erator t0.erator t0. cmos 2-in.ull u. E. test data% 24% List out t'e .ull do+n* "N(6<$9+ &'at is time dela0 +it' s+itc' .erator .ine net declaration dela0* 12% !e.licit continuous assignment dela0* 11% !e.ine s+itc' le)el modelling* 2% &'at is s+itc' modelling elements* 3% &'at are t'e t+o t0.erator t0.rimiti)es* &rite cmos in)erter e-am.-. What are the rules in scan design? 13% &'at is cmos nand gate* 20% !esign cmos in)erter circuit% 21% !ra+ t'e trut' ta(le o.e* 18% &rite a(out unar0 o.erator t0.es* 11% &rite a(out o. 7(8'.nit-V9<r%=R"<>.e% .es o.e* 20% &rite a(out relational o. 13% 14% 1/% 11% 12% &'at is . /2(45 >?05=& .ormat o. cmos nand gate* 22% !esign o. Define scan chain. cmos s+itc'% 10% &'at is (idirectional s+itc'es* 11% &'at are t'e t'ree ke0+ords used in (idirectional s+ic'tes* 12. and .recedence* 12% &rite a(out arit'metic o.ut nand gate* 23% &rite a(out ram cell% 24% &rite a(out cmos ram (lock* 78 79":"9.019: "#.le* 18.e* 21% &rite a(out e6ualit0 o. (Apr’12) /% &'at is t'e e.erators* 1/% &'at are t'e o.Regulation-2008 Academic Year -2013-2014 10% &'at is im.erands* 14% &'at is o.ect o.erator t0./01 01 8'5/0... mos s+itc'es* 4. scan signal asserted* 1% &'at is cmos s+itc'* 2% &'at are t'e t+o control in.'6'.

ort connecting rules* 5N(6<#$+ 11% &'at is in.orms* 1% &'at is t'e (est +a0 to generate se6uence )alues* 2% !ra+ +a)e.le o.ort declaration* 1/% &'at is . test (enc'* 3% &rite t0.eci.o. a module* "A-)<##+ 11% &'at is a .orm generation* /% &'at are t'e t0. +a)e.erence (et+een module and instance* 10% &rite s0nta. /2(45 8'>091 &0')/)=&* /18 08'15030')>: ".ort* 21% !esign . modules* 1% &'at does addition instantiates* 2% &'at does su(traction instantiates* 8% &'at is identi. /2(45 5'>5 2'1=&: 1% !e./01 01 8'5/0.+ 1% &'at is design 'ierarc'0* 2% Ao+ ne+ 'ierarc'0 is de.-..iers* 78 79":"9.uts* 12% &'at is out.iers* 3% Ao+ to s.0 t'e identi.ort* 12% &'at is t'e c'aracteristics o. as0mmetric gates% .<AR? <rs%SAS >ALA9 !"S #$9QB9Version1%1 Year9V sem9":23/49VLS 4 .orm generation using initial statement* 8% &'at is a module* 3% &'at is t'e di.-.roac'es o.ur. module* 13% #i)e an e-am. (locks and module instantiation* /% &'at are t'e t+o (locks in to.orm* 4% &'at are t'e t+o main a. E.lement as0mmetric gates* 23% &rite a(out ske+ed in)erters% 24% &'en reset condition occurs% 2/% &rite t'e uses o.es o.. Write about serial and partial serial scan.ine test (enc'* 2% &'at are t'e t'ree .ull adder circuit% 22% Ao+ to im./01 01 8'5/0.. +a)e. E.Regulation-2008 25. module* 14% &'at is .ine* 3% &'at is root module* 4% !ra+ 'ierarc'0 o.iers* 10% &'at are t'e e-am. Academic Year -2013-2014 5.ose o.nit-V9<r%=R"<>. identi. 0 .ical test (enc' .le o.uts* 18% &'at is inouts* 13% &'at is +idt' matc'ing* 20% &'at is unconnected .

adding scan and (uilt in sel.Regulation-2008 Academic Year -2013-2014 00.ens i.. dela0* 11% &'at 'a./01 01 8'5/0. A7=#* 18% &'at is t'e e.eci.ault* 23% &rite a(out s-a-0 . /2(45 M/143/=54)019 5'>5 -)01=0-.+ "# 507'+ "Apr’09) 1% &'at is critical .ine .)alues% 22% &rite a(out t0.ens i.anc0* 1/% Ao+ to ac'ie)e +orld class 6ualit0* 11% &rite a(out A7=#% 12% &'at is use o.eci.ens i.ault model* 4% &'at is stuck model* (Nov’09) /% &'at is stuck at .ied* 13% &'at is minBt0./*>: "#$+ "# 507'+ "A-)<#$+ 11% &'at is gate dela0* 12% &'at are t'e t'ree t0.-. discre.ault% 78 79":"9.es o... one dela0 s. E. test* 13% &rite a(out dela0 .actor in )lsi* 2% !e. )alues% 23% &rite a(out dela0 used in gate instantiation% 5A-)<#$+ 24% &rite a(out (uilt in ./01 01 8'5/0.all dela0* 1/% &'at is turn-o. =seudo-n<CS gate* 7.ect o.-.ied* 12% &'at 'a. gate dela0s* 5N(6<#$+ 13% &'at is rise dela0* 14% &'at is .rimiti)e gates% 2/% &'at are t'e uses o.)alues% 20% %&rite a(out min )alues% 21% &rite a(out ma.ault occurs* 21% &rite a(out .ect o. E.ro(lem arise +it' :<CS* 3% !e.'>: "#.anc0 detected* 14% &'at is t'e e..Bma.ied* 18% &'at 'a.ine C(ser)a(ilit0% 10% !e.ault* 1% Ao+ stuck at ..ault co)erage* (N0v’08) 12% &rite a(out good mac'ine% 13% Ao+ discre. t+o dela0 s.eci.ine controlla(ilit0% 11% &'at is meant (0 .ault% 22% List out t'e t0.ine e-'austi)e testing% 3% !e. t'ree dela0 s.ault testing% 20% Ao+ dela0 .ault determines* 2% &'at are t'e ot'er models in . stuck at .ault models* 8% &'at is t'e .<AR? <rs%SAS >ALA9 !"S #$9QB9Version1%1 Year9V sem9":23/49VLS 5 . /2(45 9/5' 8'.nit-V9<r%=R"<>.es o..

4(it magnitude com.Ds current la+% /% List t'e conditions .aults% 2/% &rite a(out random class% 9.roduction test* 12% &rite a(out (urn-in .019: "#.arameter% 18% &rite t'e ste.or t'e occurrence o.ault% Academic Year -2013-2014 @. .ine non-in)asi)e mode% !e.-. /2(45 S*>5'7 .s in)ol)ed during (urn-in* 13% List out t'e uses o. 9/5' . .ical :A! tool set* 24% &rite a(out (ridging .eed% 23% List out t'e tools a)aila(le in t0.ose o.ault% 2/% &rite a(out s'ort circuit .+ 1% 2% 3% 4% /% 1% &'at is 8"7A#* &'at is 87A#* !e. =0)=405> 4>019 >5)4=54)/.arator* 10% &'at is t'e .ine .or c'aracteriEation test* 13% #i)e notes on 0ield% 14% &rite a(out . 5'>5 5'=&10A4'>: "#.roduction test% 1/% List out t'e need .Regulation-2008 24% &rite a(out s-a-1 .ur. .<AR? <rs%SAS >ALA9 !"S #$9QB9Version1%1 Year9V sem9":23/49VLS 6 .'6'. 7(8'.arasitic estimation* 8% &'at is com. c'aracteriEation* 11% &rite a(out c'aracteriEation test% 12% &'at is t'e need .unctional test* 20% &'at are t'e .rocess s.aults detected (0 !!Q test* 21% List out t'e .ro(lem o. single rung ladder model% 4% &rite a(out kirc'o. !!Q testing% 22% &rite a(out s0stematic class in ..ied (0 .'> (3 =(7201/50(1/./01 01 8'5/0.in . D'>=)02' >(7' '.all dela0% 1% &rite a(out a(solute dela0% 2% &'at are t'e limitations o. decoder circuit* 2% &'at is modelling o..or . e6ualit0 detector* 3% !ra+ t'e diagram o. E.ort declaration in design o.'6'.arator circuit* "N(6<#$+ 3% &rite i9o .roduction test* (Nov’10) 11% List out t'e .ine (oundar0 scan* &'at is s0stem le)el test tec'ni6ue* !e./7-.+ "# 507'+ "N(6<#$+ 1% &'at is structural gate le)el modelling o.arameters )eri.ermission mode% 2% &'at is (oundar0 scan met'odolog0* "N(6<#$+ 8% &'at is BR* 78 79":"9.nit-V9<r%=R"<>.

lications o. VA!L* /% &'at is design met'odolog0* 1% &'at is gate le)el modelling* 2% &'at are t'e t+o t0. domino logic% 23% &rite a(out non-monotonic% (Nov’10) 24% List out t'e a.<AR? <rs%SAS >ALA9 !"S #$9QB9Version1%1 Year9V sem9":23/49VLS 7 .iler directi)es* 20% &'at are t'e ad)antages o.rocess* 21% &rite a(out .at' dela0s% 23% !ra+ t'e diagram o.a(ilities o.arameter* 11% &'at is task in VA!L* 12% #i)e some e-am. com. register data t0. net data t0.e* 14% #i)e some e-am.e* 12% #i)e some e-am.s in)ol)ed in .iler directi)e* 13% #i)e some e-am. B S7 . memor0 sel.lo+ modelling* 3% &'at is (e'a)ioural modelling* "Apr’11) 10% &'at are t'e data t0.les .e* 1/% &'at is a .-. multi.es o.or circuit in stand-(0 mode% 2/% &rite a(out (oundar0 scan arc'itecture% #$.'ase% 22% List out t'e disad)antages o.lo+% 2% &rite t'e ste.rocess o.-test% 2/% &rite a(out ::L% 78 79":"9.nit-V9<r%=R"<>. c'i.le t'res'old )oltage :<CS logic% 24% &rite t'e condition .Regulation-2008 Academic Year -2013-2014 3% &'at is BS:* 10% &'at is BSR* 11% &rite a(out BS7* 12% &rite a(out !:C!"* 13% #i)e notes on R* 14% #i)e notes on 7A=* "A-)<#$+ 1/% &rite a(out 7:>* 11% &rite a(out 7! * 12% #i)e notes on 7!C* 18% &rite a(out 7!R* 13% &rite a(out 7<S* 20% #i)e notes on 7RS7* 21% &rite a(out normal o.le o.eration o. VA!L* 11% &'at is net data t0.(? /18 5&'0) 341=50(1>: "#.le o. design met'odolog0* 8% &'at is data. in (oundar0 scan% 22% &rite a(out critical . )lsi design .'0sical design* 3% &'at is VA!L* 4% &'at are maFor ca.or s0stem task in )erilog* 18% &'at is com..+ "# 507'+ "N(6<$@+ 1% &rite t'e .es o.e* 13% &'at is register data t0. E.>0 8'>091 3.le o.rec'arge ./01 /2(45 6.

Regulation-2008 Academic Year -2013-2014 78 79":"9.nit-V9<r%=R"<>.<AR? <rs%SAS >ALA9 !"S #$9QB9Version1%1 Year9V sem9":23/49VLS 8 .