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1070

IEEE

JOURNAL

OF SOLID-STATE

CIRCUITS,

VOL.

SC-14,

NO. 6, DECEMBER

1979

Shunichi Suzuki was born on August 25, 1940. He received the B.E. degree from Kyoto University, Kyoto, Japan, in 1963. He joined the Nippon Electric Company, Ltd., Kawasaki-shi, Japan, in 1963 and has been engaged in research and development of magnetic plated wire memory. From 1968 to the present he has been working on semiconductor memory, particularly silicon Schottky-gate FET, DMOS, He is and short-channel MOS technologies. currently a Research Manager at the Centrrd Research Laboratories, managing a group in semiconductor digitaJ and analog circuits and systems. Mr. Suzuki is a member of the Institute of Electronics and Communication Engineers of Japan.

Masaki Hirata was born in Hiroshima, Japan, on March 9, 1949. He received the B.S. and M.S. degrees in electronic engineering from the University of Electronics Communication, Tokyo, Japan, in 1970 and 1972, respectively. He joined the Nippon Electric Company, Ltd., Kawasaki, Japan, in 1972. He has been His current working in MOS circuit design. research interests are in sensor devices. Mr. Hirata is a member of the Institute Electronics and Communication Engineers Japan. of of

A High-Performance All-Enhancement Operational Amplifier


IAN A. YOUNG, MEMBER, IEEE

NMOS

Abstract fabricated employs achieved

An using a novel include

NMOS only

operational enhancement

amplifier mode

has been scheme.

designed

and that

with

a gain between to realize

1000 and 2000. an amplifier with

It therefore

became

MOSFETS

in a circuit

attractive

this gain in single-

feedforward

compensation

Specifications

high open loop gain (2200), low-power

(15 mW or less

depending on the load), fast settling time (0.1 percent setting time in 3 #s for a 4 V input step and a 10 pF load), and small area. While this amplifier uses only a small number of transistors, its performance is comparable to that of recent depletion load amplifiers. Fewer critical steps are needed to fabricate this amplifier, making it attractive for large arialog/digitaf LSI circuits.

channel NMOS. The single-channel NMOS technologies are the most cost-effective in terms of cost per unit digital or analog function on the chip because of their high yield, low fabrication cost, and the very dense digital and analog circuit packing density. Thus, provided the design difficulties can be overcome, it is more cost-effective to realize these functions are used to realize an

in single-channel NMOS technology. When only enhancement transistors I. INTRODUCTION

HE REALIZATION of an internally compensated MOS amplifier has made possible the complete integration of analog and digital subsystems on a LSI chip. For example, A-D and D-A converters, tone generators, CODECS, CCD, and switched-capacitor filters have each been fully integrated in a MOS technology, some in CMOS and others in NMOS. In CMOS the operational amplifier design was found to be quite straightforward due to the availability of complementary devices which produce high gain per stage. In NMOS the first internally compensated amplifier [1] used only enhancement transistors and achieved the moderate gain of 200 which was sufficient for its design application in a CODEC. However, CCD transversal filters [2] and the more recently developed switched-capacitor recursive filters [3] required an amplifier

amplifier, the gain obtained for each common source stage is to a first-order dependent on the ratio of the (W/L) in the common source transistor over the (lV/L) of the load transistor. The latter would have its gate connected to, the positive supply voltage. As with the inverter design in digital circuits it became clear that the depletion-type MOSFET, when used as a load device in an inverter gain stage [4], would provide more gain than an enhancement load having the same geometry [5]. Here the depletion load device with a constant its gate consource. nected to its source is ideally current

Working against this ideal situation, however, is the fact that the clepletion device is not grounded at the source. Therefore, the output resistance of this current source is degraded as the output voltage changes, varying the back gate bias and modifying the threshold voltage through the body effect. Within the category of single-channel MOS design alternatives the ability to realize the high-performance generalpurpose MOS amplifier with only enhancement MOSFETS is attractive for a number of reasons. MOS circuits that use only enhancement MOSFETS are easier to design and manufacture, especially with regard to insensitivity to variati~ns in device@ 1979 IEEE

Manuscript received May 1, 1979; revised September 5, 1979. This research was sportsored by the National Science Foundation under Grant ENG73-01484-A01. The author wa$ with the Department of Electrical Engineering and Computer Science, University of California, Berkeley, CA 94720. He is now with the Mostek Corporation, Carrollton, TX 75006.

001 8-9200/79/1

200-1070$00.75

YOUNG:

ALL-ENHANCEMENT

NMOSOP

AMP

1071

.+
BODY BIAS (a) SOURCE FOLLOWER

k
M15 M13 PUT OUT M14 M16 OUTPUT STAGE

is a source-coupled single-ended output

pair forming

a differential

input with one This drives The load, level shift.

(as in a paraphase amplifier).

a second gain stage through a source follower

second gain stage consists of a driver and enhancement

whose gate is biased by the voltage present on the second output of the differential input stage, rather than the VDD supply. This connection provides a feedforward path with small phase shift at high frequencies. The second gain stage has a feedback capacitor tion. to realize a dominant pole through Miller compensatransistor gain stage drives a shunttrack one This simple two

shunt feedback output stage. The bias points in the circuit are interdependent such that all devices in the circuit another through proper choice of device geometry. These gain stages remain in their high gain active region independent of VT and mobility variations.
CIRCUIT DESCRIPTION

II. AMPLIFIER A. Process Description The amplifier switched-capacitor


DIFFERENTIAL INPUT STAGE SOURCE FOLLOWER GAIN STAGE

was fabricated recursive

as part of a fully falter using

monolithic Al-gate

n-channel

(b) Fig. 1. (a) NMOS operational amplifier (with only enhancement transistors). Cc= 11 pF. (b) Block diagram description of the amplifier circuit in (a).

MOS technology. No p+ isolation diffusion was employed; however a low resistivity p-type substrate (1 -2 Q . cm/5X 1015 boron atoms/cm3) was used to raise the field threshold to more. than +20.0 V with a small substrate bias applied. The enhancement device threshold was 0.2 V for zero substrate bias. To simulate higher threshold voltages, more typical of industrial processing, a substrate bias of-5 V was used so that the effective threshold of the devices, whose source is connected to - V~~, was 1.5 V. The range of threshold voltages that can be present throughout will, of course, be different the circuit from and body effect were that if the circuit

threshold voltages. This will help increase the yield, together with the fact that there is one less mask required to process this circuit. In a standard digital enhancement/depletion NMOS process, on 10-15 Q . cm material, the depletion transistor threshold enhancement voltage ( VTD) is not as well defined as the In addition, the body threshold voltage ( VTE).

factor for the depletion device is not low enough to allow a depletion load inverter formidably higher gain than an enhancement load inverter could realize in the same area. The enhancement/depletion amplifier has to maintain dc operating points where all devices are in the saturation region for worse case VTD and VTE variations. Additional circuitry is often needed to improve the insensitivity of the design to these variations. While the basic superiority be correct when analyzing amplifier of the depletion an inverter from device might a small signal

realized with devices having VT = 1.5 V without a substrate bias. The use of a substrate bias is justified, however, by the fact that the circuit operation is based on threshold voltage tracking rather than exact threshold voltages. B. The Input Stage The input stage is drawn in Fig. 2 with the layout W/L device sizes shown in microns. This amplifier is operated only with its positive input grounded in the switched-capacitor mode range is not region if the quiesIn this case, however, 445 and lf6 recursive falters; therefore, necessary. wide common

During transient conditions,

point of view, it is not necessarily true that use of this device in an overall operational design results in a general-purpose amplifier of superior performance to one designed A high-performance enhancement MOSFETS. amplifier that uses solely enhanceresults

can be driven hard out of their saturation

cent voltage drops across IW4 and J47 are large.

using only internally compensated in this paper. load amplifier It is interesting

iW5 and lt!f6 would be operating too close to VDSAT, the drainto-source saturation voltage, Thus, to avoid large transient distortion arising from the input stage, the voltage drop across A44 and J147 was limited to 6 V when the amplifier was biased from V~~ = +10 V, V~~ = -10 V, VBB = -15 V supplies. The single-ended gain of this input stage is given by w

ment MOSFETS is described along with experimental

It compares favorably with a recent depletion desi~ [5] in all aspects including silicon area. to also note that some high-performance

memory circuits do not have a depletion transistor in their design. [9] Fig. l(a) shows the basic circuit diagram of the operational amplifier to be described in this paper. Some devices have been left out for clarity at this point. The complete circuit will be given later. A block diagram for this amplifier circuit, shown in Fig. 1(b), illustrates the signal paths. The input stage

AV, =

dvm
VINDIFF

.1
2

w
1+; dvD~

/n

15

w
(1)
1

X4

+ VBB + 2@~

1072

IEEE JOURNAL

OF SOLID-STATE

CIRCUITS,

VOL. SC-14, NO. 6, DECEMBER

1979

+VDD

!
L

+VDD ?
L

T
M7 12/152 ? J

ML

12/152

}1~5 +

D%* 5
M1O
254/12

M12 25L/12

- v:~
Fig. 3. Source follower driving the second gain stage. Cc= 11 pF.

v:~
Fig. 2. Differential input stage. is shown in microns The channel width (W) and length for each transistor (W/L). (L)
V,N(S)

where y = body factor;


OF= bulk silicon Fermi potential; to ground; to ground. the differential one-half to enable compensation input VBB = substrate bias relative

Fig. 4. Small-signal block diagram of the circuit in Fig. 3. Small-signal components at VD4 and VD7 are out of phase with each other.

-0
V3 +

+ z + vou~(s)

-Avz

VD ~ = drain voltage With to the tageous overall The device sizes shown, output

of Jf5 relative the gain from is 12. for Only phase

single-ended use of amplifier. common-mode

of the availthe advanof the by

able differential

gain has been exploited feedforward

Cl is total capacitance between input and output (mostly Cg,,), and C2 is the total capacitance between the source follower output and ground. At low frequencies, and since rO for the devices is large compared to l/gm9, (3a) becomes

gain of the input

stage is controlled

AV(0)=C19. The value of this gain is 0.89. given by The output

(3b) impedance is

the output

resistance of M8.
1

The common-mode

gain is given

by AVCm= (2) 2 r. 84 gm

ROUT

= -+
~m9

llrOQllrO,O.
-

(4)

where rfl. is the small signal output resistance of Jf8 and g~~ is the sm~! signal transconductance of kf4. By increasing the channel length of lf8 one can reduce the common mode gain. The common mode gain of the input stage is approximately 0.04 with the device sizes as shown in Fig. 2.
C.

This impedance when multiplied with the sum of the input capacitance to Ml O, the total junction capacitance connected to this node, and the Miller multiplied feedback capacitance Cc, forms the dominant D.
Second Gain Stage

pole in the amplifier.

Source

Follower

Level

Shift

The single-ended output

from

the input stage is applied to

the gate of M9, a source follower which dc level shifts the signal down in voltage to drive the gate of Ml 2, the second
gain stages bias the driver device. as M3, the follower. and Ml O, whose provides Fig. second gain 3 shows gate is controlled current for it by the circuit which by to this the same dc voltage source follower source the quiescent stage

The second gain stage is a simple inverter in which the load device has its gate biased by the voltage at VD7 (the second output of the differential input stage). The low-frequency gain for this stage is given by
gin,,

AV,

=.

(5) 7

drives.

gw,,

~+ 2dv~12

The voltage

gain of this source follower


gm, + scl

is described

+ v~~ + 2@p
load inverter load is not as [5], the in

A~(s)=- + ag
where
.gm,

(3a) S(C1+C2)

Note that
strongly

the gain in this enhancement dependent on ~ as the stage forms provides is less process dependent. of this path that the some

depletion

inverter node for

J++-+ rO9

and therefore The output feedforward this three feedforward amplifier

010

summing phase

compensation low-frequency the latter

stage amplifier. compensation. stage with two

Fig. 4 illustrates

the principle

of the arising

A ~, is the high-gain, poles and one zero,

YOUNG:

ALL-ENHANCEMENT

NMOS

OP AMP

1073

from

the source follower

(3a).

Av,

isthelow-gain stage with

(a simple one pole This Based parasitic


M13 12/51

source follower

in fact) high-frequency

and one zero that are close to each other. stage provides a low phase shift path athigh path maintains the frequency stability

This feeclforward frequencies.

of the amplifier.

upon CgS and cgd in the devices and the lumped capacitances from nodes 1 and 2 to ground

V2($3(1+3 y2(S) =

(6)

mk
b stage,
M15 16/18 t-----

(1+:)(1+:)

A~3(o)

1 +:
( )

T-(7) Also the output impedance, output capacitor Cc, in a [6].

A ~3(s) = ()

1+1
P3

Fig. 5. Output

1/gml,,

of the Ml 5/&ll 6 inverter, This allows a lower The gain of this output

A ~,(s) describes the signal path from V~4 to the output of the circuit in Fig. 3, while A v, (s) describes the signal path from right V~7 to the output. to introducing half-plane The compensation a dominant addition pole, also introduces to a=, = (gm,, /Cc)

is reduced by the loop-gain gn, c/g~,,. than when feedback is not employed.

impedance with less quiescent current in Ml 5 and Ml 6

stage, assuming negligible body effect, is given by

zero corresponding

This right half-plane zero occurs at a low frequency because of the low transconductance from the MOS device. This is highly while at the same time stops pole in the undesirable since it degrades the phase of the complete amplifier by 90 at high frequencies the 20 dB/decade rolloff magnitude response. The overall transfer function for the scheme in Fig. 4 is V,(S). (8a) this created by the dominant

+= %i+gsk.l
.

gin,,

W =A ~ToT(s)
With the substitution

=AV,(S)+A

of (6) and (7) and refactorization,

equation takes the form

r
z ()

L lb

L14X w ~3

()

()

(9)

~ToT(S)

{A v,()+

A v,()}

The device geometries were chosen such that: capacitance to this stage did not load the output

1) the input of the second

gain stage, 2) the amplifier had a fast transient response with 10 pF connected directly I o the output (t2 V step in under 3.5 I-N), and 3) maximum The feedforward path has introduced new zero IIocations, which can be used to compensate the whole amplifier. P1 is the dominant pole produced by the Miller compensation capacitance Cc. The finrd location of the zeros is determined mainly by PI and the original zeros Z2 and Z3, the latter being controlled by Cg~, and Cgs,,. The design must ensure that any zeros below the unity gain crossover frequency pole. are placed as close as possible to their matching This is neeessary to F. VT
Insensitive Biasing

output voltage swing was achieved.

The complete

amplifier,

shown in Fig. l(a),

derives its dc

biasing from the three transistor string Ml, 1142,and Jf3, each of which is always in saturation because their gate and drain are connected. The quiescent voltages in the circuit are designed to track and maintain all devices, up to IW14, in the saturation re@on independent of the value of VT. This is based on the fact that the VT and mobility of the devices in the circuit will track, even though the absolute value might vary across the wafer. The quiescent voltage tracking will now be explained. geometric ratio after lateral (W/L)n denotes then transistors diffusion has been taken into account. The input stage is symmetrical, such that for z,ero differential input, VGsq = VGsT, independent of VT. Geometries (W/L)lO, (W/L)8, and (W/L)3

avoid any doublet contributing a large slow settling component to the transient response [7]. E.
Output Stage

The output stage is shown in Fig. 5. The use of shunt-shunt negative feedback allows this circuit to realize a moderate amount of gain while being broad-band in nature [1], [4].

1074

IEEE

JOURNAL

OF SOLID-STATE

CIRCUITS,

VOL.

SC-14,

NO.

6, DECEMBER

1979

TABLE M4s~ llEVICE


DIMENSIONS DEVICE Ml

1
CIRCUIT L (pm) 396.2 396.2 203.2 12.7 152.4 12.7
IN

FOR THE AMPLIFIER W(pm) 12.7 12.7 12.7 254 12.7 254

FIG,

Ml
M2 M3 M4 k s

M5

Fig. 6. Enhancement

NMOS operational cc=7pF+14pF.

amplifier.

CB, = CB, = 3.8 pF;

M6
M7 M8

254
12.7 254 12.7 12.7 254

12.7
152.4 12.7 203.2 203.2 12.7

are all the same, so that 110 =18 =13 = 11. Therefore, a current of Ii/2 flows through M4 and M7. Since (W/L)q = (W/L)7 = ~(W/L)l,
therefore, VGSI = VGS4 = VGS,. ~ ~Ds,2. This means that Of ~Gs, + VGS, = ~GS, + ~Ds, O= ~Gs,, The choice

M9 M9 kilo
ml

(W/L), /( W/L)3 = ( W/L)9/(W/L)10 therefore, of VT. (W/L)l VDG,O = O with Now ,/(W/L)12 then

results in VGs2 = VG~, and,

12.7
12.7 254 12.7 190.5 12.7 254

203.2
203.2 12.7 50.8 12.7 38.1 12.7

V~~lo = VGs10 = VGs, independent Thus,

Ml
Mlz N13 M14 M15 M16

since V~s, ~ = VGs,, and if (W/L) z/( W/L)3 = VGs2 = VGSII and V~Gl, = O. of VT. As long as

V~s,2 = VGs,, = V~s10 = VGs, independent

VT> O, Ml O and Ml 2 will remain in the saturation region where their transconductance is high and II ~ = II ~. The geometries were chosen such that the quiescent current in M3, M8, M1O, andikl12is 20pA when V~~ = +IOV, V~~ = -IOV, and VBB = -15 V. This choice consumed minimum power while also providing good frequency response from the input stage and high slew rate when charging the compensation G. Complete Amplifier The excessive area associated with a very long load device in the second gain stage can be reduced somewhat by using a split-load inverter consisting of two devices, with their gate tied to their drain, connected in series. The two series devices can produce the same small-signal resistance as the one transistor load, while requiring less total length for the transistors. The complete circuit for the amplifier is shown in Fig. 6, with the device geometries given in Table I. Bypass capacitance has been introduced into the two source follower signal paths in order to lower the dominant zero frequency and move it closer to the second dominant pole. This enables the unity gain bandwidth to be increased from 1.5 MHz up to 3 MHz with two bypass capacitors of 3.8 pF and Cc = 14 pF. The phase margin was increased from 45 to 55. When CC = 7 pF the slew rate is higher; however, the time over which damped oscillation occurs is longer. Finally, common mode feedback was used in the input stage as shown in Fig. 6. Ml and Ml sense the common mode voltage at nodes V~4 and VD7 of the input stage, and control the current into the lf3, M8 current mirror. Thus, if the common mode output the current through voltage for the input M3 stage increases, then into the increases and is mirrored capacitor.

VOUT ( VOLTS ) A 7 6 5 L 3 2 1 0. -1 -2 -3 -L -5-6 -

Fig. 7. Simulated dc amplifier characteristics of the NMOS (VDD V,yS = 20V; VBB - V8S = -5 V.)

amplifier.

technique overall

increased

the common

mode

rejection

ratio

for the

amplifier.

H. Simulated Performance Computer simulation was done using the circuit analysis

current source M8< This increased current in M8 causes the common mode output voltage to remain unchanged from the original value. Thus, more control has been placed on the dc operating points of VD4 and VD7 in the input stage. This

program SPICE2. The device model parameters were determined from experimental characteristics of devices that were fabricated with the process described in Section I. For V~D = 10 V, Vss = -10 V, VBB = -15 V, the dc transfer characteristic of the amplifier is given in Fig. 7, and the frequency response in Fig. 8(a) and (b).

YOUNG:

ALL-ENHANCEMENT

NMOS

OP AMP

1075

,.2

~03

,.4

,@
(a)

,.6

107

FREQUENCY [ HERTZ)

PHASE

( DEG]

102

103

IOL

105
(b)

106

107 FREQUENCY [ HERTZ)

Fig. 8. (a) Magnitude response of the NMOS~plifier (b) Phase response of the NMOS amplifier from

from simulatioln. simulation.

III.

EXPERIMENTAL

RESULTS

The all-enhancement NMOS amplifier was fabricated with the Al-gate NMOS technology described in Section II-A. A die photograph amplifier of the amplifier dimensions is shown in Fig. 9. The circuit of 12 ~m. The die arei~ for the had minimum

excluding bonding pads was 0.32 mm2 or 500 mils2.

Table II contains the measured performance from a sample of eight amplifiers on two different wafers. The dc transfer characteristic for this operational amplifier can be seen in Fig. 10. The power supply voltages were VDD =+1 O V, V~~ = -10 V, VBB = -12.5 V. Fig. 11 provides information about the common mode input range and the common mode rejection ratio. This photograph is a trace of the input offset voltage as a function of common mode input voltage. Fig. 12
Fig. 9. Microphotograph of the amplifier.

DD

1076

IEEE

JOURNAL

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VOL.

SC-14,

NO. 6, DECEMBER

1979

TABLE H PERFORMANCE PARAMETERS OF THE NMOS AMPLIFIER BASED UPON A SAMPLE OF EIGHT AMPLIFIERS ON Two DIFFERENT WAFERS Power Supplies:
Substrate bias VDD = + 10.0 = 2.5 V, VSS = 12.5 V) 10.0 V

COMMON MOOE UT .:; 1

(VBB = -

+4 +2

Low Frequency Low Frequency Input Input Offset Offset

Gain Gain Voltage Voltage Input

Mean Standard Mean Standard Range Ratio voltage) Rejection Rejection (at zero Deviation Deviation

2200 200 20 mv 5 ml + 5. Ovto-8.5V

o -2 -L -6

Common Mode

Common Mode Rejection common mode input Positive Negative Slew Step Rate Response fOra fOra Settling Power Power Supply Supply

72 dB

SO dB 74 dB + 5 vf~sec,

-20

L-L&&.& -lo INPUT OFFSET (mV) amplifier.

Fig. 11. Common - 2 Vlvsec OUTPUT

mode input

performance

of the NMOS

Time Vstep: Vstep:

to

O.1%: 2.0 2.0 3.5 3.0 +3.2 60 to

OVto+l OVtO-l

vsec usec usec lJsec


vto-7.4v

1 V/div

+2 +1 o -1 -2

f0ra-2Vt0+2V f0ra+2Vto-2V Output Total Voltage SwinS

step: step:

Input Referred Noise (O to 50 kHz bandwidth) Conswnpt ion

SO UV IlUS

Power

15 mW

OUTPUT 1 Vid!v OUTPUT (VOLTS) +2 +6


+L

(a)

+1 o -1 -2

+2 o -2 -L -6

~
2 pec/dlv (b) Fig. 12. Measured transient response of the NMOS operational fier in the unity g~in connection with a 10 pF load. I
I I I I I -20 -lo 0 10 20 DIFFERENTIAL INPUT [ mV]

ampli-

-8~

only

enhancement was lower The unity are similar operational all-enhancement performance

mode

transistors.

The gain achieved area was

(2200) any

Fig. 10. Measured dc transfer characteristic of the NMOS operational amplifier. Input offset was 18 mV, but is set to zero in the above curve: VDD VSS = 20 V; VBB - VSS = -2.5 V.

was higher, voltages) previous design. * 2 V input istics load the

the power

consumption MOSFET

(15 mW for *1 O V supply

and the silicon gain settling

srnallei- than

all-enhancement

operational load. [5].

amplifier

to 0.1 percent the

was 3 MS for a These characterdepletion of the on the cost, on the is that than

shows some step responses of the operational amplifier when connected as a unity gain buffer with around 10 pF directly on the output. The measured power consumption was 15 mW, By reducing the load drive capability could be reduced to less than 5 mW. IV. of the design, this power

step and a 10 pF capacitive to those for amplifier of described the (e.g., circuit body in

general-purpose techniques and

The advantage less dependent VTD) to a lower amplifiers

amplifier

design

overall depletion higher systems one die.

is far factor This

processing

parameters load that amplifier

CONCLUSIONS

design. multiple

leads

The results of this work have shown that an internally compensated operational amplifier with good overall characteristics can be realized with single-channel MOS technology and

yielding

alternative require

for large-scale operational

integration

of analog

IEEE

JOURNAL

OF SOLID-STATE

CIRCUITS,

VOL.

SC.14,

NO. 6, DECEMBER

1979

1077

ACKNOWLEDGMENT The Gray, author and Prof. wishes to thank for Dr. B. J. Hosticka, helpful Prof. P. R. ,6]

Y. P. Tsividis

their

comments. [7] NMOS operational J, Soli&State Cir-

REFERENCES [1] Y. P. Tsividis and P. R. Gray, An integrated amplifier with internal compensation, IEEE cuits, vol. SC-11, pp. 748-753, Dec. 1976.

[8] [9]

[2]

[3] [4]

[5J

C. H. Sequin and M. F. Tompsett, Charge transfer devices, in Advances in Electronics and Electron Physics. New York: Academic. 1975. R. W. Brodersen, P. R. Gray, and D. A. Hodges, Proc. IEEE, vol. 65, Jan. 1979. MOS sampled-data recursive fiiters using state B. J. Hosticka, variable technique s, Ph.D. dissertation, Univ. of California, Berkeley, 1977. D. Senderowicz, D. A. Hodges, and P. R. Gray, High performance

IEEE J. Solid-State Ctrcuits, vol. SC-13, pp. 760-766, Dec. 1978. Y. P. Tsividis, Design considerations in single-channel MOS analog integrated circuits A tutorial, IEEE J, Solid-State Circuits, vol. SC-13, pp. 383-391, June 1978. R. J. Apfel and P. R. Gray, A fast-settling monolithic operational amplifier using doublet compression techniques, IEEE J. SolidState Circtiits, vol. SC-9, Dec. 1974. C. N. Ahlquist et al., A 16,384 bit dynamic RAM, IEEE J. SolidState Circuits, vol. SC-1 1, ]pp. 570-574, Oct. 1976. P. R. Schroeder and Robert J. Proebsting, A 16K X 1 bit dynamic RAM, Digest Int. Solid-State Circuits Conf. (Philadelphia, PA, Feb. 1, 1977), pp. 12-13.

NMOS operational amplifier,

Ian A. Yourrz C373-M78), issue, p. 10331

for

a photograph

and biography,

see this

End

of Special

Section

Nonlinear

Signal Processing with Domain Devices


ALBERT C. VAN DER WOERD

Carrier

Abstract cuits ployed occurring

new

design The

method principle

for

nonlinear

signal

processing domain The by

ciremthe two

is presented. in a planar geometries of which the domain

is based structure [3].

on carrier of special

moving, Smith

such as p-n junctions. In practice this has sometimes led to quite complicated circuits with relatively low bandwidth. In this paper a method fo~r performing nonlinear signal processing based on the carrier domain principle will be presented. The concept was first introduced by Gilbert [1] and is also mentioned in [3] , When this approach is used the actual nonlinear operation is executed by only one network element: a carrier domain device (CDD). Because the high bandwidth and the noise properties of such devices are promising [2] , a comparison with common circuits is useful. In this paper, however, only the development of some new CDD geometries is described. We start by giving a brief description of the idea of the carrier domain principle adapted to our special aim. Generally speaking, a carrier domain device is an element comprising an extended bipolar transistor structure where the carrier injection is compressed into a small area (domain) by enforced emitter crowding; in addition, this domain, and hence the signal transfer, can be changed by an external variable. Gilbert applied this principle to his new four-quadrant multiplier [2] , 01979 IEEE

transistor multiplier domain

design,,

are variants

of the geometry corresponding method in practical

employed to

for his carrier calculation arbitrary examples,

The design method has been devices.

involves to

locus The

a predetermined applied

transfer

function.

have been realized

I.

INTRODUCTION

ONLINEAR

analog signal processing circuits are widely

used in electronic systems. Some examples are signal compressing and expanding circuits in audio systems, gamma correctors in video systems, and triangle-sine converters in function generators. Prevailing circuits commonly employ a combination of several basic nonlinear network elements
Manuscript received May 25, 1978; revised July 17, 1979. The author is with the Department of Electrical Engineering, University of Technology, Delft, The Netherlands.

Delft

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