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Pipelined MIPS CPU Synthesis and On-Die Representation

ECE472
Joseph Crop Stewart Myers

2008

.... 11 APPENDIX B – Pipelined MIPS CPU On-Die Representation....................................... 15 APPENDIX E – Pipelined MIPS CPU Verilog Code ............................................................................................................................................. 13 APPENDIX D – Synthesis Configuration Code................................................................................................................................................................ 8 Simulated Delay.............................. 9 APPENDIX A – Synthesized Pipelined MIPS CPU ....................................... 3 Pitfalls ...........................................................................................Table of Contents Introduction.................... 3 Steps Taken and Simulation.......... 16 2 ...................................................................................................... 12 APPENDIX C – Encounter Configuration File .....................................................................................................

We will explain all the steps taken to reach the final representation.v 4. Place all of your . If you haven’t already. Modify the dc_syn file inside of the synthesis folder to include all of your . 2. create a test bench for your verilog code.v files in the verilog_input folder.Introduction This project involved the creation of an on-die representation of a pipelined MIPS CPU from code acquisition to synthesis to final die layout./verilog_input/file1. Also. the pitfalls we encountered and how we overcame them. many of the tools required to complete the synthesis and on-die representation were completely new to us. Although we have had experience with ModelSIM and writing Verilog from other projects during this term. and we will explain how we simulated the delay and what those delay values were..v files read_verilog .. make sure your test bench module has a clock input current_design mips_pipeline_testbench 3 . 3. Steps Taken and Simulation 1.v read_verilog ./verilog_input/file2. Change both of the current_ design parameter to contain the name of your test bench module. how we simulated our pipelined CPU.

design_vision-xg -f dc_syn 8.v write_sdc . 4 .gate. If not already selected. create_clock clk -name cpu_clock -period 5 6.. If you don’t have your current design listed as your test bench thing will go wring and you may or may not get errors.sdc 7. and execute the following command. Open a terminal. Change the names of the output files to something useful. make sure your test bench is loaded in the drop-down box at the top of the screen. After ogling your cool design close Design Vision. If you didn’t set the current_design parameter correctly your test bench will load as a very small design instead of your whole cpu. 9..5. Ours was named “clk”. navigate to the synthesis folder. This starts the Design Vision program and creates gate-level synthesized verilog. write -format verilog -hierarchy -output ./synthesized_verilog/pipeline_testbench. After the Design Vision program loads choose Schematic -> New Design Schematic View./synthesized_verilog/pipeline_testbench. Create a clock in the design: change the create_clock command to have the get_ports parameter to point you your clock register.

they are placed in the synthesis/reports folder.gate.00 # 0.01 5 . Three reports are generated from the synthesis. It should be located in: synthesized_verilog/[name].00 0.90 -------------------------------------------------------------------------.00 dut/WB_MemtoReg_reg/CK (DFFTRX1MTH) 0.5} {clk} -------------------------------------------------------------------------------If the clock report looks correct.10. Verify the clock was asserted correctly to you design by opening the clock report.00 {0 2.91 . -------------------------------------------------------------------------. . open the delay report.00 clock network delay (ideal) 0.--------------slack (MET) 0.--------------clock clk (rise edge) 0.v 11. The delay report will tell you if your selected clock period will work for the gate simulated gate delays from Design Vision.--------------data required time 4. . If it’s wrong your test bench or synthesis configuration file are incorrect. you should see something like this: Clock Period Waveform Attrs Sources -------------------------------------------------------------------------------clk 5.00 0. Make sure your gave-level verilog was synthesized correctly by running is in modelsim and verifying identical operation to your original code. clock report and a delay report.91 data arrival time -4. an area report.00 r data required time 4. It should look something like this: Point Incr Path -------------------------------------------------------------------------.

lef are pointed to correctly set rda_Input(ui_timelib) ".12./cell_lib_files/lef/cms9flp_8lm_2thick_tech. Make sure your ./cell_lib_files/scmetro_cms9flplvt_tt_1p2v_25c. 6 .. Change the directory in your shell to the encounter folder. Make sure your test bench is your top cell! set rda_Input(ui_topcell) "mips_pipeline_testbench" 3.sdc" 14... 13./synthesized_verilog/[name].conf in the encounter folder..conf” file and click OK.lef" 2. Make sure your timing and netlist files are pointed to correctly set rda_Input(ui_netlist) ". You should see a black square with gray horizontal lines on the screen../cell_lib_files/lef/cms9flplvt_m_macros.gate. Edit encounter./synthesized_verilog/[name]. 1.v" set rda_Input(ui_timingcon_file) ". Navigate to Design -> Design Import -> Load and select your “encounter.lib" set rda_Input(ui_leffile) ".lef .lib and . Run Cadence encounter! We found it in “/usr/local/apps/cadence/SOC/current/bin/encounter” 15.

7 . this will place all of the standard blocks. 21. Click “OK”. 17. 18. click “update” to see what values it is actually going to use. fitting the largest block it can into each hole. This will add filler blocks. Add filler blocks to connect the power rails between the standard cells with Place -> Physical Cells -> Add Filler and click on “select”. Now run Timing -> Optimize with “Post-Route” selected. Type "VSS VDD" into the "Net(s):" area. Add power rings by navigating to Power -> Power Planning -> Add Rings. Sometimes unnecessarily ugly routes will be taken. manually fix these to ensure a clean signal path if you would like. Add horizontal power buses by navigating to Route -> Special Route and clicking “OK” (the default values are usually acceptable). and select "center in channel". To make the cells show up by clicking on the "Physical View" button in the top right corner of the screen. Now go to Edit -> Pin Editor and click on your clock(s) in the list of pins and change "USE:" to "CLOCK". 20.16. This step can take a while so be patient. To route the blocks run Route -> Nanoroute -> Route with the default options. Then click “Close” and then click “OK”. specify metal layers and ring width (We used Top/Bottom Metal5 and Left/Right Metal6). Highlight all fillers and click "add". 19. 22. Navigate to Place -> Standard Cells and click “OK”.

g. the rom32. We visited opencores. Also run Verify -> Verify Connectivity to look for unconnected pins. Then save the SOC Encounter design with Design -> Save Design As -> SoCE and click “OK”. Failing to change that variable caused Design Vision to list all elements of our pipelined MIPS CPU. we decided to use our existing pipelined MIPS code from the final project.. That’s it! you’re done! Pitfalls The first pitfall we encountered was simply trying to obtain Verilog source code that we could synthesize and model on-die. Apparently the program needed to know hierarchy of all elements of the 8 .23. Export your design by running Design -> Save -> GDS/OASIS and specify a name such as “counter. Thus we were able to move on to the synthesis phase. 24. or contained notes to the effect there were still bugs to work out. Finally.gds” (the default options are sufficient). After a couple of hours of searching. if there is a violation use Tools -> Violation Browser to see a list of the violations. Verify the layout by running Verify -> Verify Geometry. we discovered that the current_design parameter in the Design View configuration file had to be changed to the name of our pipelined MIPS module. Not only were there very few projects written in Verilog. the forwarding unit. Synthesis is where we ran into the second pitfall. When synthesizing our Verilog code. exit SOC Encounter. etc. 25. separately and would not combine them into an integrated chip. e.org and viewed all the projects written in Verilog. but those that initially appeared suitable turned out to have been deleted.

easily remedied issues such as forgetting to check or uncheck a dialog box entry. along with running our MIPS pipeline module. We ran Design Vision many. Design Vision said we had no clock and we couldn’t time our CPU. Operating Conditions: tt_1p2v_25c Wire Load Model Mode: top Library: scmetro_cms9flp-lvt_tt_1p2v_25c Startpoint: dut/WB_MemtoReg_reg (rising edge-triggered flip-flop clocked by clk) Endpoint: dut/MEM_Zero_reg (rising edge-triggered flip-flop clocked by clk) Path Group: clk 9 . overview file. We had to have an output Y and input A. Simulated Delay Following is the report created by Design Vision on simulated delay: **************************************** Report : timing -path full -delay max -max_paths 1 Design : mips_pipeline_testbench Version: X-2005.CPU and the current_design parameter serves as the entry point. When using the testbench.09-SP2 Date : Fri Dec 12 14:29:03 2008 **************************************** # A fanout number of 1000 was used for high fanout net computations. then set them equal to each other on the posedge of the clock. and with no reset signal. of that hierarchy. many times before discovering this error. we ran into a third major pitfall when trying to time the synthesized CPU in Design Vision. these changes added a clock to our synthesis and we could time the pipelined CPU. We began synthesis by using the pipelined testbench which contained a clock. etc. All these issues were quickly taking care of by rereading the online tutorial. For whatever reason. After synthesizing we were able to move on to the on-die representation phase where we encountered only minor. but did not have a clock as input. After synthesizing our CPU.

16 0.71 f dut/EX_ALU/add_145/U1_24/CO (ADDFX2MTH) 0.13 3.57 f U282/Y (AOI22X1MTH) 0.13 2.00 clock network delay (ideal) 0.12 4.09 f dut/EX_ALU/add_145/U1_27/CO (ADDFX2MTH) 0.31 f dut/EX_ALU/add_145/U1_5/CO (ADDFX2MTH) 0.01 10 .56 f dut/EX_ALU/add_145/U1_7/CO (ADDFX2MTH) 0.33 f U970/Y (AO22X2MTH) 0.67 f U268/Y (AO22X2MTH) 0.44 f dut/EX_ALU/add_145/U1_30/CO (ADDFX2MTH) 0.84 f dut/EX_ALU/add_145/U1_25/CO (ADDFX2MTH) 0.13 4.58 f dut/EX_ALU/add_145/U1_23/CO (ADDFX2MTH) 0.13 2.04 4.07 4.13 3.13 3.13 2.00 dut/MEM_Zero_reg/CK (DFFTRX1MTH) 0.09 4.00 0.13 1.33 f dut/EX_ALU/add_145/U1_21/CO (ADDFX2MTH) 0.32 f dut/EX_ALU/add_145/U1_29/CO (ADDFX2MTH) 0.04 4.05 f dut/EX_ALU/add_145/U1_3/CO (ADDFX2MTH) 0.13 2.04 4.17 f U335/Y (BUFX2MTH) 0.00 r library setup time -0.20 f dut/EX_ALU/add_145/U1_20/CO (ADDFX2MTH) 0.13 3.86 f U289/Y (NOR2X1MTH) 0.96 f dut/EX_ALU/add_145/U1_26/CO (ADDFX2MTH) 0.13 1.00 # 0.90 -------------------------------------------------------------------------slack (MET) 0.18 f dut/EX_ALU/add_145/U1_4/CO (ADDFX2MTH) 0.13 3.13 2.13 1.08 f dut/EX_ALU/add_145/U1_19/CO (ADDFX2MTH) 0.13 3.23 1.13 1.00 r dut/WB_MemtoReg_reg/Q (DFFTRX1MTH) 0.70 f dut/EX_ALU/add_145/U1_16/CO (ADDFX2MTH) 0.12 4.17 0.90 clock clk (rise edge) 5.69 r U252/Y (OAI2B11X2MTH) 0.27 r U267/Y (NAND3X2MTH) 0.00 0.13 3.00 clock network delay (ideal) 0.90 r dut/MEM_Zero_reg/D (DFFTRX1MTH) 0.19 f dut/EX_ALU/add_145/U1_12/CO (ADDFX2MTH) 0.09 4.90 r data arrival time 4.49 f U258/Y (BUFX4MTH) 0.23 f U272/Y (NAND2X1MTH) 0.44 f dut/EX_ALU/add_145/U1_14/CO (ADDFX2MTH) 0.Path Type: max Point Incr Path -------------------------------------------------------------------------clock clk (rise edge) 0.57 f dut/EX_ALU/add_145/U1_15/CO (ADDFX2MTH) 0.07 0.13 2.00 5.46 f dut/EX_ALU/add_145/U1_22/CO (ADDFX2MTH) 0.81 f dut/EX_ALU/add_145/U1_9/CO (ADDFX2MTH) 0.00 5.82 f dut/EX_ALU/add_145/U1_2/CO (ADDFX2MTH) 0.08 0.76 f U269/Y (NOR2XLMTH) 0.64 r U278/Y (OAI2BB1X2MTH) 0.13 1.91 data required time 4.06 f dut/EX_ALU/add_145/U1_11/CO (ADDFX2MTH) 0.95 f dut/EX_ALU/add_145/U1_18/CO (ADDFX2MTH) 0.17 0.00 5.68 f dut/EX_ALU/add_145/U1_8/CO (ADDFX2MTH) 0.05 4.13 3.43 f dut/EX_ALU/add_145/U1_6/CO (ADDFX2MTH) 0.14 4.13 1.04 0.04 4.82 f dut/EX_ALU/add_145/U1_17/CO (ADDFX2MTH) 0.91 -------------------------------------------------------------------------data required time 4.94 f dut/EX_ALU/add_145/U1_10/CO (ADDFX2MTH) 0.66 f U251/Y (NAND2X1MTH) 0.57 f dut/EX_ALU/add_145/U1_31/Y (XOR3X1MTH) 0.13 2.82 r U259/Y (NAND2XLMTH) 0.32 f dut/EX_ALU/add_145/U1_13/CO (ADDFX2MTH) 0.00 4.15 0.06 4.00 dut/WB_MemtoReg_reg/CK (DFFTRX1MTH) 0.13 1.91 data arrival time -4.13 2.

APPENDIX A – Synthesized Gate Level Pipelined MIPS CPU 11 .

APPENDIX B – Pipelined MIPS CPU On-Die Representation 12 .

0ps} set rda_Input(ui_net_load) {0.v" set rda_Input(ui_timingcon_file) "../cell_lib_files/scmetro_cms9flp-lvt_tt_1p2v_25c.sdc" set rda_Input(ui_topcell) "mips_pipeline_testbench" set rda_Input(ui_netlisttype) {Verilog} set rda_Input(ui_ilmlist) {} set rda_Input(ui_settop) {1} set rda_Input(ui_celllib) {} set rda_Input(ui_iolib) {} set rda_Input(ui_areaiolib) {} set rda_Input(ui_blklib) {} set rda_Input(ui_kboxlib) "" set rda_Input(ui_timelib) ".lef" set rda_Input(ui_core_cntl) {aspect} set rda_Input(ui_aspect_ratio) {1.0} set rda_Input(ui_time_unit) {none} set rda_Input(ui_cap_unit) {} set rda_Input(ui_sigstormlib) {} set rda_Input(ui_cdb_file) {} set rda_Input(ui_echo_file) {} set rda_Input(ui_qxtech_file) {} set rda_Input(ui_qxlib_file) {} set rda_Input(ui_qxconf_file) {} set rda_Input(ui_pwrnet) {VDD} set rda_Input(ui_gndnet) {VSS} set rda_Input(flip_first) {1} 13 .0} set rda_Input(ui_xcap_scale) {1./cell_lib_files/lef/cms9flplvt_m_macros.APPENDIX C – Encounter Configuration File ################################################ # # # SOC Encounter Input configuration file # # # ################################################ global rda_Input set rda_Input(ui_netlist) "...0} set rda_Input(ui_shr_scale) {1.7} set rda_Input(ui_core_height) {} set rda_Input(ui_core_width) {} set rda_Input(ui_core_to_left) {30} set rda_Input(ui_core_to_right) {30} set rda_Input(ui_core_to_top) {30} set rda_Input(ui_core_to_bottom) {30} set rda_Input(ui_max_io_height) {0} set rda_Input(ui_row_height) {} set rda_Input(ui_isHorTrackHalfPitch) {0} set rda_Input(ui_isVerTrackHalfPitch) {1} set rda_Input(ui_ioOri) {R180} set rda_Input(ui_isOrigCenter) {0} set rda_Input(ui_exc_net) {} set rda_Input(ui_delay_limit) {1000} set rda_Input(ui_net_delay) {1000.0ps} set rda_Input(ui_captbl_file) {} set rda_Input(ui_cap_scale) {1.lef ./synthesized_verilog/pipeline_testbench..5pf} set rda_Input(ui_in_tran_delay) {120.lib" set rda_Input(ui_smodDef) {} set rda_Input(ui_smodData) {} set rda_Input(ui_dpath) {} set rda_Input(ui_tech_file) {} set rda_Input(ui_buf_footprint) {BUFX2MTH} set rda_Input(ui_delay_footprint) {BUFX2MTH} set rda_Input(ui_inv_footprint) {INVX1MTH} set rda_Input(ui_leffile) ".0} set rda_Input(ui_core_util) {0.0} set rda_Input(ui_res_scale) {1..gate./synthesized_verilog/pipeline_testbench./cell_lib_files/lef/cms9flp_8lm_2thick_tech.

set rda_Input(double_back) {1} set rda_Input(assign_buffer) {0} set rda_Input(ui_pg_connections) [list \ {PIN:VDD:} \ {PIN:VSS:} \ ] set rda_Input(PIN:VDD:) {VDD} set rda_Input(PIN:VSS:) {VSS} 14 .

{"\\]"..sdc ./verilog_input/out. "_"}} } read_verilog ./synthesized_verilog/pipeline_testbench./reports/area./reports/clock../reports/delay.v write_sdc .gate.v current_design mips_pipeline_testbench link ##### constraints are below ##### #erase all attributes and constrains from the current design reset_design #set wire loading mode to top #set_wire_load_mode top # Create clock with 5ns period create_clock clk -name clk -period 5 change_names -rules "MYrules" -hierarchy # Compile with completely disolved design compile -ungroup_all # Make sure we are at the top level set current_design mips_pipeline_testbench # Generate area and constraints reports on the optimized design report_area > ..rpt report_clock > .rpt # Save the compiled design write -format verilog -hierarchy -output . "_"}.APPENDIX D – Synthesis Configuration Code #synopsys synthesis script set hdlin_auto_save_templates true set hdlin_check_no_latch true set hdlin_warn_sens_list true define_name_rules MYrules -map { {{"\\[".rpt # Generate timing report for worst case path report_timing > ./synthesized_verilog/pipeline_testbench.