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Two-dimensional CdS nanosheet-based TFT and LED nanodevices

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IOP PUBLISHING Nanotechnology 23 (2012) 194004 (5pp)



Two-dimensional CdS nanosheet-based TFT and LED nanodevices
Yu Ye, Bin Yu, Zhiwei Gao, Hu Meng, Hui Zhang, Lun Dai and Guogang Qin1
State Key Lab for Mesoscopic Physics and School of Physics, Peking University, Beijing 100871, People’s Republic of China E-mail: and

Received 26 November 2011, in final form 27 December 2011 Published 27 April 2012 Online at Abstract Semiconductor nanosheets have several unique applications in electronic and optoelectronic nanodevices. We have successfully synthesized single-crystalline n-type CdS nanosheets via a chemical vapor deposition (CVD) method in a Cd-enriched ambient. The as-synthesized nanosheets are typically 40–100 nm thick, 10–300 µm wide, and up to several millimeters long. Using the nanosheets, we fabricated for the first time (to our knowledge), nano thin-film transistors (nano-TFTs) based on individual CdS nanosheets. A typical unit of such nanosheet TFTs has a high on–off ratio (∼1.7 ×109 ) and peak transconductance (∼14.1 µS), which to our knowledge are the best values reported so far for semiconductor nano-TFTs. In addition, we fabricated n-CdS nanosheet/p+ -Si heterojunction light emitting diodes (LEDs) with a top electrode structure. This structure, where the n-type electrode is directly above the junction, has the advantage of a large active region and injection current favorable for high-efficiency electroluminescence (EL) and lasing. Room-temperature spectra of the LEDs consist of only an intense CdS band-edge emission peak (∼507.7 nm) with a full width at half-maximum of about 14 nm. (Some figures may appear in colour only in the online journal)

1. Introduction
Two-dimensional (2D) semiconductor nanosheets, which are characterized by a thickness of the order of nanometers and a lateral scale much bigger than that of nanobelts (NBs), are important for a variety of applications [1–3]. Similar to nanowires (NWs)/NBs, single-crystalline nanosheets can also be grown on lattice mismatched substrates and constructed into devices using the bottom-up method on almost any substrate [4]. Additionally, semiconductor nanosheet-based devices, as a new type of nano thin-film device, have some important advantages over NW/NB-based devices. For example, semiconductor nanosheet-based transistors and photovoltaic devices can supply higher on-state current and larger output power, respectively, compared to their NW/NB counterparts. Thin-film transistors (TFTs) with high on-state current are desirable for such macroelectronics applications
1 Author to whom any correspondence should be addressed.

as active matrix LCD display etc [5–8]. At present, parallel aligned semiconductor NW and carbon nanotube (CNT) arrays have been used to fabricate nano-TFTs [6, 9]. Their performance is demonstrated to be better than those of the conventional TFTs due to higher carrier mobility. However, the coexistence of metallic and semiconducting CNTs in a product makes the device fabrication process more complex. Namely, semiconducting CNTs have to be pre-separated for the fabrication of TFTs [9]. On the other hand, the electrical properties of NWs are usually nonuniform [10]. This lowers the reliability of NW-based TFTs. The intrinsic deficiencies of NW and CNT array-based nano-TFTs can be solved by employing single-crystalline semiconductor nanosheets as the alternative material. Development of semiconductor nanostructure/Si heterojunction light emitting diodes (LEDs) is an important step toward realizing Si-based optoelectronic integration [11]. Compared to the common lateral electrode structure of the semiconductor nanostructure/Si heterojunction LED [12, 13], the
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top electrode structure has a much lower series resistance, a larger active region, and a higher injection current favorable to high-efficiency electroluminescence (EL) and lasing [14, 15]. While it is difficult to fabricate a top electrode structure in semiconductor NW (NB)/Si heterojunction LEDs with proper insulation, the use of nanosheets makes a top electrode structure possible. To our knowledge there have been only a small number of reports (including our own) on 2D semiconductor nanosheets and related devices. We think one of the main reasons is that high quality 2D semiconductor nanosheets with appropriate electron or hole concentrations required for device application are still hard to obtain in bulk quantities [1–3, 16]. In this paper, we report the synthesis of high quality single-crystalline n-type CdS nanosheets made via a chemical vapor deposition (CVD) growth method in Cd-enriched ambient. The growth mechanism of the CdS nanosheets is discussed. We have fabricated, for the first time to our knowledge, novel nano-TFTs based on individual CdS nanosheets. Among the nano-TFTs reported so far, our nanosheet-based TFTs have the highest on–off ratio and peak transconductance. We also fabricated n-CdS nanosheet/p+ -Si heterojunction LEDs with a top electrode structure. Their electroluminescence (EL) properties have been studied.

beam lithography (FEI Strata DB 235) followed by a thermal evaporation and lift-off process. Herein, the source and drain electrodes were fabricated along the lateral direction of the nanosheet to maximize the on-state current. The underlying p+ -Si was used as the back gate. The CdS nanosheet/p+ -Si heterojunction LEDs with top electrode structure were fabricated as follows (figure 4(a)): first, a silicon-on-insulator (SOI) substrate with a 100 nm thick p+ -Si layer and a 380 nm insulator layer was dipped in diluted HF solution for 10 s to remove the native oxide layer on the p+ -Si. Then a CdS nanosheet suspension was dropped onto the SOI substrate. After that, a photoresist pad was patterned to cover a large part of a nanosheet by a UV lithography and development process. The photoresist together with the uncovered part of the nanosheet was then used as the mask for the following p+ -Si etching process by an inductively coupled plasma (ICP) etching technique. Later, the photoresist was removed by acetone. Finally, an In/Au (10 nm/100 nm) Ohmic contact electrode was made on top of the nanosheet by UV lithography followed by a thermal evaporation and lift-off process. It is worth noting that because an undercut was formed during the ICP etching process, the In/Au electrode does not contact with the underlying Si at the edge of the nanosheet [17].

2. Experimental section
The n-type CdS nanosheets were synthesized via a CVD method. CdS (99.995%) powders were used as the source, and pieces of Si wafers covered with 10 nm thick thermally evaporated Au catalysts were used as the substrate. A Cd (99.999%) particle was used as the dopant. Under the Cd-enriched synthesis ambient, the S vacancies created lead to an n-type conductivity of our CdS nanosheets. Prior to heating, a quartz tube inside a tube furnace was cleaned with high-purity argon gas for 1 h. Then under a constant argon flow rate of 150 sccm, the furnace was rapidly heated to 850 ◦ C. After that, a quartz boat loaded with CdS, Cd, and Si substrates in sequence was inserted into the center of the tube, with CdS at the upstream side of the argon gas flow. During the growth process, the local temperatures for CdS, Cd, and the Si substrates were about 850 ◦ C, 700–750 ◦ C, and 600–700 ◦ C, respectively. The synthesis process took about 1 h under atmospheric pressure. The resulting material was characterized using a field emission scanning electron microscope (FESEM) (FEI Strata DB 235) and a high-resolution transmission electron microscope (HRTEM) (Tecnai F30). The room-temperature electrical transport properties of the devices were measured with a semiconductor characterization system (Keithley 4200). The EL measurements were performed with a microzone confocal Raman spectroscope (Horiba Jobin Yvon, LabRam HR 800) equipped with a color charge-coupled device camera. The individual CdS nanosheet TFTs were fabricated as follows: first, the CdS nanosheet suspension was dropped on oxidized Si substrates. The SiO2 layer was about 600 nm thick. Then, Ohmic contact In/Au (10 nm/100 nm) electrodes were defined on a CdS nanosheet by electron

3. Results and discussion
FESEM observations reveal that the material consists of a large quantity of sheet-like nanostructures with widths in the 10–300 µm range and lengths ranging from submillimeter to several millimeters (figure 1(a)–(d)). The thickness of these nanosheets ranges from 40 to 100 nm, as measured by an atomic force microscope (AFM). Figure 1(e) shows the AFM measurement results of the CdS nanosheet used in the later TFT device. The thickness of the CdS nanosheet is about 60 nm. Each CdS nanosheet has a smooth surface and uniform width. Wider sheets are usually thicker than narrower ones. Figure 2(a) shows a low magnification TEM image of an individual nanosheet, showing that the nanosheet is flat, smooth, and uniform in width. Figure 2(b) shows the HRTEM image of the nanosheet from figure 2(a). The directions of crystal planes with spacings of about 0.36 nm and 0.67 nm can be seen parallel and perpendicular to the growth direction, respectively. According to the JCPDS card (no. 80-0006), ¯ and (0001) planes of these planes can be indexed as the (1010) the hexagonal wurtzite CdS. The upper-left inset of figure 2(b) is the corresponding selected area electron diffraction (SAED) ¯ 10] ¯ zone axis. Corresponding pattern recorded along the [12 Miller indices are labeled. The HRTEM image together with the SAED pattern reveals that the nanosheet is single crystal ¯ and lateral [0001] growth CdS with the longitudinal [1010] directions. The 2D nanostructure is generally considered to grow through two processes: an Au-catalyzed faster vapor–liquid–solid (VLS) growth process creates the longitudinal dimension, and a slower vapor–solid (VS) growth process creates the lateral dimension [2, 3]. In our case, the lateral growth direction of CdS nanosheets is [0001]. We think

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Figure 1. (a)–(d) FESEM images of as-synthesized CdS nanosheets of different sizes. (e) AFM measurement results for a CdS nanosheet used in the later TFT device. The thickness of the CdS nanosheet is about 60 nm.

Figure 2. (a) Typical TEM image of a nanosheet. (b) HRTEM image of the nanosheet shown in panel (a). Upper-left inset: the ¯ 10] ¯ zone axis. corresponding SAED pattern recorded along the [12


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that, as is the case in CdSe [3], the Cd-terminated (0001) surface is also the active growth plane in CdS. In our growth process, the Cd-enriched ambient may benefit the formation of a Cd-terminated (0001) surface, and thus benefit lateral growth. This Cd-enriched CVD method can also be applied to synthesize CdSe and CdSx Se1−x nanosheets [18, 19]. The inset of figure 3(a) shows an optical image of a typical CdS nanosheet TFT. The length L (channel width of the TFT) and thickness T of the CdS nanosheet are about 57.1 µm and 60.0 nm, respectively. The spacing W (channel length of the TFT) between the source and drain electrodes is about 3.6 µm. Figure 3(a) shows the I –V curve measured between the source and drain electrodes at a gate voltage of VG = 0 V. It shows a linear behavior, confirming the Ohmic contacts between the In/Au electrodes and the CdS nanosheet. Electrical transport measurements show typical n-channel transistor characteristics. From the relation of source–drain current IDS and VG shown in figure 3(b), we can obtain the threshold voltage Vth and on–off ratio to be about −14.4 V and 1.7 × 109 , respectively. To our knowledge, this is the largest on–off ratio reported so far for nano-TFTs. The subthreshold swing is about 166 mV/dec from the linear region of the IDS –VG curve, which is determined by the equation S = ln 10[dV G /d(ln IDS )] [20]. The inset of figure 3(b) shows the transconductance (G = dIDS /dVG ) versus VG curve (VDS = 1 V). The peak transconductance (Gm ) obtained is about 14.1 µS, which is to our knowledge the highest value for semiconductor nano-TFTs reported so far [6]. High transconductance is a critical measure of transistor performance, which determines the voltage gains of transistor-based devices including amplifiers and logic circuits [6, 21]. The electron concentration (ne ) and the electron mobility (µe ) can be estimated by ne = CG Vth /eWLT , and µe = Gm (W 2 /CG VDS ), where CG is the gate capacitance and q is the electron charge [13]. Assuming a parallel plate capacitor model in our CdS nanosheet TFTs, CG = εε0 WL/h, where ε and h are the relative dielectric constant and thickness of SiO2 , we deduce ne ≈ 8.63 × 1016 cm−3 and µe ≈ 154.5 cm2 V−1 s−1 . We attribute the n-type conductivity of our CdS nanosheets to S vacancies created in the Cd-enriched synthesis ambient [22]. By increasing the temperature of the Cd particle in the synthesis process, we can obtain CdS nanosheets with higher electron concentrations (∼1018 cm−3 ). With these CdS nanosheets, we fabricated the n-CdS nanosheet/p+ -Si heterojunction LEDs with a top electrode structure. A typical I –V curve of such an n-CdS nanosheet/p+ -Si heterojunction LED is shown in figure 4(b). We can see the good rectification characteristic. When the forward bias is above 5 V, green light spots can be seen from the LEDs even with the naked eye. The inset of figure 4(b) shows a room-temperature EL image of such a LED at 9 V recorded by an optical microscope (Olympus BX51M). We can see many bright light spots along the edges of the CdS nanosheet. Note that we can also see several light spots at the edges of the Au electrode. We attribute this to light scattering from defects or adhered particles on the nanosheet and the Au electrode.

Figure 3. Electrical transport properties of a typical unit of such CdS nanosheet TFTs. (a) I –V curve measured between the source and drain electrodes at VG = 0 V. Inset: the optical image of the CdS nanosheet TFT. (b) IDS –VG curve of the nanosheet TFT shown in panel (a) (VDS = 1 V). The inset is a G–VG curve of the TFT at VDS = 1 V.

Figure 4(c) shows the EL spectrum measured at one light spot. Only an intense sharp CdS band-edge emission around 507.7 nm with full width at half-maximum (FWHM) as small as 14 nm can be observed. The EL spectrum is similar to the PL spectrum of the CdS nanosheet (not shown here), which suggests the high quality of the nanosheet. Further improvement of the LED, which aims at realizing Si-based electrically driven laser, is still ongoing in our group.

4. Conclusion
High quality single crystal n-type CdS nanosheets were synthesized via a CVD method in a Cd-enriched ambient. Using these nanosheets, high-performance nano-TFTs were fabricated. An on–off ratio higher than 109 and a maximum transconductance as high as 14.1 µS were obtained at room temperature, which is to our knowledge the best performance for semiconductor nano-TFTs reported so far. CdS nanosheet/p+ -Si heterojunction LEDs with a top electrode structure were also fabricated. Their EL spectra are dominated by an intense sharp band-edge emission and are free from deep-level defect emissions. Our results demonstrate that the 2D CdS nanosheets,

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Figure 4. (a) Schematic illustration of the fabrication process for an n-CdS nanosheet/p+ -Si heterojunction LED with a top electrode structure. (b) Typical I –V curve of such an n-CdS nanosheet/p+ -Si heterojunction LED. Inset: EL image recorded at a forward bias of 9 V. The scale bar is 20 µm. (c) Normalized room-temperature EL spectrum measured at a certain light spot shown in panel (b).

which take the advantages of both NWs (NBs) and thin film, are promising material in developing novel electronic/optoelectronic nanodevices.

The authors would like to thank Dr W L Chen for improving the English in this paper. This work was supported by the National Natural Science Foundation of China (nos 61125402, 51172004, 11074006, 10874011, 50732001), the National Basic Research Program of China (nos 2012CB932703, 2007CB613402).

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