R.Ubar, J.Raik, T.Evartson, M.Kruus, H.Lensen, Tallinn Technical University Raja 15, 12618 Tallinn Estonia {raiub, jaan, teet}@pld.ttu.ee, {kruus, hl}@cc.ttu.ee

ABSTRACT To cope with the complexity of today’s digital systems in diagnostic modelling, hierarchical approaches should be used. In this paper, the possibilities of using Decision Diagrams (DD) for diagnostic modelling of digital systems are discussed. DDs can be used for modelling systems at different levels of representation like logic level, register transfer level, instruction set level. The nodes in DDs can be modelled as generic locations of faults. For more precise general specification of faults logic constraints are used. To map the physical defects from transistor level to logic level a new functional fault model is introduced.

functional modelling lies in the possibility of constructing test plans on higher levels, and modelling faults on more detailed lower levels. The drawback of traditional multi-level and hierarchical approaches to digital test lies in the need of different languages and models for different levels. Most frequent examples are logic expressions for combinational circuits, state transition diagrams for finite state machines (FSM), abstract execution graphs, system graphs, instruction set architecture (ISA) descriptions, flow-charts, hardware description languages (HDL, VHDL, Verilog etc.), Petri nets for system level description etc. All these models need different manipulation algorithms and fault models which are difficult to merge in hierarchical test methods. Better opportunities for hierarchical diagnostic modelling of digital systems provide Decision Diagrams (DD) [4-9]. Binary DDs (BDD) have found already very broad applications in logic design as well as in logic test [4-5]. Structurally Synthesized BDDs (SSBDD) are able to represent gate-level structural faults directly in the graph [6,7]. Recent research has shown that generalization of BDDs for higher levels provides a uniform model for both gate and RT level or even behavioral level test generation [8,9]. On the other hand, the disadvantage of the traditional hierarchical approaches to test is the traditional use of gate-level stuck-at fault (SAF) model. It has been shown that high SAF coverage cannot quarantee, high quality of testing [10]. The types of faults that can be observed in a real gate depend not only on the logic function of the gate, but also on its physical design. These facts are well known but usually, they have been ignored in engineering practice. In earlier works on layout-based test techniques [11,12], a whole circuit having hundreds of gates was analysed as a single block. Such an approach is computationally expensive and highly impractical as a method of generating tests for real VLSI designs. To handle physical defects in fault simulation, we still need logic fault models to reduce the complexity of simulation. In this paper, we present, first, in Section 2 a method for modelling physical defects by generic Boolean differential equations which gives a possibility to map the defects from physical level to logic level. A

KEY WORDS Digital systems, faults and defects, modelling, simulation, test generation, Boolean derivatives, decision diagrams.

1. Introduction
The most important question in testing today’s complex digital systems is: how to improve the testing quality at continuously increasing complexities of systems? Two main trends can be observed: defect-orientation and highlevel modelling. To follow the both trends, hierarchical approaches should be used. One way to manage hierarchy in a uniform way at different levels is to use decision diagrams (DD). Traditional low-level test methods and tools for complex digital systems have lost their importance, other approaches based mainly on higher level functional and behavioral methods are gaining more popularity [1-3]. However, the trend towards higher level modelling moves us even more away from the real life of defects and, hence, from accuracy of testing. To handle adequately defects in deep-submicron technologies, new fault models and defect-oriented test methods should be used. But, the defect-orientation is increasing even more the complexity. To get out from the deadlock, these two opposite trends – high-level modelling and defect-orientation – should be combined into hierarchical approach. The advantage of hierarchical approach compared to the high-level

or in defect-oriented test generation.1.. x2. x2. or by carrying out real experiments to learn the physical behavior of different defects. for checking if the condition (2) is fulfilled. Mapping faults from lower Mk. to map a lower level fault d ∈ Rk to the higher level variable xk. x n d ) = d f ∨ df d (1) as a function of a defect variable d.. either in defect-oriented fault simulation.. x3 x5 The described method represents a general approach to map an arbitrary physical defect onto a higher (in this case. and y* = f if d = 0. fault simulation. The parametric modeling of a defect d by equations (1) and (2) allows us to use the constraints Wd = 1. logic) level. ∨ d nW dn 2. A functional fault representing a defect d can be described as a couple (dy. The event of erroneous value on the output y of a component can be described as dy = 1. Hierarchical Approach to Test The method of defining faults by logic conditions Wd allows us to unify the diagnostic modelling of components of a circuit (or system) without going into structural details of components and into the diagnostic simulation of interconnection network of components. and for the fault-free case d y = 0. Modelling Defects and Faults Consider a Boolean function y = f (x1. FFM can be regarded as a uniform interface for mapping faults from a given arbitrary level of abstraction to the next higher level. The conditions Wd can be used both in fault simulation and in test generation. or fault diagnosis purposes. Section 7 concludes the paper. x 2 . Wd). WFk Component k represented by a Low level variable xk. DDs are used. By the described approach a physical defect in a component can be represented by a logical where for j = 1. Denote by Wd the condition when the fault d ∈ Rk will change the value of xk.…n: dj ∈ Rk. to solve the equation (2) when the defect d should be activated and tested. 2. To the higher level event dxk = 1. Introduce a Boolean variable d for representing a physical defect in the component.. a solution of the equation Wd = 1 is to be found. At the presence of a physical level defect d.2) High level as the output of a module Mk. the value of d as a parameter is equal to 1. In fault simulation (or in fault diagnosis) an erroneous value of xk (denoted by a Boolean differential dxk=1) can be explained as dxk → d1W d 1 ∨ d 2W d 2 ∨ . For hierarchical diagnostic modelling. In other words. WSk Bridging fault Associate with k a Environment set of faults Rk = RFk ∪ RSk where RFk is the subset of Mapping faults in the module Fig. …. Introduce for the block C a generic parametric function y* = f * ( x1 . In test generation.. In Section 4 SSBDDs are presented for logic level test generation and fault simulation. and RSk is a level to higher level subset of structural faults (defects) in the “network neighbourhood” of Mk. we set into correspondence a lower level event dj if the condition Wdj = 1 is fulfilled. xn) implemented by an embedded component C in a circuit.generalization of the SAF model called Functional Fault Model (FFM) is presented in Section 3. where dy means Boolean differential. constraint Wd = 1 to be fulfilled for activating the defect. which may affect the value y by converting f into another function y = fd (x1. …. For hierarchical testing purposes we should construct for each module Mk of the circuit a list of faults Rk with logical conditions Wd for each fault d ∈ Rk. The set of conditions WFk for the functional faults d ∈ RFk of the . xn). Section 5 explains how the hierarchical approach can be implemented by using higher level DDs. In both cases. 3. The solutions of the Boolean differential equation ∂y * Wd = = 1 (2) Fig. we will have a higher level erroneous signal dy = 1 iff the condition Wd = 1 is fulfilled. Mapping Consider a node k in a circuit (Fig. which describes the behavior of the component simultaneously for both possible fault-free and faulty cases.. Wd describes how a lower level fault d (a defect either in a component or in the network) should be activated at a higher level to a given node. For the faulty case.2. Denote by WFk the set of conditions Wd activating the defects d ∈ RFk and by WSk the set of conditions Wd activating the defects d ∈ RSk. To find Wd for a given defect d we have to create the corresponding logic expression for the faulty function fd either by logical reasoning or by carrying out directly defect simulation. Transistor circuit ∂d with a short describe the conditions which activate the defect d on a line y. Some experimental data are presented in Section 6 to illustrate the efficiency of the method. By using WFk and WSk we can set up a mapping of faults from a lower level to a higher level for test generation. x1 x2 x4 Short y* = f d if d = 1.

is a directed acyclic graph Gy = (M.4. iff for all the possible vectors Xt ∈ {0. so that y = f(Xt) = x(mT). Modelling Digital Circuits with BDDs Consider first. the following graph theoretical definitions of the BDD. (3) where ∂Y/∂yM means the fault propagation condition calculated by high-level modeling.5] because all the procedures defined further for SSBDDs are based on the topological reasoning rather then on graph symbolic manipulations as traditionally in the case of BDDs.X) represents a Boolean function y=f(X). mT) is activated. 1 2 71 3 4 5 6 & 7 Macro & & a d 72 & 73 & & b e & c y a) y 6 73 W = ∂Y/∂yM ∧ ∂ yM /∂yG ∧ Wd = 1. In Fig.Γ. We used the notation ∂Y/∂yM to denote the dependency of Y from yM as an analogue of Boolean derivative for higher level (e. a general hierarchical test Test F W k concept based on System parametric fault Network WF modeling and the k of modules functional fault model for a 3Test W S ki Fk level system is illustrated. mT) is activated so that y = f(Xt) = x(mT). Unlike the traditional BDDs [4-5]. yM an output variable of a logic level module and yG the output of a logic gate with a physical defect d. By the value of x(m) = e. We use the graph-theoretical definitions instead of traditional ite expressions [4. Consider a BDD Gy=(M. then m0 is the successor of m for the value x(m) = 0 and m1 is the successor of m for x(m) = 1.Γ. mT) from the root node m0 to one of the terminal nodes mT∈ MT. 1 1 2 71 5 72 0 b) Fig.3. A terminal node mT ∈ MT = {mT.module can be found by low level test generation for the defects in the module. The BDD is called a structurally synthesized BDD (SSBDD) iff there exists one-to-one correspondence between literals x ∈ X and nodes m ∈ MN given by the set of labels { x(m) ⎜ x ∈ X. The set of conditions WSk for the structural faults d ∈ RSk in the environment of the module can be found as explained in Section 2.g. ∂yM/∂yG is the fault propagation condition (Boolean derivative) calculated by gate-level modeling. In the following we show how we can calculate Boolean derivatives with BDDs and thereafter how we can generalize this operation for higher level representations based on high-level DDs. gate and defect Fig. SSBDDs [7] support structural representation of gate-level circuits in terms of signal paths.1}n to some value.1} and is called leaf.Γ. … . and have exactly two successors. dispite of that there is no mathematics available for calculating Boolean derivatives at higher (not logic) levels. We say that a BDD Gy = (M. RT level) of abstraction for digital systems. xn). we can create SSBDDs with one-to-one correspondence between graph 4.X) with a set of nodes M and a mapping Γ from M to .1}n a path l(m0. the nodes m ∈ MN are labelled by x(m) where x ∈ X and ⎜M ⎜ = ⎜X ⎜. X = (x1. then the condition to detect the defect d on the observable test point Y is S Functional approach Structural approach M. we say the edge between nodes m ∈ M and me ∈ M is activated.X) where X is the vector of literals of a function y = P(X) represented in the equivalent parenthesis form [7]. while all nonterminal nodes m ∈ MN are labelled by variables x ∈ X. By superposition of DDs [7]. Let Y be a test RTL variable (an observable point).. Definition 1. e ∈ {0. mT. Definition 2.1} is labelled by a constant e∈{0. Hierarchical approach to levels.3. Definition 4. m ∈ MN}. Let us denote the associated with node m variable as x(m). and iff for all the possible vectors Xt ∈ {0. M = MN ∪ MT consists of two types of nodes: nonterminal MN and terminal MT nodes.1}n a path l(m0. Module Network F Consider a task of W ki of gates defect oriented fault simulation in a system which is Test W d ki F ki represented at Circuit Gat e three levels: RTL. Consider a situation where all the variables x ∈ X are assigned by a Boolean vector Xt ∈ {0. The activated by Xt edges form an activated path l(m0. and Wd is the functional fault condition calculated from (2) by the gate preanalysis.1}.0. A BDD that represents a Boolean function y=f(X).x2. Digital circuit and its SSBDD Definition 3.

1). mT. we usually partition the system into control and data parts. and (¬1. For non-terminal nodes m∈MN. A decision diagram Gk represents a function zk = fk (zk.2. zk.4b. For simplicity. the following paths in Gy are to beactivated: 1) l(m0. An activated path l(m0. we have to describe these components by their corresponding functions which can be represented by DDs. which represent connections between components. so that zk = z(mT) is valid.2. fk ∈ F. In RTL descriptions.. Terminal nodes in DDs correspond to the data path. . Definition 6. the right-hand edge corresponds to 1 and the lower-hand edge to 0). additional constraints W=¬x6∧x7=1 is to be used..p). By me we denote the successor of m for the value z(m) = e.mT. registers.1. which are finite. the subsets of input and output variables.0). Also. Activated edges. m).1 lm. correspondingly. and m ∈ MN. Calculation of Boolean Derivatives with SSBDDs ∂y = 1 for ∂x 7 . which produces the pattern: x1x2x3x4x5x6 = 11xx00. 71). Using SSBDDs.¬1. We can now generalize Procedure 1 for higher level functions with the goal to create dependencies between high level variables as we used the notation ∂Y/∂yM in (3).p) = fk (Zk ) where zk ∈ Z. The value of the function y = 1 for this pattern is determined by the value of the variable x5 = 1 in the terminal node of the path. inputs and outputs of the network. × v(zk.4a by using SSBDD means to use the Procedure 1 for the node m = 71 in the graph in Fig. …. V(z) denotes the set of possible values for z ∈ Z.1 SSBDD mT. Calculating of high-level dependencies of signals (conformity test). To make a system level variable zk depending on an argument z(m)∈Z (denoted as lm m m0 m1 lm. and they are labelled by state and output variables of the control part serving as addresses or control words.0).4. Fig. Consider a digital system zk=f(Z) represented by a single graph Gk.. The following paths should be activated.1 the circuit in Fig. The whole circuit can be represented as a network of tree-like subcircuits (macros). Procedure 2.p) = fk (Zk) iff for each value v(Zk) = v(zk. Then.0 mT. (6. 3) l(m0. Modelling Systems with High Level DDs Consider now a digital system S = (Z. terminal nodes with constants 0 and 1 are omitted: leaving the graph to the right corresponds to y = 1.nodes and signal paths in the circuit. and Zk ⊂ Z.5. are next state functions. and they are labelled by the data words or functions of data words. or algebraic expressions of z ∈ Z. In some simple cases a digital system can be represented as a single DD. The labels can be ether variables z ∈ Z. By bold lines a full activated path is highlighted in the graph corresponding to the input pattern x1x2x3x4x5x6 = 110100.0 Fig.mT. The edge (m. Definition 5. . or constants. or data manipulation blocks. it is possible to ascend from the gate-level to a higher macro level without loosing accuracy of representing gate-level signal paths. and each of them represents a signal path in a circuit.2. which connect mi and mj make up an activated path l(mi. The graph contains 7 nodes. and down. zk. Calculation of Boolean derivatives. which updates the test vector to 111x00. ∂z k = 1 ) for the system function zk=f(Z) with DD Gk. When using DDs for describing complex digital systems. zk. A decision diagram (denoted as DD) is a directed acyclic graph Gk = (M. we have to first. mT) from the initial node m0 to a terminal node mT is called full activated path. which correspond to buses. Nonterminal nodes in DDs correspond to the control path. values of variables on edges of the SSBDD are omitted (by convention. mT. 2) l(m1. Γ. an onto function exists between the values of z(m) and the successors me ∈ Γ(m) of m.1). To test a physical defect of the bridge between the lines 6 and 7. Let F be the set of digital functions on Z: zk = fk (zk. Depending on the class of the system (or its representation level). where x ∈ X. z) where M is a set of nodes.1) × v(zk. for the state variables z ∈ ZSTATE ⊂ Z. Some of the functions fk ∈ F. zk. and Γ(m) ⊂ M denotes the set of successor nodes of m ∈ M. shows a representation of a tree-like combinational circuit by a SSBDD. me) which connects nodes m and me is called activated iff there exists an assignment z(m) = e. where Γ(m) ≠ ∅. Root node Denote by X ⊂ Z and Y ⊂ Z.1. The nodes m ∈ M are marked by labels z(m). Boolean vectors or integers). we may have various DDs. Procedure 1. represent the system by a suitable set of interconnected components (combinational or sequential subcircuits). To solve ∂y a Boolean differential equation = 1 for the ∂x (m) function y=f(X) with SSBDD Gy. mj). Γ is a relation in M. a full path in Gk to a terminal node mT ∈MT in Gk is activated. each of them represented by a SSBDD. to y = 0. ∂z ( m) . To solve the Boolean differential equation 5. which is activated on the line 7. (¬1.2) × .. where nodes have different interpretations and relationships to the system structure. F) as a network of components where Z is the set of variables (Boolean.

m). correspondingly.the following paths are to beactivated: 1) l(m0. l(m. e. y2.6.R2. y4 represent the control signals. R2 and R3 represent registers.). l(m.m) for testing the multiplier are to be generated at low level by an arbitrary ATPG. and the data DATA = (R1.D. To generate a scanning test for the node R1*R2 of the DD in Fig. The data vector DATA = (R*1. y2 . R1. Root node lm m DD m1 m2 lm. y3 = D. The scanning test consists in cyclically run sequence: For all (a. y2. the control path). M1. Each node in DD represents a subcircuit of the system (e. e. a path l(m0. M3 are multiplexers.2) ≠ … ≠ z(mT. similarly as in the case of SSBDDs. in the DD only 3 control variables are visited during simulation.1. m4) = (y3.2.g. y3.m. IN*) is found by solving the inequality R1+R2 ≠IN ≠ R1 ≠ R1*R2. y3. R2.g.0. … R1.1. In Fig. Load: R2 = b.R2. and only a single data manipulation R2 = R1*R2 is carried out. y4 represent multiplexers and decoders. y2.1. Read R2].2.g.2.6.mT.7 the result of simulating the vector y1. IN = 0.1 lm. The variables R1. the following paths are to be activated l(m0. Read R2]. y3. the nodes y1. R1). the data path). Experimental results We have carried out two types of experiments: to show the possibility of increasing the accuracy of diagnostic modeling digital circuits by introducing the defect-based functional fault model.3}: [Load: R1 = R*1. y4 = 0. R1. guided by the values of input variables until a terminal node is reached. In test pattern simulation.12 is R2 = R1*R2 = 60 (bold arrows mark the activated path). IN = IN*. m) = (y4. y3). To test a node means to test the corresponding subcircuit.b)∈DATA: [Load: R1 = a. b) Fig.0.R2. y3. The conformity test consists in cyclically run sequence: For all D ∈ {0.2 lm. y2. y2. m3) = (y3. Calculating RT level dependencies with DDs Solutions find by Procedure 2 are called conformity tests. 6. l(m. the integer variables y1. according to the hierarchical approach described). y1 y2 y3 y4 R1 • a M1 b • + • c e M3 R2 • • IN M2 * d a) R2 y4 0 1 2 #0 R2 y3 1 2 3 0 y1 1 IN R1 y2 0 R1 * R2 1 IN* R2 0 R1 + R2 IN + R2 It is easy to notice that the scanning test is a particular case of the conformity test.2. .k) where k = | v(z(m)) |. y3. R1*R2) that produces a test vector y1.n mT. and the proper data are to be found by solving the inequality z(mT. Apply: y2 = 0.6. on the lower level representation of z(m). y4 = 2.10. We differentiate two testing types used for digital systems: scanning test (for testing terminal nodes in DDs.1 mT.3. the following path is to beactivated: l(m0. m2) = (y3. R1+R2). Scanning test. y4 = 2. and results in a similar way as the conformity test from generalization of Procedure 1. In Fig. and to show the the possibility of increasing the speed of diagnostic modelling by using multi-level DD-based approach. To generate a scanning test for a node m ∈ MT in Gy. R1*R2) is to be activated.7 a RTL data-path and its high-level DD is presented. y3 = 3. They check if a system is working in a particular working mode defined by the value of a (control) variable z(m) properly.1) ≠ z(mT.e). y4.2 mT. To generate a conformity test for the node y3. Representing a data path by a high-level DD Procedure 3. a path is traced in the graph. Instead of simulating by a traditional approach all the components in the circuit. and conformity test (for testing nonterminal nodes. IN).n mn Fig. m) = (y4.7. 2) for all the values of e ∈ v(z(m)): l(me. Apply: y1 = 0. M2. y2 = 0. m1) = (y3. l(m. The whole DD describes the behaviour of the input logic of the register R2. R*2. and the functions R1+R2 and R1*R2 represent the adder and multiplier. m).2. Load: R2 = R*2. y1.g. IN represents the input bus. and the test patterns for testing the function z(m) should be generated (e.

[12] M. Combining Functional and Structural Approaches in Test Generation for Digital Systems. Rudnick. BDDs and Applications for VLSI CAD. SYNOPSYS. [7] R.F.. pp. In Table 2. Multiple Valued Logic. For hierarchical diagnostic modelling of digital systyems.6 8 14 79 50 1198 151 296 Average FC 76.Table 1: Experiments of defect oriented test generation Number of defects Circuit All Redundant defects Gates 1 c432 c880 c2670 c3540 c5315 c6288 2 1519 3380 6090 7660 14794 24433 3 226 499 703 985 1546 4005 Syst 4 0 5 61 74 260 41 Defect coverage 100% stuck-at fault ATPG 5 78. Tallinn. 75% of defect coverage for c880 gives not much confidence for this test.9 87. W. No 3. T.Ubar. of European Test Conference. [6] R. 1991 [2] J. comparison of test generation results of three ATPG tools are presented on 6 hierarchical benchmarks.1 95.M. and that the real test efficiency is actually 99.pp. The next coverage measure shows the test efficiency. Spring 1996.317-329. G. The tools used for comparison include HITEC [1]. 1993. [3] E. Faults 2 454 1938 2036 5388 6434 10008 HITEC [1] 3 81. [8] R. An interesting remark is. which is a logic-level deterministic ATPG and GATEST [3] as a genetic-algorithm based tool.Maly.9 100 New tool 8 100 100 100 99.Sudbrock. for circuit c2670 the defect coverage obtained by SAF tests was more than 1.V.214-218. The experimental results show the high speed of the new ATPG tool which is explained by the efficient algorithms based on DDs and by the hierarchical approach used in test generation Table 1 presents the results of investigating the defectoriented test generation. M. 38. Test Synthesis with Alternative Graphs. The system contains gate-level EDIF interface which is capable of reading designs of CAD systems CADENCE. OPA (Overseas Publ.0 99. 2005.3 99. 1998.6 98. Proc. No8. J. pp. 1996. IEEE Trans. Speed up of behavioral ATPG. multi-level DDs were proposed as an efficient model for representing digital systems in a uniform way at different representation levels. Vol.1 82. Patel. 141 p. References [1] T. on Computers. of the 10th IEEE European Test Symposium. M. Patel. Only using the new ATPG allows to prove that most of the undetected defects are redundant. IEEE DATE.3 65. DOT: New Deterministic Defect-Oriented ATPG Tool. Conclusion A method for modelling defects by a functional fault model was developed as a general basis for hierarchical approach to digital test. Design Automation (EDAC).2 94. Proc.8 operating . W. VIEWLOGIC. IEEE Design&Test of Computers. [5] S. 1989. Greenstein. 1993. 1994. [4] R. March 9-12.0 74. H.5 96. Santucci et al.) N. 154-157. Huisman. 888-899.3 98. while column 5 shows the ability of logic level SAF-oriented ATPG to cover physical defects.9 52. H.2 4 170 728 1243 2090 49020 13320 Gatest [3] 5 91.48-57. Acknowledgements: This work has been supported by the Estonian Science Foundation grants 5649 and 5910.4 77.Guggenbuhl. pp. [11] P. Fault Coverage and Yield Predictions: Do We Need More than 100% Coverage? Proc. 1993. R.4 6 75 739 822 6229 2459 3000 DDapproach 7 89. Microelectronics Reliability.0 96. Column 3 reflects the number of gate level redundant defects.4.5 97. IEEE Trans.5 88.Nigh and W. [13] J. pp.0 79.E. Multi-Valued Simulation of Digital Circuits with Structurally Synthesized Binary Decision Diagrams. May 22-25.Ubar. Gordon and Breach Publishers. Vol.1 80. In this value. Layout . Ass. 180-187.Raik.Kuzmicz. Table 2: Comparison of ATPGs Circuit 1 Gcd Sosq Mult Ellipf Risc Diffec 7.7 99.667-690. Experiments were carried out with a new defect-oriented Automated Test Pattern Generator (ATPG) [13].0 6 99. 1986.7 96. 30th ACM/IEEE DAC. gate level redundancy of defects (column 6) and circuit level redundancy of defects (column 7) are taken into account. M.66 giving finally a good confidence to the test.0 99. ICCAD. Column 2 shows the total number of defects in the fault tables summed over all the gates belonging to the netlist. Vol.9 87. Kluwer Academic Publishers.1 77.0 96.8 7 99.6 75. Niermann.6 % lower than the result of the proposed tool. Column 8 shows the number of defects covered by the new ATPG.Ubar.141-157. R. 698-704. Proc. Graph-based algorithms for Boolean function manipulation.Jacomet and W. The experiments prove that relying on 100 % SAF test coverage would not necessarily guarantee a good coverage of physical defects. on CAD.9 100 100 system.Raik. MENTOR GRAPHICS. J.1998.pp. Layout-Dependent Fault Analysis and Test Synthesis for CMOS Circuits.Pleskacz. pp. 12.8 96.0 79. S. pp. both. [9] J.Ubar.Driven Test Generation.9 80. Niermann.C35. Sequential circuit test generation in a genetic algorithm framework. 1999. HITEC: A test generation package for sequential circuits. Sequential Circuit Test Generation Using Decision Diagram Models.9 The experiments of the DD-based ATPG for digital systems were run on a 366 MHz SUN UltraSPARC 60 server with 512 MB RAM under SOLARIS 2.Ubar.7 99.Bryant. European Conf. pp.9 69. 736-740. of DAC. J. 92-96. [10] L.5 98. that up to 25% of the defects were proved redundant by the new tool and can therefore not be detected by any voltage test. Proc. Minato. Munich. For example. We used the ISCAS85 suite as benchmarks. etc. In column 4 circuit level redundant defects are counted.