SPRING2007

ARROW ARM SOLUTIONS GUIDE

ARM Solutions
www.arrownac.com/arm

ARM SUPPORT
4 Arrow Services and Solutions

Table of Contents

ARM CORES
8 ARM7TDMI 10 ARM920T 12 ARM926EJ-S 14 ARM966E-S 16 ARM1136J(F)-S 18 ARM Cortex-A8 20 ARM Cortex-M3 22 ARM CortexR4(F) 24 Intel XScale®

It’s a fact. Arrow Electronics is the only distributor and approved training center for ARM tools in North America. Which means we can solve your ARM-powered design challenges efficiently and completely. Our broad line card features more than a dozen major silicon suppliers offering ARM technology and our innovative services can help you at every point in your design cycle. Whether you need support for ARM software development or architecture, you can rely on Arrow to deliver up-to-date and accurate technical information from well-versed industry experts. Arrow’s vast line card, services, and unparalleled expertise deliver comprehensive ARM solutions that get you to market faster.

ARM SUPPLIERS

34 Freescale i.MX31 36 Intel® Intel® Network Processors and Intel® I/O Processors

40 NXP LPC210x | LPC23xx and LPC24xx | LPC2478 46 STMicroelectronics STR7 and STR9 Families | STR730F | STR710F | STR750F | STR910F 54 Texas Instruments DaVinci™

TOOLS
58 IAR IAR Embedded Workbench Version 4.41 for ARM 60 Keil The Keil RealView Microcontroller Development Kit 62 ARM RealView Tools by ARM

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ARM Support from Concept through Production
Arrow solves your ARM challenges through outstanding technical support, training, and seminars designed to address your specific ARM requirements. We’re here to help you navigate at every point in the design cycle.

Engineering Expertise—the Right Team for the Job
Arrow’s Field Applications Engineers (FAEs) provide expert support for all your design requirements, no matter where you are located. Our FAEs undergo monthly ARM training and constantly deliver the latest technical overviews of ARM technologies, so you can rest assured the information you receive is accurate, up-to-date, and relevant.

Arrow Technical Solutions Forum (ATSF): ARM Seminar Series for Cost-Sensitive Applications
This seminar series offered by Arrow addresses embedded customers’ demand for ARM technology and supports your emerging requirements. ARM offers some of the best solutions for balancing the needs for high performance, high integration, low power, and small die sizes (low cost). This ARM technology seminar series provides valuable solutions that get you to market faster. Visit www.arrownac.com/atsf for more information.

The Industry’s Only ARM Training Center
Arrow is the “go-to source” for ARM training. It’s the only approved ARM training center in North America and the only distributor for ARM tools. You can turn to us for relevant technical information conveyed by seasoned trainers because our team draws from the world’s largest and most experienced pool of ARM technology experts. Our field trainers provide multi-day classes that dive deep into ARM architectures and surrounding development tools. These classes can be conducted at any Arrow branch or customer location and give you access to quality technical training available only from Arrow and ARM. To register or for more information, go to www.arrownac.com/arm.

ARM Seminar Series for High-End Applications
ARM technology is widely used in high-performance applications that require the most from a processor yet need to maintain a low power profile. This seminar series is aimed at applications that utilize media, complex user interfaces, and computationalintensive applications on large data segments. The higher end of the industrial, medical, transportation, and other commercial markets is addressed, providing you with valuable, effective solutions. For more information, visit www.arrownac.com/atsf.

EmbeddedDeveloper.com
Finding the right ARM solution has never been easier. With EmbeddedDeveloper.com, you can search ARM devices by core type, peripheral sets, price, and many other specifications. Compare and contrast device functions, download specifications and datasheets, and even go to the Arrow shopping cart and buy the best development tool FIND. COMPARE. BUY. solution on-line.

For information on Arrow’s ARM training and seminars, visit www.arrownac.com/arm or call 1-866-910-3650. Arrow Electronics ARM Solutions
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Innovative Arrow Services
Access to comprehensive ARM offerings and leading suppliers is complemented by Arrow services that go far beyond getting you the components you need. Our engineering services, on-line development tool selection process, complimentary development tool evaluation program, supply chain solutions, and custom logic solutions ensure the success of your design from concept to production.

Arrow Consulting Engineering Services
The Arrow Consulting Engineering Services (ACES) program puts you in touch with pre-screened, qualified, and certified third-party solutions and design services companies so you can save time, effort, and resources. The superior core competencies of our partners allow them to provide complete outsourced designs—while allowing you to focus on your core competency.

Supply Chain Solutions
For decades, Arrow has successfully managed one of the most complex supply chains in the world, allowing us to offer unmatched insight and expertise. Our services, which include collaborative material planning tools, vendor managed inventory programs, performance analysis services, materials management programs, and electronic communication services, can support your needs throughout a product’s entire lifecycle—from the technical discovery stage to design and prototype development, and through production and product end of life.

Custom Logic Solutions Arrowdevtools.com
Find the best reference designs and evaluation tool solutions with arrowdevtools.com—an on-line development tool selection and purchasing process that gives you access to a vast range of development tools. This proprietary parametric search engine allows you to narrow your tool search quickly and intuitively to the unique tool you need to keep your development on track. Browse and compare different solutions and then conveniently and confidently purchase your tool for immediate delivery from arrowdevtools.com on-line or through Arrow’s sales team. Arrowdevtools.com offers everything you need to move your project rapidly to completion. Arrow’s Custom Logic Solutions group has partnered with industry leaders to meet your custom logic needs with the right combination of vendor technology, design services, and intellectual property. Solutions range from small FPGAs to structured ASICs, to highly complex standard cell ASICs. More than 130 local engineers and over 20 factory Custom Logic Solutions engineers, as well as integrated staff from Arrow’s network of design services partners, provide comprehensive design services that help you get to market quickly with the right product at the lowest possible risk and cost. Custom Logic Solutions also extends engineering support into the IP space, enabling you to piece together complex SOCs (Systems On A Chip) without having to be “experts at everything.”

TestdriveSM
Arrow’s Testdrive tool evaluation program helps you save time and money on your designs. The program allows you to try tools before you buy them, free of charge for 21 days. You can test a vast selection of tools from all the major semiconductor suppliers without impacting your budget. Additionally, Arrow’s Field Applications Engineers are familiar with the tools offered through Testdrive and can work through any issues that may arise, saving you precious resources and giving you access to some of the industry’s leading expertise.

Global Programming Services
More and more companies are relying on programmable devices to improve performance, simplify design, reduce chip count, and ease manufacturing. To help you keep up with constant advances in technology, Arrow has developed Global Programming Services to support procurement and the actual programming of your devices. Our services can give you greater levels of scheduling flexibility, reduce internal coordination and tracking, and avoid cost on capital equipment and staffing, to get you to market faster.

For information on Arrow’s Innovative Services, visit www.arrownac.com/arm or call 1-866-910-3650.

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ARM7TDMI and ARM7TDMI-S
ARM 32-Bit RISC Core with 16-Bit System Costs The ARM7TDMI core is the industry’s most widely used 32-bit embedded RISC microprocessor. The ARM7TDMI-S is a synthesizable version of the ARM7TDMI. Optimized for cost- and power-sensitive applications, the ARM7TDMI solution provides the low power consumption, small size, and high performance needed in portable, embedded applications. The ARM7TDMI core is a 32-bit embedded RISC processor delivered as a hard macrocell optimized to provide the best combination of performance, power, and area characteristics. The ARM7TDMI core enables system designers to build embedded devices requiring small size, low power, and high performance. The ARM7 family also includes the ARM7TDMI processor, the ARM7TDMI-S processor, the ARM720T processor, and the ARM7EJ-S processor, each of which has been developed to address different market requirements.

RISC Advantages
The ARM architecture is based on the Reduced Instruction Set Computer (RISC) principles. The RISC instruction set and related decode mechanism are much simpler than those of the Complex Instruction Set Computer (CISC) designs. This simplicity has the following advantages: • A high instruction throughput • An excellent real-time interrupt response • A small, cost-effective, processor macrocell
32-bit ALU High-performance multiplier ETM Interface

Control logic

EmbeddedICE-RT logic

Thumb decoder

The Instruction Pipeline
• The instruction pipeline • Memory access • Memory interface • EmbeddedICE

ARM7TDMI-S

Bus Interface Unit

Coprocessor Interface

The Instruction Pipeline
The ARM7TDMI core uses a pipeline to increase the speed of the flow of instructions to the processor. This allows several operations to take place simultaneously. A three-stage pipeline is used, so instructions are executed in three stages: • Fetch (the instruction is fetched from memory) • Decode (decoding of registers used in the instruction) • Execute (register/s read from register bank; shift and ALU operations; write register/s back to register bank)

Memory Access
The ARM7TDMI core has a Von Neumann architecture with a single 32-bit data bus carrying both instructions and data. Only load, store, and swap instructions can access data from memory. This simplifies the internal logic of the processor memory interface using less die area.

Memory Interface
During normal operation, while one instruction is being executed, its successor is being decoded and a third instruction is being fetched from memory. The ARM7TDMI processor memory interface has been designed to allow performance potential to be realized while minimizing the use of memory. Speed-critical control signals are pipelined to allow system control functions to be implemented in standard low-power logic. These control signals facilitate the exploitation of fast-burst access modes supported by many on-chip and off-chip memory technologies.

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EmbeddedICE-RT Logic
The EmbeddedICE-RT logic provides integrated on-chip debug support for the ARM7TDMI core. You use the EmbeddedICE-RT logic to program the conditions under which a breakpoint or watchpoint can occur. The EmbeddedICE-RT logic contains a Debug Communications Channel (DCC), which is used to pass information between the target and the host debugger. The EmbeddedICE-RT logic is controlled through the Joint Test Action Group (JTAG) test access port.

On execution, 16-bit Thumb instructions are transparently decompressed to full 32-bit ARM instructions in real time without performance loss.

Applications
• Industrial • Automotive • Personal audio (MP3, WMA, and AAC players)

Features Architecture
The ARM7TDMI processor has two instruction sets: • The 32-bit ARM instruction set • The 16-bit Thumb® instruction set Having both 32-bit ARM instructions and 16-bit Thumb instructions gives the ARM7TDMI processor two advantages: instruction compression and higher performance over typical 16-bit architectures. Microprocessor architectures traditionally have the same width for instructions and data. In comparison with 16-bit architectures, 32-bit architectures exhibit higher performance when manipulating 32-bit data and can access a large address space much more efficiently. Typically, 16-bit architectures have higher code density than 32-bit architectures, but they have approximately half the performance. The Thumb instructions implement a 16-bit instruction set on a 32-bit architecture to provide: • Higher performance than a 16-bit architecture • Higher code density than a 32-bit architecture The Thumb instruction set is a subset of the most commonly used 32-bit ARM instructions. Thumb instructions are each 16 bits long and have a corresponding 32-bit ARM instruction. This has the same effect on the processor model. Thumb instructions operate with the standard ARM register configuration, allowing excellent interoperability between ARM and Thumb states. Performance Characteristics
0.18 µm Speed Optimized 115 0.59 0.21 0.13 µm Speed Optimized 133 0.26 0.06 0.090 µm Speed Optimized 236 0.18 –

• 32-/16-bit RISC architecture (ARM v4T) • 32-bit ARM instruction set for maximum performance and flexibility • 16-bit Thumb instruction set for increased code density • Unified bus interface; 32-bit data bus carries both instructions and data • Three-stage pipeline • 32-bit ALU • Very small die size and low power consumption • Fully static operation • Coprocessor interface • Extensive debug facilities: – EmbeddedICE-RT real-time debug unit – JTAG interface unit – Interface for direct connection to Embedded Trace Macrocell (ETM)

Benefits
• Generic layout can be ported to specific process technologies • ARM and Thumb instruction sets can be mixed with minimal overhead to support application requirements for speed and code density • Small die size reduces overall SoC area, cost, and power consumption • EmbeddedICE-RT and optional ETM units enable extensive, real-time debug facilities

Frequency* (MHz) Area (mm2 ) Power** (mW/MHz)

*Worst-case conditions—0.18 µm process—1.62V, 125°C, slow silicon; 0.13 µm process—1.08V, 125°C, slow silicon; 90 nm process—0.9V, 125°C, slow silicon **Typical-case conditions—0.18 µm process—1.8V, 25°C, typical silicon; 0.13 µm process—1.2V, 25°C, typical silicon; 90 nm process—1V, 25°C, typical silicon

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ARM920T
High-Performance and Low-Power Platform OS The ARM9TDMI processor core is a Harvard architecture device implemented using a five-stage pipeline consisting of fetch, decode, execute, memory, and write stages. It can be provided as a standalone core that can be embedded into more complex devices. The standalone core has a simple bus interface that allows you to design your own caches and memory systems around it. The ARM920T processor is a member of the ARM9TDMI family of general-purpose microprocessors, which includes: • ARM9TDMI (core) • ARM940T (core plus cache and protection unit) • ARM920T (core plus cache and MMU)

ARM920T Application Support Features
The ARM9TDMI family of microprocessors supports both the 32-bit ARM and 16-bit Thumb® instruction sets, allowing you to trade off between high performance and high code density. The ARM920T processor is a Harvard cache architecture processor that is targeted at multi-programmer applications where full memory management, high performance, and low power are all-important. The separate instruction and data caches in this design are 16 KB each in size, with an eight-word line length. The ARM920T processor implements an enhanced ARM architecture v4 MMU to provide translation and access permission checks for instruction and data addresses. The ARM920T processor supports the ARM debug architecture and includes logic to assist in both hardware and software debug. The ARM920T processor also includes support for coprocessors, exporting the instruction and data buses along with simple handshaking signals. The ARM920T’s interface to the rest of the system is over unified address and data buses. This interface enables implementation of an Advanced Microcontroller Bus Architecture (AMBA), an Advanced System Bus (ASB), or an Advanced High-performance Bus (AHB) scheme either as a fully compliant AMBA bus master, or as a slave for production test. The ARM920T processor also has a Tracking ICE mode, which allows an approach similar to a conventional ICE mode of operation. The ARM920T processor supports the addition of an Embedded Trace Macrocell (ETM) for real-time tracing of instructions and data.
ETM Interface

16K Instruction cache MMU

ARM9TDMI core

16K Data cache MMU

ARM920T

Write buffer Control Logic and Bus Interface Unit

Coprocessor Interface

AMBA AHB Interface

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Applications
• Automotive infotainment • Industrial connectivity • Medical handheld • Platform OS-based devices • Next-generation smart phones, communicators, and PDA’s • 3G baseband and applications processor • Digital still camera • Audio and video decoding • Set-top box

• MMU which supports operating systems including Symbian OS, Windows CE, Linux, and Palm OS • Instruction and data caches: ARM920T = 16K/16K, ARM922T = 8K/8K • Industry-standard AMBA bus interface • ETM interface for real-time trace capability with ETM9

Benefits
• Runs all major OS’s and existing middleware • Single development toolkit for reduced development costs and shorter development cycle time • Multiple sourcing from industry-leading silicon vendors • Code-compatible upward migration path to ARM10E family • Excellent debug support for SoC designers • Instruction set can be extended by the use of coprocessors

Features
• 32-/16-bit RISC architecture (ARMv4T) • 32-bit ARM instruction set for maximum performance and flexibility • 16-bit Thumb instruction set for increased code density

Performance Characteristics
0.18 µ M Speed Optimized 190-200 11.80 16K/16K 0.80 0.13 µM Speed Optimized 230-250 4.70 16K/16K 0.25

Frequency* (MHz) Area with cache (mm2) Cache size Power with cache** (mW/MHz)

*Worst-case conditions—0.18 µm process—1.62V, 125˚C, slow silicon; 0.13 µm process—1.08V, 125˚C, slow silicon **Typical-case conditions—0.18 µm process–1.8V, 25˚C, typical silicon; 0.13 µm process—1.2V, 25˚C, typical silicon

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ARM926EJ-S
ARM926EJ-S Jazelle-Enhanced Macrocell Processor The ARM926EJ-S™ fully synthesizable processor features a Jazelle-enhanced 32-bit RISC CPU, flexible size instruction and data caches, Tightly Coupled Memory (TCM) interfaces, and a Memory Management Unit (MMU). It also provides separate instruction and data AMBA AHBTM interfaces particularly suitable for multi-layer AHB-based systems. The ARM926EJ-S processor implements the ARMv5TEJ instruction set and includes an enhanced 16 x 32-bit multiplier, capable of single-cycle MAC operations. The instruction set includes 16-bit fixed-point DSP instructions to enhance performance of many signal processing algorithms and applications as well as supports Thumb® and Java bytecode execution.

The ARM926EJ-S processor is a member of the ARM9 family of general-purpose microprocessors. The processor is targeted at multi-tasking applications where full memory management, high performance, small die size, and low power are all important. The processor supports the 32-bit ARM and 16-bit Thumb instruction sets, enabling the user to trade off between high performance and high code density. The ARM926EJ-S processor includes features for efficient execution of Java byte codes, providing Java performance similar to JIT, but without the associated code overhead. The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both hardware and software debug. The processor has a Harvard cached architecture and provides a complete high-performance processor subsystem, including: • An ARM9EJ-S integer core • An MMU • Separate instruction and data AMBA AHB bus interfaces • Separate instruction and data TCM interfaces The ARM926EJ-S processor provides support for external coprocessors, enabling the addition of other floating-point or other application-specific hardware acceleration. The processor implements ARM architecture version 5TEJ. The ARM926EJ-S processor is a synthesizable macrocell. This means that you can optimize the macrocell for a particular target library, and you can configure the memory system to suit your target application. You can individually configure the cache sizes to be any power of two between 4 KB and 128 KB.
Instruction TCM interface Instruction cache MMU

ETM9 Interface Data TCM interface Data cache MMU

ARM9EJ-S core

ARM926EJ-S

Write buffer Control Logic and Bus Interface Unit

Coprocessor Interface

AMBA AHB interface
Instruction Data

The tightly coupled instruction and data memories are instantiated externally to the ARM926EJ-S macrocell, providing you with the flexibility to optimize the memory subsystem for performance, power, and particular RAM type. The TCM interfaces enable non-zero wait-state memory to be attached, as well as provide a mechanism for supporting DMA.

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Applications
• Automotive infotainment • Audio and video decoding • Platform OS-based devices • Next-generation smart phones, communicators, and PDAs • 3G baseband and applications processor • Digital still camera

Benefits
• Runs all major OS’s and existing middleware • Single-chip MCU, DSP, and Java solution • Support for leading Java run-times • High-efficiency Java bytecode execution • Ultra-low Java power consumption • Java JIT compiler performance without the disadvantages • Jazelle support code has no increase in VM size

Features
• 32/16-bit RISC architecture (ARMv5TEJ) • 32-bit ARM instruction set for maximum performance and flexibility • 16-bit Thumb instruction set for increased code density • DSP instruction extensions and single-cycle MAC • ARM Jazelle technology • MMU which supports operating systems including Symbian OS, Windows CE, and Linux • Flexible instruction and data cache sizes • Instruction and data TCM interfaces with wait-state support • EmbeddedICE-RT logic for real-time debug • Industry-standard AMBA bus AHB interfaces • ETM interface for real-time trace capability with ETM9 • Optional MOVE coprocessor delivers video encoding performance

• Simple single-processor software structure, no need for software partitioning across MCUs • Single development toolkit for reduced development costs and shorter development cycle time • Multiple sourcing from industry-leading silicon vendors • Code-compatible upward migration path through to the latest cortex family of processors • Process portable synthesizable design • Excellent debug support for SoC designers • Instruction set can be extended by the use of coprocessors • ARM-EDA Reference Methodology deliverables significantly reduce the time to generate a specific technology implementation of the core and to generate industry-standard views and models

Performance Characteristics
0.18 µ M Speed Optimized SAGE-X HSHD 200 6.5 3 8K/8K – – 0.13 µ M Speed Optimized SAGE-HS HSHD 276 2.78 1.61 8K/8K – – Area Optimized SAGE-X HSHD 238 2.39 1.45 8K/8K 0.48 0.36 Speed Optimized Advantage-HS Advantage 500 1.55 1.05 8K/8K 0.29 0.24 90 nm Area Optimized Metro Metro 250 0.85 0.50 8K/8K 0.14 0.11

Standard cells Memories Frequency* (MHz) Area with cache (mm2 ) Area without cache (mm2 ) Cache size Power with cache** (mW/MHz) Power without cache** (mW/MHz)

*Worst-case conditions—0.18 µm process—1.62V, 125˚C, slow silicon; 0.13 µm process—1.08V, 125˚C, slow silicon; 90 nm process—0.9V, 125˚C, slow silicon **Typical-case conditions—0.18 µm process—1.8V, 25˚C, typical silicon; 0.13 µm process—1.2V, 25˚C, typical silicon; 90 nm process—1V, 25˚C, typical silicon

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ARM966E-S
Embedded Core with Flexible Memory System and DSP Instruction Set Extensions The ARM966E-S processor is targeted at a wide range of embedded applications where high performance, low system cost, small die size, and low power are all important. The ARM966E-S macrocell is a fully synthesizable 32-bit RISC processor aimed specifically at embedded hard real-time applications. The core implements the ARMv5TE instruction set and features an enhanced 16 x 32-bit multiplier capable of single-cycle MAC operations, and 16-bit fixed point DSP instructions to accelerate signal processing algorithms and applications.

The ARM966E-S processor has separate, directly connected instruction and data Tightly Coupled Memory (TCM), which have flexible sizes and run at the processor clock speed. The ARM966E-S processor supports ARM’s real-time trace technology with the optional ETM9 Embedded Trace Macrocell. The ARM966E-S features a simple memory map providing an area and power-efficient solution for applications that do not require complex memory management support. The core includes an AMBA AHB™ interface and a coprocessor interface for connection to application acceleration hardware such as the VFP9-S floating-point coprocessor. The ARM966E-S processor provides a high-performance processor subsystem that includes the ARM9E-S RISC integer CPU core featuring: • ARMv5TE 32-bit instruction set with improved ARM/Thumb code inter-working and enhanced multiplier designed for improved DSP performance • ARM debug architecture with additional support for real-time debug; this enables critical exception handlers to execute while debugging the system • Support for external TCM; a TCM interface is provided for each of the external instruction and data memory blocks; the TCM interfaces of the ARM966E-S processor enable high-speed operation without incurring the performance and power penalties of accessing the system bus, while having a lower area overhead than a cached memory system; the size of both the Instruction and Data TCM blocks are implementor-specific to enable tailoring of the hardware to the embedded application • A simple fixed memory map for the local TCM, ideal for real-time embedded control applications

ETM Interface

Instruction TCM interface

ARM9E core

Data TCM interface

ARM966E-S

Write buffer Control Logic and Bus Interface Unit

Coprocessor Interface

AMBA AHB interface

• An AMBA AHB bus interface • Support for external coprocessors enabling floatingpoint or other application-specific hardware acceleration to be added • Support for the use of a scan test methodology for the standard-cell logic and Built-In-Self-Test (BIST) for the TCM

Providing this complete high-frequency subsystem frees the SoC designer to concentrate on design issues unique to their system; the synthesizable nature of the device eases integration into ASIC technologies.

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Applications
• Automotive control: Powertrain with VFP9-S coprocessor • Industrial control • Mass storage devices: hard disc drives and DVD drives • Networking systems • Wireless devices • Digital still cameras

Benefits
• Single-chip MCU and DSP solution • Deterministic performance from TCM memories • Simple single-processor software structure; no need for software partitioning across MCUs and eliminates multi-MCU debugging • Single development toolkit: reduced development costs and shorter development cycle time • Optimized for hard real-time applications

Features
• 32-/16-bit RISC architecture (ARMv5TE) • 32-bit ARM instruction set for maximum performance and flexibility • 16-bit Thumb instruction set for increased code density • Tightly Coupled Memories (TCMs) • EmbeddedICE-RT logic for real-time debug • Floating point capability with VFP9-S coprocessor • ETM interface for real-time trace capability with ETM9 • ARM-Synopsys Reference Methodology compliant deliverables • Optional MOVE coprocessor delivers video encoding performance

• Multiple sourcing from industry-leading silicon vendors • Code-compatible upward migration path to ARM10E family • Excellent debug support for SoC designers • Instruction set can be extended by the use of coprocessors • ARM-EDA Reference Methodology deliverables significantly reduce the time to generate a specific technology implementation of the core and to generate industry-standard views and models

Core area, frequency range, and power consumption are dependent on process, libraries, and optimizations. The numbers quoted above are illustrative of synthesized cores using general-purpose TSMC process technologies and ARM Artisan standard-cell libraries and RAMs. The speed-optimized implementations refer to the library choices and synthesis flow decisions and tradeoffs made in order to achieve the target frequency performance. The area-optimized implementations refer to the library choices and synthesis flow decisions and tradeoffs made in order to achieve a target area density.

Performance Characteristics
0.18 µ M Speed Optimized NA 200 2 0.70 0.13 µM Speed Optimized NA 250 1 0.25 90 nm Speed Optimized Advantage-HS 500 0.70 0.15 Area Optimized Metro 250 0.35 0.07

Standard cells Frequency* (MHz) Area (mm2) Power** (mW/MHz)

*Worst-case conditions—0.18 µm process—1.62V, 125˚C, slow silicon; 0.13 µm process—1.08V, 125˚C, slow silicon; 90 nm process—0.9V, 125˚C, slow silicon **Typical-case conditions—0.18 µm process—1.8V, 25˚C, typical silicon; 0.13 µm process—1.2V, 25˚C, typical silicon; 90 nm process—1V, 25˚C, typical silicon

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ARM1136J(F)-S
A High-Performance, Low-Power Processor with DSP and Media Extensions The award-winning ARM1136J-S™ and ARM1136JF-S™ processors deliver up to 660 Dhrystone 2.1 MIPS in a 0.13 µm process. Both processors feature the ARM v6 instruction set with media extensions, ARM Jazelle® technology for efficient embedded Java execution, ARM Thumb® code compression, and an optional floating-point coprocessor. Media processing extensions offer up to 1.9x the acceleration of media-processing tasks such as MPEG4 encode. Instruction and data cache sizes are configurable, and optional Tightly Coupled Memories (TCMs) can be added to accelerate interrupt handling and data processing. These processors feature AMBA® 2.0 AHB™ interfaces compatible with a wide range of system IP and peripherals. The ARM1136JF-S processor also features an integrated floating-point coprocessor, which makes it particularly suitable for embedded 3D-graphics applications.

The ARM1136JF-S processor incorporates an integer unit that implements the ARM architecture v6. It supports the ARM and Thumb instruction sets, Jazelle technology to enable direct execution of Java bytecodes, and a range of SIMD DSP instructions that operate on 16-bit or 8-bit data values in 32-bit registers. The ARM1136JF-S processor is a high-performance, low-power, ARM cached processor macrocell that provides full virtual memory capabilities.

Debug Interface

VFP

Coprocessor Controller

Instruction Cache TCRAM

ARM1136J-S core

Data Cache TCRAM

• An integer unit with integral EmbeddedICE-RT logic • An eight-stage pipeline • Branch prediction with return stack • Low-interrupt latency • External coprocessor interface and coprocessors 14 and 15 • Instruction and Data Memory Management Units (MMUs), managed using MicroTLB structures backed by a unified Main TLB • Instruction and data caches, including a non-blocking data cache with Hit-Under-Miss (HUM) • The caches are virtually indexed and physically addressed, and have a 64-bit interface to both caches • Level-one TCM that can be used as a local RAM with DMA, or as SmartCache • High-speed Advanced Microprocessor Bus Architecture (AMBA) level two • Vector Floating-Point (VFP) coprocessor support In addition to the ARM1136J-S, ARM introduced a version that includes a VFP coprocessor. This is designated as the ARM1136JF-S.

ARM A R M 1 1 3 6 J (F)- S F-S

Features

Memory Management

Instruction Interface

Data Interface

DMA

Peripheral Port

Core
The ARM1136JF-S processor is built around the ARM11 core in an ARMv6 implementation that runs the 32-bit ARM, 16-bit Thumb, and 8-bit Jazelle instruction sets. The processor contains EmbeddedICE-RT logic and a JTAG debug interface to enable hardware debuggers to communicate with the processor.

Registers
The ARM1136JF-S core contains: • 31 general-purpose 32-bit registers • Seven dedicated 32-bit registers

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Thumb Instruction Set
Thumb is an extension to the ARM architecture. It contains a subset of the most commonly used 32-bit ARM instructions that has been encoded into 16-bit wide opcodes, to reduce memory requirements.

Memory System
The core provides a level-one memory system with the following features: • Separate instruction and data caches • Separate instruction and data RAMs

DSP Instructions
The ARM DSP instruction set extensions provide the following: • 16-bit data operations • Saturating arithmetic • MAC operations Multiply instructions are processed using a single-cycle 32x16 implementation. There are 32x32, 32x16, and 16x16 multiply instructions (MAC). • 64-bit datapaths throughout the memory system • Complete memory management • 32-bit dedicated peripheral interface

Applications
• Automotive infotainment: in-car entertainment, DVD players, and navigation equipment • Networking: control processors in network infrastructure, switch, and router products • Consumer: digital TVs, set-top boxes, game consoles, and handheld digital media players

Media Extensions
The ARMv6 instruction set provides media instructions to complement the DSP instructions. The media instructions are divided into the following main groups: • Additional multiplication instructions for handling 16-bit and 32-bit data, including dual-multiplication instructions that operate on both 16-bit halves of the source registers; this group includes an instruction that improves the performance and size of code for multi-word unsigned multiplications • Instructions to perform Single Instruction Multiple Data (SIMD) operations on pairs of 16-bit values held in a single register, or on quadruplets of 8-bit values held in a single register; the main operations supplied are addition and subtraction, selection, pack, and saturation

Core area, frequency range, and power consumption are dependent on process, libraries, and optimizations. The numbers quoted above are illustrative of synthesized cores using general-purpose TSMC process technologies and ARM Artisan standard-cell libraries and RAMs. The speed-optimized implementations refer to the library choices and synthesis flow decisions and tradeoffs made in order to achieve the target frequency performance. The area-optimized implementations refer to the library choices and synthesis flow decisions and tradeoffs made in order to achieve a target area density. The cache sizes are specified as InstructionCache/DataCache. The area without cache numbers quoted exclude RAM area, but include all logic including memory management, cache control, and debug. The area with cache numbers quoted includes the core, the specified instruction and data caches, and all necessary RAMs.

Performance Characteristics
90 nm Standard cells Memories Frequency* (MHz) Area with cache (mm2 ) Area without cache (mm2 ) Cache size Power** with cache (mW/MHz) Power** without cache (mW/MHz) Speed Optimized Advantage-HS Advantage 620 2.50 1.80 16K/16K 0.45 0.37 Area Optimized Metro Metro 320 1.55 0.90 16K/16K 0.24 0.18

*Worst-case conditions—0.18 µm process—1.62V, 125˚C, slow silicon; 0.13 µm process—1.08V, 125˚C, slow silicon; 90 nm process—0.9V, 125˚C, slow silicon **Typical-case conditions—0.18 µm process—1.8V, 25˚C, typical silicon; 0.13 µm process—1.2V, 25˚C, typical silicon; 90 nm process—1V, 25˚C, typical silicon

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ARM Cortex-A8
Processors for Complex OS and User Applications The ARM Cortex™-A8 processor is the first applications processor based on the ARMv7 architecture and is the highest performance, most power-efficient processor ever developed by ARM. With the ability to scale in speed from 600 MHz to greater than 1 GHz, the ARM Cortex-A8 processor can meet the requirements for power-optimized mobile devices needing operation in less than 300 mW and performance-optimized consumer applications requiring 2000 Dhrystone MIPS. The ARM Cortex-A8 processor is ARM’s first superscalar processor featuring technology for enhanced code density and performance, NEON™ technology for multimedia and signal processing, and Jazelle® RCT (Runtime Compilation Target) technology for efficient support of ahead-of-time and just-in-time compilation of Java and other bytecode languages.

The exceptional speed and power efficiency of the Cortex-A8 processor is enabled by new ARM Artisan® Advantage-CE libraries supporting and implementing advanced leakage control.

DFT/Test

Debug

ETM

The processor is supported by a wide range of ARM technologies for rapid system design including: • The RealView® DEVELOP family of software development tools • The RealView CREATE family of ESL tools and models • CoreSight™ debug and trace technology as well as software library support through the OpenMAX multimedia processing standard • AMBA® 3 AXI high-performance SoC interconnect

IFetch

IDecode

IExecute

Load store

I-side L1 RAM

L1 cache interface

Prefetch and branch prediction

Decode & sequencer

Dependency check and issue

Flags RegBank

ALU1 ALU2 MAC Load store L1 cache interface D-side L1 RAM

TLB

TLB

Level 2 cache

Instruction and Data DMA arbitration

NEON unit
NEON instruction queue Decode control Issue and forward control NEON load data queue

The ARM Cortex-A8 processor’s sophisticated pipeline architecture is based on dual, symmetric, in-order issue, 13-stage pipeline with advanced dynamic branch prediction achieving 2.0 DMIPS/MHz. • The in-order, dual-issue, superscalar microprocessor core includes: – 13-stage main integer pipeline – 10-stage NEON media pipeline – Dedicated Level 2 (L2) cache with programmable wait states – Global-history-based branch prediction • The processor works in conjunction with a power-optimized load store pipeline to deliver 2.0 DMIPS/MHz for power-sensitive applications

CORTEX -A8

Architectural Features

L2 cache and preload engine

Fill and eviction queue L2 cache data RAM BIU Write buffer L2 cache tag RAM

NEON Floating Point NEON RegBank VFPLite

NEON Load Store

NEON Integer

AXI

• The ARM Cortex-A8 is ARMv7 architecture-compliant and includes: – Thumb®-2 technology for greater performance, energy efficiency, and code density – NEON signal processing extensions to accelerate media codecs such as H.264 and MP3 – Jazelle RCT Java-acceleration technology to optimize Just In Time (JIT) and Dynamic Adaptive Compilation (DAC), and to reduce memory footprint by up to three times – TrustZone technology for secure transactions and Digital Rights Management (DRM)

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• Integrated L2 Cache: – Built using standard compiled RAMs – Configurable size from 64K-2 MB – Programmable delay • Optimized Level 1 (L1) Cache: – Performance- and power-optimized – Combines minimal access latency with hash way determination to maximize performance and minimize power consumption • Dynamic Branch Prediction: – Enabled by branch target and global-history buffers – Achieves 95% accuracy across industry benchmarks – Replay mechanism minimizes miss-predict penalty

• Memory System: – Single-cycle load-use penalty for access to the L1 cache – Hash array in the L1 cache limits activation of the memories to when they are likely to be needed – Direct interface between the integrated, configurable L2 cache and the NEON media unit for data streaming – Banked L2 cache design that enables only one bank at a time – Support for multiple outstanding transactions to the Level 3 (L3) memory to fully utilize the CPU

Performance Characteristics
65 nm Speed Optimized 600-800 <4 <3 < 0.5

Frequency* (MHz) Area with cache (mm2) Area without cache (mm2) Power with cache** (mW/MHz)

*Core area, frequency range, and power consumption are dependent on process, libraries, and optimizations. The numbers quoted above are illustrative of synthesized cores using general-purpose TSMC process technologies and ARM Artisan standard-cell libraries and RAMs. Area is for core only (excluding NEON, Trace technology, and L2 cache). Frequency and power are for mobile applications. Frequency for consumer applications = 1 GHz. The speed-optimized implementations refer to the library choices and synthesis flow decisions and tradeoffs made in order to achieve the target frequency performance. The area-optimized implementations refer to the library choices and synthesis flow decisions and tradeoffs made in order to achieve a target area density. **The 65 nm (LP) dynamic power measured is at 1.2V nominal and, hence, is higher than the 65 nm (GP) dynamic power, which is at 1.0V. However, the 65 nm (LP) leakage is significantly lower and this is the major consideration for mobile or battery-operated devices that need to conserve power in standby mode.

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ARM Cortex-M3
Processors Optimized for Cost-Sensitive and Deeply-Embedded Applications The ARM CortexTM-M3 processor has been developed to provide a high-performance, low-cost platform that meets the needs of minimal memory implementation, reduced pin count, and low power consumption, while delivering outstanding computational performance and exceptional system response to interrupts. The ARM Cortex-M3 32-bit RISC processor executes purely Thumb®-2 instructions, delivering the high performance expected of an ARM core in the memory size usually associated with 8- and 16-bit devices; typically in the range of a few kilobytes of memory for microcontroller class applications.

In addition to minimizing its memory requirement, the ARM Cortex-M3 processor is also the smallest 32-bit core designed by ARM at just 33k gates for the central processing core (CM3Core) and 60k gates total, including many close system peripherals. This design reduces silicon area requirements even further, enabling the smallest of packages or the manufacturing of devices on low-cost processes, such as 0.35 µM and 0.25 µM.

Configurable NVIC

ETM

ARM core
Memory protection unit

DAP

Serial wire viewer

Cortex-M3

The ARM Cortex-M3 processor also reduces the number of pins required for debug from five to one, by implementing a new debug interface technology—Single Wire Debug—that can replace the current multi-pin JTAG port.

Data watchpoints

Flash patch

Bus Matrix Code interface SRAM & peripheral I/F

Outstanding Performance
In addition to unparalleled performance, power consumption, and memory utilization, the ARM Cortex-M3 processor also achieves exceptional interrupt handling. By implementing the register manipulations required for handling an interrupt in hardware, this core achieves minimal clock overhead on entering interrupts, and switches between pending or higher priority interrupts in only six cycles. The design, which comes with 32 interrupt channels as standard, can be configured to between 1 and over 240 channels.

Enabling Technology
The ARM Cortex-M3 processor has been designed “from the ground up” to provide optimal performance and power consumption within a minimal memory system. To achieve this, the core executes only the Thumb-2 instruction set, which delivers an unparalleled combination of ARM instruction set performance with industry-leading code density. The design, which is based on a three-stage pipeline Harvard architecture, also maximizes memory utilization through the support of unaligned date storage, and single-cycle atomic bit manipulation.

The ARM Cortex-M3 processor also includes an optional Memory Protection Unit (MPU) to provide a privileged mode of operation for complex applications.

The exceptional performance of the ARM Cortex-M3 processor is achieved through a highly revised architecture that also implements many new technologies in this type of core, such as hardware divide and single-cycle multiply.

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Benefits
The ARM Cortex-M3 processor offers significant benefits to system and software developers. • Lower cost devices through smaller processing core, system, and memories • Ultra-low power consumption and integrated sleep modes • Outstanding processing performance for challenging applications • Fast interrupt handling for critical control applications • Platform security with optional integrated memory protection unit • Enhanced system debug for faster development • No assembler code requirement to ease system development • Wide application envelope encompassing ultra-lowcost microcontrollers and high-performance SoC

Core area, frequency range, and power consumption are dependent on process, libraries, and optimizations. The numbers quoted above are illustrative of synthesized cores using general-purpose TSMC process technologies and ARM Artisan® standard-cell libraries and RAMs. Area numbers include the CM3Core, the Nested Vectored Interrupt Controller (NVIC), and Bus Matrix, but not the optional components including the Memory Protection Unit, Embedded Trace Macrocell, Breakpoint Unit, Data Watchpoint Unit, and Trace Port Interface Unit.

The speed-optimized implementations refer to the library choices and synthesis flow decisions and tradeoffs made in order to achieve the target frequency performance. The area-optimized implementations refer to the library choices and synthesis flow decisions and tradeoffs made in order to achieve a target area density.

Performance Characteristics
0.18 µ M Standard cells Frequency* (MHz) Area (mm2 ) Power** (mW/MHz) Speed Optimized SAGE-X 100 0.86 0.19 Area Optimized Metro 50 0.70 0.14 Speed Optimized SAGE-X 135 0.39 0.12 0.13 µ M Area Optimized Metro 50 0.30 0.09

*Worst-case conditions—0.18 µm process—1.62V, 125˚C, slow silicon; 0.13 µm process—1.08V, 125˚C, slow silicon **Typical-case conditions—0.18 µm process—1.8V, 25˚C, typical silicon; 0.13 µm process—1.2V, 25˚C, typical silicon

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ARM Cortex-R4(F)
Embedded Processors for Real-Time Applications The ARM Cortex™-R4 processor is the first deeply embedded processor to be based on the ARMv7 architecture and is targeted at very high-volume, deeply embedded applications such as hard-disk drives, inkjet printers, and automotive safety systems. The ARM Cortex-R4 processor provides key savings in cost and power consumption for system developers, offering substantially higher performance than any other processor with similar die size. Along with the ARM1156T2-S and ARM Cortex-M3 processors, the ARM Cortex-R4 processor completes comprehensive coverage for the diverse needs of the embedded microprocessor market. Furthermore, the ARM Cortex-R4 processor supports substantial synthesis time configurability that enables designers to match the processor precisely to the application requirements.

C o r t e x - R 4 (F) F

In addition to the ARM Cortex-R4, ARM has introduced the ARM Cortex-R4F, which contains a Floating Point Unit (FPU). The ARM Cortex-R4F processor’s FPU performs floating-point calculations that allow a greater dynamic range and accuracy than fixed-point calculations. The FPU is backward compatible with earlier ARM FPUs (VFP9/10/11), and is optimized for the single-precision processing most commonly used in automotive and control applications. The FPU is particularly useful in sophisticated control applications, where algorithms are often modeled in an environment such as Simulink or ASCET-SD, and code is auto-generated using tools such as Real Time Workshop Embedded Coder, ASCET-SE, or dSPACE Targetlink.

Debug Interface

VIC Port

ETM Interface

Prefetch & Branch Prediction Unit

core
FPU

TCM Arbiter and Interface

The ARM Cortex-R4 processor is capable of running at clock speeds of up to 400 MHz on typical 90 nm processes, and the focus throughout the design is on efficiency and configurability.

Instruction Cache

Memory Protection Unit FP exec 1 Data Cache

AXI Master Interface

AXI Slave Interface

Technical Innovations
• Thumb®-2 technology; an innovation that has enabled partners to combine the minimal memory footprint of 16-bit Thumb code with the high performance of 32-bit ARM code • AMBA 3 AXI protocol; a set of major enhancements to AMBA for high-performance on-chip interconnect, the ARM Cortex-R4 processor integrates a 64-bit master port as well as a 64-bit DMA port for direct access to the Tightly Coupled Memories (TCM) • A selective superscalar eight-stage pipeline that provides more than 1.6 DMIPS/MHz in an efficient low gate count implementation • Non-Maskable Interrupts (NMI); many real-time applications demand this and the ARM Cortex-R4 supports a configurable NMI pin

• CoreSight™ technology; a framework for complete system debug and trace; this includes the ETM-R4 embedded trace macrocell and many other CoreSight components • A significantly improved local memory architecture for TCM and DMA; TCM can now be unified into a single logical address space and can run as fast as cache memory • Enhancements over the ARMv6 architecture include improvements in interrupt handling and the memory protection scheme; new instructions for managing interrupts reduce the critical early-interrupt handler code, and the worst-case interrupt latency is vastly improved to only 20 clock cycles • Performance monitoring support; very useful for refining and tuning a system through advanced profiling of the system performance

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• Architected support for parity in the caches and parity or ECC in the TCMs; soft errors are an increasing concern in embedded systems and either parity or ECC is now essential in many systems • A very efficient branch prediction and prefetch unit provide a branch accuracy of more than 90% for typical C code • The overall aim of the ARM Cortex-R4 processor is to provide around 40% more efficiency than the ARM9 family whilst increasing the maximum clock speed, supporting the use of low-power, dense RAMs for cache and TCMs, and delivering an efficient Thumb-2 engine

• Either one, two, or three TCM ports can be included • A number of breakpoints and watchpoints can be selected • Dynamic Branch Prediction - Enabled by branch target, global-history buffers, and a function called return stack - Achieves 90% accuracy across industry benchmarks • Single-cycle load-use penalty for access to the L1 cache and TCM • A single 64-bit AXI master port for easy integration into the SoC interconnect • An AXI slave port to allow direct access to TCMs by DMA controllers and other processors in the system

Architectural Features
The ARM Cortex-R4 processor’s sophisticated pipeline architecture is based on low-cost dual-issue pipeline, eight stages with advanced dynamic branch prediction achieving 1.6 DMIPS/MHz; the ARM Cortex-R4 processor is fully ARMv7 architecture-compliant and includes: • Thumb-2 technology for greater performance, energy efficiency, and code density • Hardware divide instructions for control applications • Optimized level-one caches and TCM • Synthesis optional cache controllers (with optional cache parity) and TCM ports for flexibility • Full wait and error support on TCM interfaces • Flexible configuration at synthesis time of major level-one features • A Memory Protection Unit (MPU) can be removed or an eight- or 12-region one selected • Vectored Interrupt Controller (VIC) port for fast connection to interrupt management peripherals Core area, frequency range, and power consumption are dependent on process, libraries, and optimizations. The numbers quoted above are illustrative of synthesized cores using general-purpose TSMC process technologies and ARM Artisan standard cell libraries and RAMs. The speed-optimized implementations refer to the library choices and synthesis flow decisions and tradeoffs made in order to achieve the target frequency performance. The area-optimized implementations refer to the library choices and synthesis flow decisions and tradeoffs made in order to achieve a target area density. The cache sizes are specified as InstructionCache/DataCache. The area without cache numbers quoted exclude RAM area, but include all logic including memory management, cache control, and debug. The area with cache numbers quoted includes the core, the specified instruction and data caches and all necessary RAMs.

Performance Characteristics
0.13 µ M Area Optimized SAGE-HS HS 300 3.35 1.99 16K/16K – – 90 nm Speed Optimized Advantage-HS Advantage 500 2.50 1.66 16K/16K 0.41 0.33 Area Optimized Metro Metro 210 1.50 0.80 16K/16K 0.22 0.16

Standard cells Memories Frequency* (MHz) Area with cache (mm2) Area without cache (mm2 ) Cache size Power** with cache (mW/MHz) Power** without cache (mW/MHz)

*Worst-case conditions—0.18 µm process—1.62V, 125˚C, slow silicon; 0.13 µm process—1.08V, 125˚C, slow silicon; 90 nm process—0.9V, 125˚C, slow silicon **Typical-case conditions—0.18 µm process—1.8V, 25˚C, typical silicon; 0.13 µm process—1.2V, 25˚C, typical silicon; 90 nm process—1V, 25˚C, typical silicon

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Intel XScale®
Designed to Enable High Performance, Low Power Consumption, and Systems Integration The Intel XScale® core is based on an ARM processor family second-generation core and consists of innovative custom circuits, a proprietary design, and proprietary process techniques. This unique core enables processors in the Intel XScale® family to operate on very low current while in run and low-power modes. Designed to enable high performance, low power consumption, and systems integration, the Intel XScale® core empowers OEMs to develop smaller, more cost-effective, handheld devices with longer battery life, while providing the performance to run MIPS-intensive multimedia applications such as audio encode/decode, video compression, and speech. The Intel XScale® microarchitecture extends to set-top boxes, networking, intelligent I/O, and remote-access servers. This unique processor engine design affords a substantial leadership position in the handheld device market segment where high performance, low power, and integration-per-cost-effectiveness are all critical factors.

The Intel XScale® core targets the portable information device segment, which consists of feature-rich handheld devices such as (but not limited to) the following: • Vertical application devices • Palm-size devices • Smart phones/3G+ multimedia phones • PC companions The processor is also packaged in a “smaller footprint, lower cost” version focused on handheld and portable applications, and a “higher performance” version for the PC companion and vertical application device segments. In addition to handheld segments, the Intel XScale® core also provides a market entry to tethered applications such as screen phones, low-end set-top boxes, web terminals, and other Internet appliances.

• Power management unit saves power with idle, sleep, and quick wake-up modes • 128-entry branch target buffer maintains pipeline capacity with statistically correct branch choices • 32 KB instruction cache achieves high performance and low power consumption levels by keeping a local copy of important instructions • 2 KB data cache avoids “thrashing” of the data cache for frequently changing data streams • 32-entry instruction memory management unit enables logical-to-physical address translation, access permissions, and instruction-cache attributes • Four entry fill and pend buffers obtain core efficiency by allowing non-blocking and “hit-under-miss” operation with data caches • Performance monitoring unit analyzes hit rates with two 32-bit event counters and one 32-bit cycle counter • Debug unit debugs programs with hardware breakpoints and a 256-entry trace-history buffer (for flow change messages) • 32-bit coprocessor interface achieves a high-performance interface between the core and coprocessors • 64-bit core memory bus with simultaneous 32-bit input path and 32-bit output path obtains up to 4.8 GBytes/sec @ 600 MHz bandwidth for internal accesses • Eight-entry write buffer provides continuous core execution while data is written to memory • The Thumb instruction set supported selects the 16-bit Thumb instruction set from the current program status register

Features and Benefits of Intel XScale Microarchitecture

®

• Superpipelined RISC technology achieves high speed and ultra-low power with a seven-stage integer/eightstage memory superpipelined core • Dynamic voltage management obtains the right blend of performance and power with dynamic voltage and frequency scaling “on the fly” • Media processing technology achieves efficient media processing with a multiply-accumulate coprocessor that performs two simultaneous 16-bit SIMD multiplies with 40-bit accumulation

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ARM Architecture Compatibility
The Intel XScale® microarchitecture implements the integer instruction set architecture specified in ARM Version 5TE. “T” refers to the Thumb instruction set, and “E” refers to the DSP-enhanced instruction set. ARM Version 5 introduces a few more architecture features over Version 4, specifically the addition of tiny pages (1 Kbyte), a new instruction (CLZ) that counts the leading zeroes in a data value, enhanced ARM-Thumb transfer instructions, and a modification of the system-control coprocessor, CP15.

• Additional functionality has been added to coprocessor 15; coprocessor 14 also added • Enhancements were made to the event architecture, instruction cache, and data-cache parity

DSP Coprocessor 0 (CP0)
The Intel XScale® microarchitecture adds a DSP coprocessor to the architecture for increasing the performance and the precision of audio-processing algorithms. This coprocessor contains a 40-bit accumulator and eight new instructions. The 40-bit accumulator is referenced by several new instructions that were added to the architecture; MIA, MIAPH, and MIAxy are multiply/accumulate instructions that reference the 40-bit accumulator instead of a register-specified accumulator. MAR and MRA read and write the 40-bit accumulator. Access to CP0 is always allowed in all processor modes when bit 0 of the coprocessor access register is set. Any access to CP0 when this bit is clear will cause an undefined exception. Note that only privileged software can set this bit in the coprocessor access register. Two new instruction formats were added for coprocessor 0: multiply with internal accumulate format, and internal accumulate access format.

ARM DSP-Enhanced Instruction Set
The Intel XScale® microarchitecture implements the ARM DSP-enhanced instruction set, which is a set of instructions that boosts the performance of signal-processing applications. New multiply instructions operate on 16-bit data values, and new saturation instructions are available as well (see below). • SMLAxy instruction is a 16x16+32 with a 32-bit result • SMLAWy instruction is a 32x16+32 with a 32-bit result • SMLALxy instruction is a 16x16+64 with a 64-bit result • SMULxy instruction is a 16x16 with a 32-bit result • SMULWy instruction is a 32x16 with a 32-bit result

Branch Prediction
• QADD adds two registers and saturates the result if an overflow has occurred • QDADD doubles and saturates one of the input registers and then adds and saturates the result • QSUB subtracts two registers and saturates the result if an overflow has occurred • QDSUB doubles and saturates one of the input registers and then subtracts and saturates the result The Intel XScale® microarchitecture implements dynamic branch prediction for the ARM instructions B and BL, and for the Thumb instruction, B. Any instruction that specifies the PC as the destination is predicted as “not taken.” For example, an LDR or an MOV that loads or moves directly to the PC will be predicted “not taken” and incur a branch-latency penalty. These instructions (ARM B, ARM BL, and Thumb B) enter into the branch target buffer when they are “taken” for the first time. (A “taken” branch refers to when they are evaluated to be true.) Once in the branch target buffer, the Intel XScale® microarchitecture dynamically predicts the outcome of these instructions based on previous outcomes. A penalty of “zero” for correct prediction means that the Intel XScale® microarchitecture can execute the next instruction in the program flow in the cycle following the branch.

Extensions to ARM Architecture
The Intel XScale® microarchitecture includes a few extensions to the ARM Version 5 architecture to meet the needs of various markets and design requirements. The following is a list of the extensions that are discussed in the next subsections. • A DSP coprocessor (CP0) has been added that contains a 40-bit accumulator and eight new instructions • New page attributes were added to the page table descriptors; the C- and B-page attribute encoding was extended by one additional bit to allow for more encodings: write-allocate and mini-data cache; an attribute specifying ECC for 1 MB regions was also added

Power Management
The Intel XScale® microarchitecture defines three low-power modes: idle, drowsy, and sleep. All state information is lost on entering sleep mode. The only way to exit sleep mode is through the reset sequence. State is retained in idle and drowsy modes. Both idle and drowsy modes are exited by interrupt, even if the interrupt is masked. A single coprocessor 14 register write is used to enter any low-power mode.

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i.MX31 Multimedia Applications Processors
Core: ARM1136JF-S™ The popular i.MX31 and i.MX31L multimedia applications processors are developed with Freescale’s Smart Speed Technology to drive high performance applications at very low power for extended battery life. The entire portfolio of i.MX processors offers a range of performance and price levels, on chip integration, and broad connectivity options. i.MX processors also have one of the best power-to-performance ratios of any processor in their class. They are becoming the applications processors of choice for portable media players, smartphones, automotive infotainment systems, V2IP phones, video surveillance systems, and many other devices. Freescale provides board support packages (BSPs) to simplify and support development on leading operating systems and RTOSes. Freescale is a Gold-level Microsoft Windows Embedded Partner and offers BSPs for the three most recent Windows CE releases (4.2, 5.0, 6.0) Windows Mobile 5.0 and the new Windows Mobile 6. The i.MX portfolio continues to grow, and new processors will be shipping in production this year. Features
• CPU complex with L2 cache, vector floating point co-processor, and Smart Speed switch • Smart power management including support for multiple low power modes, dynamic voltage frequency scaling, and dynamic process temperature compensation • External memory interface with support for multiple types of memory • Smart multimedia with support for hardware accelerated MPEG4 encode, as well as pre & post processing • Display port with ability to support a variety of popular display devices and up to two displays simultaneously • Sensor port which provides connection to either one or two image sensors • System connectivity, including USB high speed OTG, CSPIs, I2C, PCMCIA, ATA, UARTs • 2D/3D graphics acceleration (only available on i.MX31) • Board support packages for the major operating systems

i.MX31 Block Diagram

Benefits
• • • • • High performance with 32-bit DDR and L2 cache Long battery life for mobile applications Ability to boot from NAND flash MPEG4 playback at 30 fps VGA resolution Interactive console-like gaming experience with OpenGL-ES based graphics acceleration • On chip LCDC eliminates the need for timing chips when using certain displays • Capture, process, and display of moving and still objects • High level of integration simplifies overall board design and lowers BOM cost

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A R M 7 | C o r t e x - M 3 | A R M 9 | C o r t e x - R 4 | XS c a l e | A R M 1 1 | C o r t e x - A 8

Family Comparative Features
Part Number MCIMX31VKN5B Temp °C 0 to +70 Package Core Type Max Timer Variant ID Frequency 532 532 532 2 2 2 Timer Channels 32 32 32 Serial Interface Bits USB Description Peripherals 5 UARTs/1 Fast IR, 1/1-wire I/F, LCD controller, multimedia accelerator, sensor port, 2D/3D graphics accelerator 5 UARTs/1 Fast IR, 1/1-wire I/F, LCD controller, multimedia accelerator, sensor port 5 UARTs/1 Fast IR, 1/1-wire I/F, LCD controller, multimedia accelerator, sensor port, 2D/3D graphics accelerator 5 UARTs/1 Fast IR, 1/1-wire I/F, LCD controller, multimedia accelerator, sensor port

MAPBGA 457 ARM1136JF-S MAPBGA 457 ARM1136JF-S

3/I2C; 2/SSI/I2S; 3 CSPI; 2.0 high speed OTG + 2 hosts 3/I2C; 2/SSI/I2S; 3 CSPI; 2.0 high speed OTG + 2 hosts 3/I2C; 2/SSI/I2S; 3 CSPI; 2.0 high speed OTG + 2 hosts

MCIMX31LVKN5B 0 to +70

MCIMX31CVKN5C -40 to +85 MAPBGA 457 ARM1136JF-S

MCIMX31LCVKN5C -40 to +85 MAPBGA 457 ARM1136JF-S

532

2

32

3/I2C; 2/SSI/I2S; 3 CSPI; 2.0 high speed OTG + 2 hosts

Development Tools Matrix
Tool Name i.MX31 ADS i.MX31 Lite Kit Description Complete hardware development system with power management board and included features such as LCD, camera, and board support packages Low-cost development kit for basic evaluation and application development; peripheral accessories and software available separately Part Number MCIMX31ADSE MCIMX31LITEKIT

i.MX31 Lite Kit

i.MX31 Application Development System

For more information on Arrow’s ARM solutions, pricing, and availability, visit www.arrownac.com/arm or call 1-866-910-3650. To research and compare and contrast ARM solutions, visit www.embedded-developer.com.

i.MX31 Multimedia Applications Processors | Freescale Semiconductor

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Intel ® Network Processors and Intel ® I/O Processors
Core: Intel XScale® Technology Intel XScale® Technology is available in two families: The Intel® network processors family and the Intel® I/O processors family of devices. With a single architecture and integrated design, the Intel® IXP4XX product line of network processors delivers scalable performance, reduced power, and lower cost in packages optimized for residential and small/medium enterprise network applications, as well as communications-based embedded applications. Many storage, networking, and embedded applications require fast I/O throughput for optimal performance. Intel® I/O processors (IOP) allow applications to transfer data faster, reduce communication bottlenecks, and improve overall system performance. Features
• Intel XScale® Microarchitecture running at up to 667 MHz • Intel® network processors: Peripherals - USB, up to 3 10/100 Ethernet MACs, PCI, DDR, Expansion Bus, UARTs, I2C, SSP • Intel® network processors: Advanced Serial Interfaces including a high speed serial port for connecting to T1/E1 or SLICs/CODECs; UTOPIA-2 Support; • Intel® network processors: Integrated support for cryptography, time synchronization and ECC memory • Intel® I/O processors: Integrated Designs • Intel® I/O processors: I/O Processing Performance • Comprehensive Set of Development Tools

Intel ® IXP46X Product Line Block Diagram
HSS-0 HSS-1

UTOPIA-2/MII/SMII

NPEA MII/SMII UTOPIA, AAL, HSS, HDLC
133.32 MHz Advanced High-Performance Bus

MII/Quad SMII

NPE B 1 MII or Quad SMII NPE C MII/SMII AES, DES SHA-1/-256/ -384/-512, MO5

Queue Flag Bus Cryptography Unit EAI, SHA Queue Manager 8KB SRAM

HW RNG DDR1-266 Controller Bridge 32-bit + ECC

MII/SMII PMU (AHB) IEEE 1588 Interrupt Controller

Timers

Memory Port Interface
66.66 MHz Advanced Peripheral Bus Bridge 133.32 MHz Advanced High-Performance Bus Bus Interface Unit UART 921KBaud UART 921KBaud GPIO Controller I2C SSP USB Device v1.1 USB PCI Expansion Bus Host 2.0** Controller Controller Intel XScale® Core 266/400/533/667 MHz 32 KB Data Cache 32 KB Instruction Cache 2 KB Mini-Data Cache

16 GPIO

32-bit + Parity

32-bit

Benefits
• Intel’s groundbreaking new microarchitecture provides very high processor performance with extremely low power consumption; Intel XScale® technology provides the platform for the most advanced designs in storage, infrastructure and embedded communications • Provides reduced overall system cost as well as ease of connectivity to industry standard peripherals/devices • Support for voice applications and connection to industry standard WAN interface • Improves performance and reliability • I/O processors are available in single- or dual-chip configurations this provides developers with pre-validated component sets, simplified board designs, and board-space cost savings • Offloads I/O processing functions, such as I/O interrupt processing and parity calculations from a host processor; I/O processors are also excellent general-purpose processors for high-bandwidth applications that require integrated processors with low power consumption and high-speed peripherals • Faster time-to-market and support for multiple tool-chains and operating systems on the Intel XScale® microarchitecture

**USB 2.0 Host supports low-speed (1.5 Mb/s) and full-speed (12 Mb/s) modes.

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AR M7 | Cortex-M3 | AR M9 | Cortex-R4 | XScale | AR M11 | Cortex-A8

Family Comparative Features
Part Number IXP43X Total RAM Temp °C Package Core M a x A/D A/D Timer Timer Type Variant ID Frequency Bits Channels Channels Bits PBGA PBGA FCBGA5 FCBGA5 FCBGA5 FCBGA5 FCBGA5 PBGA XScale XScale XScale XScale XScale XScale XScale XScale 667 533 800 800 800 1200 1200 667 0 0 0 0 0 0 0 0 – – 0 – – 0 – – 4 4 3 3 3 3 3 4 Serial Interface Description GPIO Ethernet USB Peripherals

eternal up to 1 GB -0 to +70

32 High Speed UART, SSP/SSI, I2C 16 32 32 32 32 32 32 32 2 High Speed UARTs 2xI2C 2xUARTs, 3xI2C 2xUARTs, 3xI2C 2xUARTs, 3xI C 2xUARTs, 3xI2C 2 High Speed UARTs
2

2 x 10/100 2x2.0 HS Host DDR I/II, 32-bit 33 MHz PCI, 16-bit Expansion Bus, UTOPIA 2, DES/3DES/AES/SHA 1/SHA256/384/512, IEEE 1588 2 x 10/100 1x1.1 Device – – – – – – – – – – SDRAM, 32-bit 33 MHz PCI, 16-bit Expansion Bus, SHA-1/MD5/ES/DES,/AES PCI, DDR PCI-X/PCIe, DDRII, 266 MHz 64-bit internal bus PCI-X/PCIe, DDRII, 333 MHz 64-bit internal bus PCI, PCIe, SAS/SATAII, DDII PCI-X/PCIe, 1 or two XScale processor cores, DDRII, 400 MHz 128-bit internal bus

IXP42X eternal up to 256 MB -40 to +85 80219 eternal up to 1 GB 0 to +55 0 to +95 0 to +95 0 to +95 0 to +95

16 8 8 16 16 16 16

IOP331/2 eternal up to 2 GB IOP333 IOP348 eternal up to 2 GB eternal up to 2 GB

IOP341/2 eternal up to 2 GB IXP46X

eternal up to 1 GB -40 to +85

3 x 10/100 1.1 Device, 2.0 DDR I, 32-bit 33 MHz PCI, 32-bit Expansion Bus, FS Host SSP/SSI, I2C UTOPIA 2, DES/3DES/AES/SHA1/ SHA256/384/512, IEEE 1588

Development Tools Matrix
Tool Name Intel® IXDP465 Development Platform
®

Description Intel® IXDP465 Development Platform, optional T1/E1, Voice, and Ethernet Modules; includes 4 PCI expansion slots, 3 Ethernet ports, USB host and device, 2 UARTS
® ® ®

Part Number KIXDP465AD KIXDP425BD

Intel IXDP425 / IXCDP1100 Development Platform Intel IXDP425 / IXCDP1100 Development Platform, Network processor base card with the Intel IXP425 network processor at 533 MHz, Two Intel LXT972A LAN PHY expansion cards, One ADSL PHY expansion card, One voltage regulator expansion card, Two High-Speed Serial (HSS) ports, Two UART (DB-9) connectors, One USB connector, Four PCI bus connectors Intel® KIXRP435 Development Platform Intel® IQ80332 Software Development and Processor Evaluation Kit Intel® IQ80219 Development Kit Intel® EP80219 Development

Intel® KIXRP435 Development Platform Includes 10/100 802.11a/g WLAN, 3x10/100 Ethernet, 2 Wideband FXS + 1 FXO, 2xUSB 2.0, UART, IR, RCA, Audio, Component Video, S-Video KIXRP435 - Hamoa Features Intel® 82545EM Gigabit Ethernet Controller, Primary PCI- PCI Express* supports up to x8 lane, Secondary PCI is PCI-X, two UARTs, Two 7-segment hex LED displays in a dPCI Express form factor Intel® IQ80219 Development Kit featuring a primary PCI-X interface 133 MHz/64-bit or PCI 66 MHz/64-bit, Two Intel® 31244 Serial ATA I/O controllers, Intel® BW31154 PCI 133 MHz transparent bridge,256MB DDR SDRAM with ECC, one PCI-X 64-bit/100 MHz expansion slot Intel® EP80219 Development Kit features a 10/100 Ethernet controller, one GD31244 SATA controller, a serial port, and a mini-PCI connector for expansion, RTC, Power control, and Temp Sensor IQ80332 IQ80219.DOM EP80219

The IQ81342MC board features a 1.2GHZ two core Intel® IOP342 I/O processors processor. This board has dual UARTs, Dual Gbit Ethernet and a x8 PCI Express slot and a 64-bit PCI-X slot for expansion, and fits in a standard flex-ATX chassis. For more information on Arrow’s ARM solutions, pricing, and availability, visit www.arrownac.com/arm or call 1-866-910-3650. To research and compare and contrast ARM solutions, visit www.embedded-developer.com.

Intel, the Intel logo, and Intel XScale are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others.

Intel® Network Processors and Intel® I/O Processors | Intel®

www.arrownac.com/arm

40 |

LPC210x 70 MHz, 32-bit microcontroller with ARM7TDMI-S
Core: ARM7TDMI-S These powerful yet cost-effective microcontrollers have up to 32 KB of zero wait-state Flash and up to 8 KB of SRAM. Each has a 10-bit A/D converter with eight channels and multiple serial interfaces. The lowest-priced part, the LPC2101, starts at only USD $1.47 each for 10 Kpcs, making it an attractive alternative to lower performing 8- or 16-bit MCUs. Blending high performance (63 Dhrystone MIPs) with low power consumption in a tiny 7 mm x 7 mm LQFP48 package makes the part ideal for almost any application. These cost-effective processors are stuffed with a variety of peripherals, including 10-bit ADCs, 4 timers, and multiple I2C, SPI, and UART interfaces. The series also features several new power-saving modes and fast general-purpose I/O, allowing more flexibility for designers. The code and peripherals are fully compatible with all of the other members of the NXP LPC2000 family, which has nearly 40 members and continues to grow.

Features
• • • • • • 70-MHz, 32-bit ARM7 Core Architecture with AHB/APB interfaces Up to 32 KB of zero wait-state Flash Fast 70 MHz performance at 63 Dhrystone MIPs Tiny 7mm x 7mm LQFP packaging Stuffed with low-power features and advanced peripherals Incredibly low pricing starting at $1.47

LPC210x Block Diagram

Benefits
• Ideal upgrade for any application using lower performance 8- or 16-bit MCUs • Ideal for almost any application • Design flexibility

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Family Comparative Features
Part Number LPC2101 LPC2102 LPC2103 Total Flash 8 16 32 Total RAM 2 4 8 Temp. °C -40 to +85 -40 to +85 -40 to +85 Package Type LQFP48 LQFP48 LQFP48 Core Variant ID ARM7TDMI-S ARM7TDMI-S ARM7TDMI-S Max Frequency 70 70 70 A/D Bits 10 10 10 A/D Channels 8 8 8 Timer Channels 7 7 7 Timer Bits 32 32 32 Serial Interface Description 2xUART, SPI, SSP 2xUART, SPI, SSP 2xUART, SPI, SSP GPIO 32 32 32 Ethernet – – – USB – – – Peripherals – – –

Development Tools Matrix
Tool Name Description Part Number MCB2103

MCB2103 evaluation board from Keil The evaluation board connects to your PC using the serial port (for flash download with the NXP LPC2000 FLASH Utility) or the JTAG interface; it can be powered from a USB connector (50mA typical) or from a 5V to 9V DC power supply; debugging is supported via the JTAG interface using the Keil ULINK USB-JTAG adapter and the _Vision IDE and Debugger

MCB2103 Keil Evaluation Board

For more information on Arrow’s ARM solutions, pricing, and availability, visit www.arrownac.com/arm or call 1-866-910-3650. To research and compare and contrast ARM solutions, visit www.embedded-developer.com.

NXP Family of Microcontrollers | NXP

www.arrownac.com/arm

42 |

LPC23xx and LPC24xx 72 MHz, 32-bit microcontrollers with ARM7TDMI-S core
Core: ARM7TDMI-S The LPC23xx and LPC24xx use a high-performance 32-bit ARM7 core that operates at up to 72 MHz. Each device has 512 KB of on-chip Flash. The LPC23xx offers up to 58 KB of SRAM, while the LPC24xx offers up to 98 KB of SRAM. Both devices have two AHB buses, so high-bandwidth peripherals like Ethernet and USB can run simultaneously, without impacting the main application. The LPC24xx is also the only ARM7 MCU with two-port USB capability; it has one USB device, and one USB Host or OTG. This unique ability enables new advances for multiple communications applications by supporting compound (Host + device) USB functionality, such as a USB mini-hub.

Features
• • • • • • On-chip RC-oscillator 4 Mhz trimmed to 1% Four 32-bit general purpose timers PWM block supporting 3-Phase Motor Control Watchdog timer from multiple clock source options 10-bit A/D converter and 10-bit D/A converter Low-power Real Time Clock with 2 KB SRAM and battery back-up • General Purpose DMA controller • High-speed Serial: I2S (digital Audio), three I2C, three SPI/SSP, four UARTs

LPC24xx Block Diagram

Benefits
• Allows fast simultaneous communications operations • Eliminates communication bandwidth bottlenecks • Design flexibility

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Family Comparative Features
Part Number LPC2468FET208 LPC2468FBD208 LPC2378FBD144 LPC2368FBD100 LPC2366FBD100 LPC2364FBD100 Total Flash 512 512 512 512 256 128 Total RAM 98 98 58 58 58 34 Temp.°C -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 Package Type TFBGA208 LQFP208 LQFP144 LQFP100 LQFP100 LQFP100 Core Max Variant ID Frequency ARM7TDMI-S ARM7TDMI-S ARM7TDMI-S ARM7TDMI-S ARM7TDMI-S ARM7TDMI-S 72 72 72 72 72 72 A/D A/D Timer Timer Bits Channels Channels Bits 10 10 10 10 10 10 8 8 8 8 8 8 4 4 4 4 4 4 32 32 32 32 32 32 Serial Interface Description 2xSSP, I2S, 4xUART, 3xI2C 2xSSP, I S, 4xUART, 3xI C SPI, 2xSSP, I S, 4xUART, 3xI C SPI, 2xSSP, I S, 4xUART, 3xI C SPI, 2xSSP, I S, 4xUART, 3xI C SPI, 2xSSP, I S, 4xUART, 3xI C
2 2 2 2 2 2 2 2 2 2

GPIO – – – 70 70 70

Ethernet 10/100 10/100 10/100 10/100 10/100 10/100

USB 2.0 FS, OTG 2.0 FS, OTG 2.0 FS, OTG 2.0 FS, OTG 2.0 high speed OTG + 2 hosts 2.0 high speed OTG + 2 hosts

Peripherals 2xCAN 2xCAN 2xCAN 2xCAN 2xCAN 2xCAN

Development Tools Matrix
Tool Name Keil MCB2300 Evaluation Boards Keil RealView Microcontroller Development Kit Keil ULINK2 Description The Keil MCB2300 Evaluation Boards introduce you to the NXP LPC23xx series of ARM microcontrollers and allow you to create and test working programs for this advanced architecture; two versions of the board are available: the MCB2360 for the 100-pin LPC2368 and the MCB2370 for 144-pin LPC2378 The RealView Microcontroller Development Kit (MDK) supports the LPC24xx family of microcontrollers from NXP; this kit is perfect for the developer who requires industry-standard compilation tools and sophisticated debugging support The Keil ULINK2 USB-JTAG Adapter connects your PC's USB port to your target hardware (via JTAG, SWD, or OCDS) and allows you to debug embedded programs running on target hardware; ULINK2 offers all the features of the original ULINK USB-JTAG Adapter and adds serial wire debug (SWD) support, return clock support, and a real-time agent; ULINK2 works with standard Windows USB drivers Part Number MCB2300 MDK-ARM ULINK2

For more information on Arrow’s ARM solutions, pricing, and availability, visit www.arrownac.com/arm or call 1-866-910-3650. To research and compare and contrast ARM solutions, visit www.embedded-developer.com.

NXP Family of Microcontrollers | NXP

www.arrownac.com/arm

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LPC2478 72 MHz, 32-bit ARM-based microcontroller with integrated LCD support
Core: ARM7TDMI-S These innovative and cost-effective microcontrollers support concurrent operations of high-bandwidth peripherals with significant power savings. The large array of peripherals supported by these devices in addition to the LCD interface include 10/100 Ethernet, USB host/OTG/device, two CAN channels, four UARTs, three I2C buses, two-input and two-output I2S, SPI, SSP, RTC, ADC/DAC, SD/MMC card interface, external interfaces to SRAM, SDRAM and NOR Flash. The LPC2478 microcontroller is the industry’s only ARM7 Flash-based MCU offering integrated LCD support as well as a Flashless version, the LPC2470.

Features
• • • • • • • • 72-MHz, 32-bit ARM7 core with dual AHB interfaces 512 KB of fast 128-bit wide embedded Flash (LPC2478 only) LCD interface 10/100 Ethernet MAC interface with DMA USB 2.0 full-speed OTG/Device/OHCI plus PHY and DMA Two CAN 2.0B controllers with acceptance filtering External interfaces to SRAM, SDRAM, and NOR Flash 10-bit A/D converter and 10-bit D/A converter

LPC247x Block Diagram

Benefits
• Significant savings in cost, area, and power consumption • Ideal for a wide range of industrial, consumer, retail and medical systems using LCD panels and requiring network or Internet connectivity • LCD implementation allows code execution on-chip

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Family Comparative Features
Part Number LPC2470FBD208 LPC2470FET208 LPC2478FBD208 Total Total Temp. °C Package Core Max A/D A/D Timer Timer Flash RAM Type Variant ID Frequency Bits Channels Channels Bits 0 0 512 98 98 98 -40 to +85 LQFP208 ARM7TDMI -40 to +85 TFBGA208 ARM7TDMI -40 to +85 LQFP208 ARM7TDMI 72 72 72 10 10 10 8 8 8 4 4 4 32 32 32 Serial Interface Description 4xUART(1xIrDA), 2xCAN, 2.0/OTG SPI, 2xSSP, 3xI2C, I2S 4xUART(1xIrDA), 2xCAN, SPI, 2xSSP, 3xI2C, I2S 4xUART(1xIrDA), 2xCAN, SPI, 2xSSP, 3xI2C, I2S 4xUART(1xIrDA), 2xCAN, SPI, 2xSSP, 3xI2C, I2S GPIO Ethernet 160 160 160 1 1 1 USB 1 1 1 Peripherals LCD (1024x768), 10/100 with MII/RMII and DMA, USB 2.0/OTG w/PHY and DMA, SD/MMC LCD (1024x768), 10/100 with MII/RMII and DMA, USB 2.0/OTG w/PHY and DMA, SD/MMC LCD (1024x768), 10/100 with MII/RMII and DMA, USB 2.0/OTG w/PHY and DMA, SD/MMC LCD (1024x768), 10/100 with MII/RMII and DMA, USB 2.0/OTG w/PHY and DMA, SD/MMC

LPC2478FET208

512

98

-40 to +85 TFBGA208 ARM7TDMI

72

10

8

4

32

160

1

1

Development Tools Matrix
Tool Name Keil RealView Microcontroller Development Kit Description The RealView Microcontroller Development Kit (MDK) supports the LPC24xx family of microcontrollers from NXP; this kit is perfect for the developer who requires industry-standard compilation tools and sophisticated debugging support The Keil ULINK2 USB-JTAG Adapter connects your PC's USB port to your target hardware (via JTAG, SWD, or OCDS) and allows you to debug embedded programs running on target hardware; ULINK2 offers all the features of the original ULINK USB-JTAG Adapter and adds serial wire debug (SWD) support, return clock support, and a real-time agent; ULINK2 works with standard Windows USB drivers Part Number MDK-ARM

Keil ULINK2

ULINK2

For more information on Arrow’s ARM solutions, pricing, and availability, visit www.arrownac.com/arm or call 1-866-910-3650. To research and compare and contrast ARM solutions, visit www.embedded-developer.com.

NXP Family of Microcontrollers | NXP

www.arrownac.com/arm

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STR7 and STR9 Families
Core: ARM7TDMI, ARM966E-S STMicroelectronics brings the power of 32-bit ARM® processor cores to the world of microcontrollers, opening endless opportunities to embedded system designers by making control and connectivity applications easy and affordable. With a wide range of embedded memories, peripherals and architectural enhancements, ST's STR7 and STR9 families help scale designs to achieve the best fit for an application. STR7 and STR9 families address needs, from low-end to high-performance, with a common set of tools and software, thus reducing cost and time to market.

Features
STR710 ARM7 • Performance up to 45 MIPs @ 50 MHz, 3.0 to 3.6V, and -40 to +85°C • STR7’s biggest RAM (64 KB) • The most UARTs (4) • External memory interface • Peripherals include CAN, USB, 4xUARTs, and SC interface (ISO7816) • Consumer and industrial applications STR730 ARM7 • Performance up to 32 MIPs @ 36 MHz, 4.5 to 5.5V, and -40 to +85°C, or up to +105°C • The most timers (20) • The most CANs (3), UARTs (4), and the most I/Os (112) • Peripherals include 3xCANs, 4xUARTs, and up to 20 timers, 16 DMA • Industrial and automotive related applications

STR750 ARM7 • Performance up to 54 MIPs @ 60 MHz, 3.0 to 3.6V or 4.5 to 5.5V, and -40 to +85°C, or up to +105°C • The best integration and balanced control/communication • Safety and low power • Unique motor control peripherals • Suitable for many general-purpose applications • Peripherals include CAN, USB, 3xUARTs, and advanced timers • General-purpose and vector drive applications STR910 ARM9E • Performance up to 96 MIPs @ 96 MHz, 2.7 to 3.6V I/O, 1.8V core, and -40 to +85°C • Highest performance (96 MHz ARM9E) • Largest Flash/RAM memory size (544 KB/96 KB) • Ethernet connectivity • Designed to complement STR7 for bigger memory, higher performance and Ethernet connectivity • Binary compatible with ARM7TDMI core code • Peripherals include Ethernet, USB, CAN, and 3xUARTs • Performance and connectivity applications

STR7 and STR9 Portfolio Diagram

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STR730F
Core: ARM7TDMI STR730F Flash microcontrollers combine the industry standard ARM7TDMI® RISC microprocessor with embedded Flash and powerful peripheral functions, including up to 20 timers, 4xUARTs and 3xCANs. The STR730F MCUs are ideal for embedded applications requiring a compact yet powerful MCU, as well as versatile, scalable solutions such as user interfaces, factory automation systems and appliances. Additionally, the STR730F family features a single 5V power supply particularly suited to industrial applications.

Features
• Largest choice of peripherals and interfaces including 4xUART, up to 20 timers and up to 3xCAN • Flexible power and clock management • Five low-power modes • Low-power voltage regulator • Extensive software and tools including the complete STR7 library supporting all standard peripherals and CAN • Dual APB buses architecture • Single 5V power supply • 16-channel DMA

STR730F Block Diagram

Benefits
• Reduces system cost with all peripherals in one chip • Full control over your power consumption and performance/power tradeoffs • Precisely manage low-power vs. performance • Built-in voltage regulator means fewer external components • Software library dramatically reduces development time and increases ease-of-use • Increased overall performance due to dual buses • Native 5V supply of industrial applications; no 3.3V conversion needed • DMA lowers CPU load, optimized access to memory

For more information on Arrow’s ARM solutions, pricing, and availability, visit www.arrownac.com/arm or call 1-866-910-3650. To research and compare and contrast ARM solutions, visit www.embedded-developer.com.

STR730F Family of Microcontrollers | STMicroelectronics

www.arrownac.com/arm

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STR710F
Core: ARM7TDMI The STR710F series is loaded with many communication interfaces including USB, CAN, ISO7816 and four UARTs. It is endowed with the biggest RAM of all STR7 MCUs (up to 64 KB) and implements an optional external memory interface. This makes it a perfect fit for consumer, point of sales and high-end industrial applications. The STR710F also features high performance, very low power, and very dense code, and ST's latest 0.18µ embedded Flash technology.

Features
• Largest choice of peripherals and interfaces, including USB and CAN • Flexible power and clock management • Superior RAM/FLASH ratio • High-quality embedded Flash with 16 K extra Flash for EE emulation (20 year retention at 85°C) • Extensive package options including the space efficient 8x8 LFBGA64 and 10x10 LFBGA 144 • Extensive software and tool support including the complete STR7 library for USB

STR710F Series Block Diagram

Benefits
• Reduces system cost with all peripherals on one chip • Allows full control over power consumption and performance/power tradeoffs • Unlimited possibilities - up to 64 K RAM, and always above 16 K even with smallest Flash option • 16 K extra Flash reduces system cost with no need for external EEPROM • Software and tools support dramatically reduces development time and increases ease-of-use

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Family Comparative Features
Part Number STR710FZ1 STR710FZ2 STR711FR0 STR711FR1 STR711FR2 STR712FR0 STR712FR1 STR712FR2 STR715FR0 Total Flash 144 272 80 144 272 80 144 272 80 Total RAM 32 64 16 32 64 16 32 64 16 Temp. °C -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 Package Type BGA144, LQFP144 BGA144, LQFP144 BGA64, LQFP64 BGA64, LQFP64 BGA64, LQFP64 BGA64, LQFP64 BGA64, LQFP64 BGA64, LQFP64 BGA64, LQFP64 Core Variant ID ARM7TDMI ARM7TDMI ARM7TDMI ARM7TDMI ARM7TDMI ARM7TDMI ARM7TDMI ARM7TDMI ARM7TDMI Max Frequency 66 66 66 66 66 66 66 66 66 A/D A/D Timer Bits Channels Channels 12 12 12 12 12 12 12 12 12 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Timer Bits 16 16 16 16 16 16 16 16 16 Serial Interface Description 4xUART, 2xSPI, 2xI2C, CAN, SC 4xUART, 2xSPI, 2xI2C, CAN, SC 4xUART, 2xSPI, 2xI2C, SC 4xUART, 2xSPI, 2xI2C, SC 4xUART, 2xSPI, 2xI2C, SC 4xUART, 2xSPI, 2xI2C, CAN, SC 4xUART, 2xSPI, 2xI2C, CAN, SC 4xUART, 2xSPI, 2xI2C, CAN, SC 4xUART, 2xSPI, 2xI2C, SC GPIO 48 48 30 30 30 32 32 32 32 Ethernet — — — — — — — — — USB Device 2.0 Device 2.0 Device 2.0 Device 2.0 Device 2.0 — — — — Peripherals EMI EMI — — — — — — —

Development Tools Matrix
Tool Name REva Starter Kit - Raisonance Description The REva starter kit from Raisonance is a cost-effective and complete solution for evaluating and starting application development Part Number STR71X-SK/RAIS STR711-SK/IAR

IAR KickStart Kit™ with STR711 IAR KickStart Kits™ are cost effective and complete evaluation and development systems in a single package; they are designed to help you to a flying start by providing all the necessary hardware and software you need to design, implement and test your STR7 application; includes J-Link: In-circuit debugger/programmer, featuring USB host interface and industry standard JTAG interface for application board connection; with STR711 target MCU IAR KickStart Kit™ with STR712 IAR KickStart Kits™ are cost effective and complete evaluation and development systems in a single package; they are designed to help you to a flying start by providing all the necessary hardware and software you need to design, implement and test your STR7 application; includes J-Link: In-circuit debugger/programmer, featuring USB host interface and industry standard JTAG interface for application board connection; with STR712 target MCU Hitex Starter Kit The Hitex Starter Kit for STR7 is a complete solution for evaluating and starting application development with ST ARM core-based microcontrollers; includes: application board; Tantino, in-circuit debugger/programmer, featuring USB host interface and industry standard JTAG interface; HiTOP5, 16K code-size limited version of Hitex’s full-featured Integrated Development Environment; plus GNU C/C++ Compiler The Keil starter kit, available from Keil, is a complete solution for evaluating and starting application development with the STR7; the package includes: application board with user LEDs, push buttons, switches, potentiometer and interfaces for device specific peripherals; ULink, in-circuit debugger/programmer; uVision3, the full-featured Integrated Development Environment; RealView Compilation Tools, 16K code-size limited version of the optimizing C/C++ compiler

STR712-SK/IAR

STR710-SK/HIT

Keil STR710 kit

STR710 kit

STR710F Series

IAR, Raisonance, & Hitex Starter Kits

For more information on Arrow’s ARM solutions, pricing, and availability, visit www.arrownac.com/arm or call 1-866-910-3650. To research and compare and contrast ARM solutions, visit www.embedded-developer.com.

STR710F Family of Microcontrollers | STMicroelectronics

www.arrownac.com/arm

50 |

STR750F
Core: ARM7TDMI The STR750F microcontrollers are the latest series in the STR7 family. These MCUs bring the best integration with a balanced peripheral set, USB, CAN, and key innovations like clock failure detection and advanced motor control timers. The STR750F supports either 3.3V or 5V systems, and it is also available in an extended temperature range (-40°C to +105°C). This makes it a genuine general purpose microcontroller, suitable for a wide range of applications such as appliance, brushless motor drive, USB peripheral, UPS, alarm systems, programmable logic controller, circuit breakers, inverters, and medical and portable equipment.

Features
• Excellent low power performance through flexible clock management and multiple low power modes with consumption down to 10 µA in standby mode • Innovative backup clock • Fast startup and wakeup • Auto wake-up • Serial memory interface (SMI) and LIN support • Single supply, 3.3V or 5V (3.3V for USB) • Powerful timers and fast ADC • Extensive firmware support and tools; the STR750F library is freely distributed by ST

STR750F Block Diagram

Benefits
• Easy adjustment of performance/power consumption ratio; suitable for battery operated applications • Additional security due to backup clock • Fast startup and wakeup adds responsiveness • Auto wakeup improve power-savings • Less external hardware needed • 3.3V or 5V supply gives additional flexibility for customers; no need for external regulator; real 5V drive on the I/Os when 5V is used • Perfect fit for tri-phase motor control applications • Extensive library dramatically reduces development time and increases ease of use

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A R M 7 | C o r t e x - M 3 | A R M 9 | C o r t e x - R 4 | Xs c a l e | A R M 1 1 | C o r t e x - A 8

Family Comparative Features
Part Number STR755FR0 STR752FR0 STR751FR1 STR752FR1 STR755FR1 STR751FR2 STR752FR2 STR751FR0 STR755FV2 STR750FV2 STR750FV1 STR755FV1 STR750FV0 STR755FV0 STR755FR2 To ta l Flash 80 80 144 144 144 272 272 80 272 272 144 144 80 80 272 To ta l RAM 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 Temp. °C -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 Pa ckage Type LQFP64 LQFP64 LQFP64 LQFP64 LQFP64 LQFP64, BGA64 LQFP64, BGA64 LQFP64 Core Va riant ID ARM7TDMI ARM7TDMI ARM7TDMI ARM7TDMI ARM7TDMI ARM7TDMI ARM7TDMI ARM7TDMI ARM7TDMI ARM7TDMI ARM7TDMI ARM7TDMI ARM7TDMI ARM7TDMI ARM7TDMI Max. Frequency 60 60 60 60 60 60 60 60 60 60 60 60 60 60 60 A/D Bits 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 A/D Channels 11 11 11 11 11 11 11 11 16 16 16 16 16 16 11 Timer Channels 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 Timer Bits 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 Serial Interface Description 2xSSP, 3xHS-UART, I2C 2xSSP, 3xHS-UART, I2C, CAN 2xSSP, 3xHS-UART, I2C 2xSSP, 3xHS-UART, I2C, CAN 2xSSP, 3xHS-UART, I2C 2xSSP, 3xHS-UART, I2C 2xSSP, 3xHS-UART, I2C, CAN 2xSSP, 3xHS-UART 2xSSP, 3xHS-UART, I2C 2xSSP, 3xHS-UART, I2C, CAN 2xSSP, 3xHS-UART, I2C, CAN 2xSSP, 3xHS-UART, I2C 2xSSP, 3xHS-UART, I2C, CAN 2xSSP, 3xHS-UART, I2C 2xSSP, 3xHS-UART, I2C G PIO 38 38 38 38 38 38 38 38 72 72 72 72 72 72 38 Ethernet – – – – – – – – – – – – – – – US B – – Device 2.0 – – Device 2.0 – Device 2.0 – Device 2.0 Device 2.0 – Device 2.0 – – Pe ripherals RTC, Motor Control RTC, Motor Control RTC, Motor Control RTC, Motor Control RTC, Motor Control RTC, Motor Control RTC, Motor Control RTC, Motor Control RTC, Motor Control RTC, Motor Control RTC, Motor Control RTC, Motor Control RTC, Motor Control RTC, Motor Control RTC, Motor Control

-40 to +85 LQFP100, BGA100 -40 to +85 LQFP100, BGA100 -40 to +85 LQFP100, BGA100 -40 to +85 -40 to +85 -40 to +85 -40 to +85 LQFP100 TQFP100 LQFP100 LQFP64, BGA64

Development Tools Matrix
Tool Name STR750 Full Evaluation Board Hitex Starter Kit for STR750 Description STR750F full evaluation board with 2 x 16 LCD, LEDs, UART and CAN interfaces Hitex starter kit with STR750 evaluation board, USB-JTAG in-circuit debugger/programmer and 16 KB code-size limited version of HiTOP software toolchain Part Number STR750-EVAL STR750-SK/HIT STR750-SK/IAR STR750-SK/KEIL STR750-SK/RAIS STR750-MCKIT

IAR KickStart™ Kit for STR750 IAR KickStart™ starter kit with STR750 evaluation board, USB-JTAG in-circuit debugger/programmer and 32 KB code-size limited version of EWARM software toolchain Keil Starter Kit for STR750 REva Starter Kit - Raisonance STR750 Motor Control Kit Keil starter kit with STR750F evaluation board, USB-JTAG debugger and evaluation version of RealView Microcontroller Development Kit for ARM with uVision3 and ARM RealView Compilation Tools Raisonance REva starter kit for STR750F with RLink In circuit debugger/programmer (USB host interface), REva mother board, STR750F daughter, 16 KB code-size limited version of the RIDE software tool set and GNU C/C++ compiler for ARM This motor control kit is ready to run within minutes for PMSM and induction 3-phase motors using STR750F for vector control drive. PMSM motor included

For more information on Arrow’s ARM solutions, pricing, and availability, visit www.arrownac.com/arm or call 1-866-910-3650. To research and compare and contrast ARM solutions, visit www.embedded-developer.com.

ST750F Family of Microcontrollers | STMicroelectronics

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STR910F
Core: ARM966E-S The STR910F family of MCUs delivers up to 96 MIPS peak performance while executing code directly from its Flash memory, executes single-cycle DSP instructions within its ARM966E-S core, and includes Ethernet, USB, and CAN interfaces. These features, combined with Flash memory sizes reaching 544 Kbytes and a vast 96 Kbyte SRAM, make the STR910F an ideal single-chip solution to transform embedded control applications into low cost nodes on a local network, or on the Internet.

Features
• 96 MHz ARM966E-S CPU core with single-cycle DSP instructions and independent internal 32-bit buses • 10/100 Ethernet connectivity with optimized DMA data flow • Plentiful SRAM and Flash memories • Dual bank Flash • Flexible power and clock management with multiple low power modes • Low power (< 1 µA) real-time clock with programmable wake-up features • Extensive firmware support and tools offering. The STR910F library is freely distributed from ST • Analog capability with 10-bit ADC and full supervisor functions

STR910F Block Diagram

Benefits
• Simultaneous access to both code and data, generating 96 MIPS peak performance executing code from Flash memory, and at the same time capable of up to 384 Mbytes/sec DMA data flow between peripherals and SRAM • Connect your product to a network and retain ample CPU bandwidth to implement the embedded application • Meet requirements of complex applications, real-time operating systems (RTOSs), communication stacks and data storage • Ideal for robust In-Application Programming (IAP) and EEPROM emulation • Tailor your system on the fly to balance performance and power consumption as needed • Ideal for battery operated applications • Extensive firmware support dramatically reduces development time and increases ease of use • With so much inside, less is needed outside saving you space, cost and logistic headaches

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A R M 7 | C o r t e x - M 3 | A R M 9 | C o r t e x - R 4 | XS c a l e | A R M 1 1 | C o r t e x - A 8

Family Comparative Features
Part Number STR911FM44 STR912FW44 STR912FW42 STR911FM42 STR910FW32 STR910FM32 Total Flash 544 544 288 288 288 288 Total RAM 96 96 96 96 64 64 Temp. °C -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 Package Type LQFP80 LQFP128 LQFP128 LQFP80 LQFP128 LQFP80 Core Variant ID ARM966E-S ARM966E-S ARM966E-S ARM966E-S ARM966E-S ARM966E-S Max Frequency 96 96 96 96 96 96 A/D Bits 10 10 10 10 10 10 A/D Timer Timer Channels Channels Bits 8 8 8 8 8 8 7 7 7 7 7 7 16 16 16 16 16 16 Serial Interface Description 3xUART, 2x SPI, CAN, 2xFast I2C 3xUART, 2x SPI, CAN, 2xFast I C 3xUART, 2x SPI, CAN, 2xFast I C 3xUART, 2x SPI, CAN, 2xFast I2C 3xUART, 2x SPI, CAN, 2xFast I C 3xUART, 2x SPI, CAN, 2xFast I C
2 2 2 2

GPIO 40 80 80 40 80 40

Ethernet – MAC 10/100 MAC 10/100 – – –

USB Device 2.0 Device 2.0 Device 2.0 Device 2.0 – –

Peripherals RTC, Motor Control RTC, Motor Control, EMI RTC, Motor Control, EMI RTC, Motor Control RTC, Motor Control RTC, Motor Control

Development Tools Matrix
Tool Name STR9 Full Evaluation Board Description An open-design evaluation platform for STR910F, which includes reference code and a range of hardware features for evaluation of device peripherals including USB, Ethernet, CAN, ADC and much more; in addition to a JTAG standard interface for in-circuit debugging and programming, it includes an ETM interface for connection of a trace tool IAR KickStart starter kit with STR9 evaluation board, USB-JTAG in-circuit debugger/programmer and 32 KB code-size limited version of EWARM software toolchain Keil starter kit with STR9 evaluation board, USB-JTAG debugger and evaluation version of RealView Microcontroller Development Kit for ARM with uVision3 and ARM RealView Compilation Tools Raisonance REva starter kit for STR9 with RLink In circuit debugger/programmer (USB host interface), REva mother board, STR9 daughter board, 16 KB code-size limited version of the RIDE software tool set and GNU C/C++ compiler for ARM Hitex starter kit with STR9 evaluation board, USB-JTAG in-circuit debugger/programmer and 16 KB code-size limited version of HiTOP software toolchain Part Number STR910-EVAL

IAR KickStart™ Kit for STR9 Keil STR9 Starter Kit REva Starter Kit - Raisonance

STR91X-SK/IAR STR91X-SK/KEI STR91X-SK/RAI

Hitex Starter Kit for STR9

STR91X-SK/HIT

IAR KickStart Kit For more information on Arrow’s ARM solutions, pricing, and availability, visit www.arrownac.com/arm or call 1-866-910-3650. To research and compare and contrast ARM solutions, visit www.embedded-developer.com.

STR910F Family of Microcontrollers | STMicroelectronics

www.arrownac.com/arm

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DaVinci™ TMS320DM644x Digital Signal Processing SoCs
Core: ARM9 + TMS320C64x+ DaVinci™ technology makes break-through innovation possible in digital media devices for the hand, home, and car. DaVinci is the first integrated portfolio of Digital Signal Processing SoCs, software, tools, and support optimized for digital video systems. These integrated components are the industry’s first complete offering of an open platform. Sampling today, the portfolio of DaVinci processors include the TMS320DM644x digital media processors which are highly integrated SoCs based on an ARM926 processor and the TMS320C64x+ DSP core. The TMS320DM644x processors are ideal for applications such as videophones, automotive infotainment, digital still cameras, streaming media, and IP set-top boxes.

Features
• Integrated portfolio of Digital Signal Processing SoCs, software, development tools, and support • Optimized for digital video systems, DaVinci technology accelerates innovation • A complete portfolio of TI-developed digital media software is now widely available to further simplify design; the software portfolio includes multimedia codecs such as H.264, MPEG-4, WMA9 and many more; for a free evaluation, visit www.ti.com/digitalmediasoftware • Supports several Operating Systems, appropriate for different applications, including open source Linux, MontaVista™ Linux, Green Hills INTEGRITY™, Green Hills VelOSity, QNX Neutrino and Microsoft Windows® CE

TMS320DM6446 DSP Block Diagram

Benefits
• Save months of development time by leveraging integrated, production-tested software and hardware components • An open development platform enables OEM product differentiation with a flexible, complete solution • Lower system cost significantly and leverage IP across multiple products • Standard operating systems will allow developers with expertise on these systems to work in an environment that is familiar • Valued members of TI’s Third Party Network provide integral components and tools that complement DaVinci™ technology; they offer various levels of video system integration, optimization and system expertise on DaVinci products worldwide

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A R M 7 | C o r t e x - M 3 | A R M 9 | C o r t e x - R 4 | XS c a l e | A R M 1 1 | C o r t e x - A 8

Family Comparative Features
Part Number TMS320DM6441ZWT Total Flash Total RAM Temp. °C Package Type Max. Frequency A/D Bits A/D Channels Timer Channels Serial Interface Description ASP, I2C, SPI, 3xUARTs ASP, I2C, SPI, 3xUARTs ASP, I2C, SPI, 3xUARTs GPIO 71 Ethernet USB Peripherals Video port front end, video port back end, VICP, VLYNQ, NAND Flash, SmartMedia/xD, ATA/CF, MMC/SD. This device is similar to the TMS320DM6446BZWT Video port back end, VICP, VLYNQ, NAND Flash, SmartMedia/xD, ATA/CF, MMC/SD Video port front end, video port back end, VICP,VLYNQ, NAND Flash, SmartMedia/xD, ATA/CF, MMC/SD

16 176 (DSP), 0 to +85 361 Pb-free BGA 513/405 DSP, N/A (ARM) 40 (ARM) 257/202 RISC 16 176 (DSP), 0 to +85 361 Pb-free BGA (ARM) 40 (ARM) 16 176 (DSP), 0 to +85 361 Pb-free BGA (ARM) 40 (ARM) 594 DSP, 297 RISC 594 DSP, 297 RISC N/A N/A

16 (ARM) 1 x 64-bit WD, 2 x 64-bit GP 16 (ARM) 1 x 64-bit WD, 2 x 64-bit GP 16 (ARM) 1 x 64-bit WD, 2 x 64-bit GP

10/100 Mbps EMAC USB 2.0

TMS320DM6443BZWT TMS320DM6446BZWT

71 71

10/100 Mbps EMAC USB 2.0 10/100 Mbps EMAC USB 2.0

Development Tools Matrix
Tool Name Digital Video Evaluation Module Description The Digital Video Evaluation Module (DVEVM) allows developers to write production-ready application code for the ARM and provides access to the DSP core using DaVinci APIs to begin immediate application development for the TMS320DM6441, TMS320DM6443 and TMS320DM6446 digital media processors Part Number TMDXEVM6446 TMDSSDK6446-L

Digital Video Software Development Kit The Digital Video Software Development Kit (DVSDK) is a software development kit designed to tune complex DaVinci-based digital video systems quickly and efficiently; the DVSDK significantly improves software integration and system visibility by incorporating tools such as the eXpressDSP™ Configuration Kit, TMS320DM644x SoC Visual Analyzer and MontaVistas Linux

Digital Video Software Development Kit

Digital Video Evaluation Module

For more information on Arrow’s ARM solutions, pricing, and availability, visit www.arrownac.com/arm or call 1-866-910-3650. To research and compare and contrast ARM solutions, visit www.embedded-developer.com.

DaVinci™ Family of Microcontrollers | Texas Instruments, Inc.

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IAR Embedded Workbench Version 4.41 for ARM ®
C/C++ Compiler and Debugger Tools for ARM IAR Embedded Workbench® is a set of highly sophisticated and easy-to-use development tools for programming ARM® embedded applications. It integrates the IAR C/C++ compiler, assembler, linker, librarian, text editor, project manager, and C-SPY® debugger in one Integrated Development Environment (IDE). With its built-in chip-specific code optimizer, IAR Embedded Workbench generates very efficient and reliable FLASH/PROMable code for ARM devices. In addition to this solid technology, IAR Systems provides professional, worldwide technical support.

The ARM Cortex-M3 processor offers significant benefits to system and software developers. • ARM7 (ARM7TDMI, ARM7TDMI-S, and ARM720T) • ARM9 (ARM9TDMI, ARM920T, ARM922T, and ARM940T) • ARM9E (ARM926EJ-S, ARM946E-S, and ARM966E-S) • ARM11 • Cortex-M3 • Intel® XScale™ core

Key Components
• IDE with project management tools and editor • Highly-optimizing ARM compiler supporting C and C++ • Configuration files for ARM chips from Analog Devices, Atmel, Freescale, Intel, Luminary Micro, NXP, STMicroelectronics, and Texas Instruments • Extensive JTAG and RDI debugger support • Optional IAR J-Link and IAR J-Trace hardware debug probes • Run-time libraries including source code • Relocating ARM assembler • Linker and librarian tools • C-SPY debugger with ARM simulator, JTAG support, and support for RTOS-aware debugging on hardware • Evaluation edition of IAR PowerPac RTOS and file system bundle • RTOS plug-ins available from IAR Systems and RTOS vendors • Code templates for commonly used code constructs • Sample projects for evaluation boards from many different manufacturers • User and reference guides, both printed and in PDF format • Context-sensitive online help

Highlights in the Current Version
• IAR PowerPac bundled evaluation edition of RTOS and file system for ARM • Live watch on target hardware • Code coverage using IAR J-Trace • Comprehensive Flash loader support • I/O register definition files • More than 400 sample projects for different evaluation boards

Supported ARM Cores and Devices
IAR Embedded Workbench supports ARM7, ARM9, ARM9E, ARM11, Cortex-M3, and Intel® XScale™ devices from these manufacturers: • • • • Analog Devices Freescale Semiconductor Luminary Micro STMicroelectronics • • • • Atmel Intel NXP Texas Instruments

For more information on Arrow's Development Tools, pricing and availability, visit www.arrowdevtools.com or call 1-866-910-3650.

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Chip-Specific Support
• Ready-made C/C++ and assembler peripheral register definition files • Multiple code and data models (where applicable) • Extensive set of language features for PROMable embedded code, including memory keywords, intrinsic functions, interrupt functions, memory-mapped I/O ports, etc. • Sample projects for evaluation boards from IAR Systems, Analog Devices, ARM, Atmel, Freescale, Keil, LogicPD, Luminary Micro, Nohau, NXP, Phytec, STMicroelectronics, and Texas Instruments • Support for 4 Gbyte applications in ARM and Thumb® mode • Each function can be compiled in ARM or Thumb mode • Vector Floating Point (VFP) coprocessor code generation • Flash loaders included for devices from Analog Devices, Atmel, Freescale, Luminary Micro, NXP, STMicroelectronics, and Texas Instruments • ARM Angel debug monitor support

• Trace utility to examine execution history: moving around in the trace window updates the editor and disassembly windows to show the appropriate location • Terminal I/O emulation • Interrupt and I/O simulation • C-like macro system to extend debugger functionality • Application program system calls emulated by the host • Code coverage and profiling performance analysis tools • Support for the ARM Debug Communication Channel (DCC) • Generic Flash loader with API guide • Multiple Flash loaders supported • Debugger software development kit for third-party extensions such as real-time operating systems and emulator drivers • Command line debugger utility

Graphical IDE
• Hierarchical project presentation • Multiple projects within the same workspace • Dockable windows and multiple views • Source browser • Library tools included for creating and maintaining libraries • Integration with source code control systems • Text editor with multi-byte character support: context-sensitive help system; syntax coloring; unlimited undo/redo; find; search; replace; incremental search; bookmarks; error tags; previous/next navigation; matching brackets; smart indentation; code breakpoint set/clear/enable/disable; and multiple panes • Command line build utility

Embedded Focus
• Advanced generic and processor-specific optimizations for speed and memory footprint • Lightweight runtime library: user-configurable to match the needs of the application; full source included • Flexible memory handling allows detailed control of code and data placement • Unnecessary functions and variables are removed • Application-wide type checking of C/C++ variables and functions at link time • Optional flexible checksum generation for image runtime verification • Automatic placement of code and data in non-contiguous memory regions • Powerful relocating macro assembler with a versatile set of directives and operators

Language and Standards
• The C programming language, as standardized by ISO/ANSI C94, with selected features from C99 • Embedded C++ extended with templates, multiple and virtual inheritance, namespaces, and other C++ features that do not cause an overhead in size or speed; full Embedded C++ library containing string, streams, etc., as well as the Standard Template Library (STL) • IEEE-754 floating-point arithmetic • MISRA C checker • Supports a wide range of industry-standard debug and image formats: compatible with most popular debuggers and emulators, including ELF/DWARF where applicable

Embedded Debugging
• Fully integrated debugger for source and disassembly level debugging • Very fine granularity execution control (function call-level stepping) • Complex code and data breakpoints • Versatile monitoring of data: locals, watch, auto, live watch, and quick watch windows; register and memory windows • STL container awareness • C/C++ call stack window that also shows the function to be entered; double-click on any function in call chain updates the editor, locals, register, watch, and disassembly windows to display the state of that particular function at the time of call

User Assistance
• Ready-made sample projects and project templates • Context-sensitive online help with library function lookup • Printed user guides with extensive step-by-step tutorials • User friendly, detailed, and precise error messages and warnings

www.arrownac.com/arm

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The Keil RealView Microcontroller Development Kit
Create Applications for ARM7, ARM9, or Cortex-M3 Based Microcontrollers The RealView® Microcontroller Development Kit (MDK) shortens development cycles by reducing the time spent configuring, testing, and debugging embedded applications. The RealView MDK combines ARM RealView compilation tools with the Keil µVision® Integrated Development Environment (IDE), providing developers with a feature-rich environment optimized for ARM-Powered® microcontrollers.

The Keil µVision IDE includes
• Project management and device and tool configuration • A source code editor optimized for embedded systems • Target debugging and Flash programming • Accurate device simulation (CPU and peripheral)

RealView Microcontroller Development Kit
µVision Project Manager

RealView Real-Time Library
RTX Source Code

C/C++ Compiler

Macro Assembler

TCP/IP Suite
TCP, UDP, PPP, SLIP, ARP, DNS Resolver, Ethernet, DHCP Client, HTTP Server with CGL TFTP Server, SMTP Client

RTX RTOS Libraries

ARM technology-based projects created under µVision are automatically compiled and linked using the RealView compilation tools. The built-in microcontroller simulator models more than 50 ARM-Powered® devices, including the ARM instruction set, on-chip peripherals, and the external signals used to manipulate them. ARM RealView compilation tools are recognized by the industry for providing the best performance of all available ARM technology-targeted compilers. Developed and tuned to deliver the tightest code density, the compiler produces the smallest code size, which leads to significant product cost savings. The compiler generates optimized code for both the 32-bit ARM and 16-bit Thumb® instruction sets while supporting full ISO standard C and C++.

Linker / Locator

Flash File System

µVision Debugger

USB Device Interface

Device Simulation

Target Hardware

CAN Interface

Project Management
File groups allow associated files to be grouped together. They may be used to separate files into functional blocks or to identify engineers in your software team. Project targets allow you to create several programs from a single project. You may require one target for testing and another target for a release version of your application. Each target allows individual tool settings within the same project file.

Project Configuration
The µVision IDE incorporates a device database of supported ARM-Powered microcontrollers. In µVision projects, required options are set automatically when you select the device from the device database. µVision displays only those options that are relevant to the selected device and prevents the selection of incompatible directives. Only a few dialogs are required to completely configure all the tools (assembler, compiler, linker, debugger, and Flash download utilities) and memory map for your application.

Editor
The µVision Editor includes all the standard features you expect in a professional editor. Color syntax highlighting and text indentation are optimized for editing C source files, while document outlining allows you to collapse function blocks in your source code. Most Editor functions are quickly accessed from the toolbars. While debugging, the Editor is available so you can easily make changes to your source code.

For more information on Arrow's Development Tools, pricing and availability, visit www.arrowdevtools.com or call 1-866-910-3650.

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Debugger
The µVision Editor enables you to set simple breakpoints using the context menu (or Editor toolbar) while creating your C or assembler source. Breakpoints you set while editing are activated when you start the µVision Debugger. In addition to simple breakpoints, the µVision Debugger supports complex breakpoints (with conditional or logical expressions) and memory access breakpoints (with read/write access from an address or range). The Debugger also displays code coverage and execution profiling information in the Editor windows.

Accurate Device Simulation
The µVision Debugger simulates a complete ARM-Powered microcontroller including the instruction set and on-chip peripherals. These powerful simulation capabilities provide serious benefits and promote rapid, reliable embedded software development. • Simulation allows software testing on your desktop with no hardware environment • Early software debugging on a functional basis improves overall software reliability • Simulation allows breakpoints that are not possible with hardware debuggers • Simulation allows for optimal input signals (hardware debuggers add extra noise) • Signal functions are easily programmed to reproduce complex, real-world input signals • Single-stepping through signal processing algorithms is possible; external signals stop when the CPU halts • It is easy to test failure scenarios that would destroy real hardware peripherals

RealView Real-Time Library
The RealView Real-Time Library (RL-ARM) enables networking, communication, and real-time software. The RL-ARM is based on a real-time kernel that simplifies the design and implementation of complex, time-critical applications. A Flash file system, TCP/IP networking suite, and other communication protocols are included. Today, microcontroller applications require simultaneous execution of multiple jobs or tasks. For such applications, the RL-ARM allows task management and flexible scheduling of system resources (CPU, memory, etc.). The RL-ARM is a full-featured real-time kernel with task priorities, round-robin, preemptive context switching, and support for multiple instances of the same task function. It is royalty-free and is fully integrated into µVision.

Third-Party Utilities
Third-party utilities extend the functions and capabilities of µVision and are available from a wide variety of vendors.

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RealView Tools by ARM
Tools that Span the Complete Development Process RealView® tools by ARM® are unique in their ability to provide solutions that span the complete development process from concept to final product deployment. Each member of the RealView portfolio has been developed closely alongside IP, ensuring that it maximizes the IP’s performance.

RealView Development Suite
RealView Development Suite is the only complete, end-to-end solution for software development that supports all ARM® processors and ARM debug technology. These tools offer the highest-performance ARM C/C++ compilers and support the most advanced debug technology available today for bringing up the latest SoC and ASIC designs. Proven to deliver the highest return for the lowest risk on their ARM-based ASICs, SoC, and FPGA designs, the RealView Developer Suite is a trusted source for ARM development solutions. Today, the majority of the four billion ARM-Powered™ devices worldwide have software created with RealView tools. Investing in the RealView solution is the clear choice for a safe, reliable, and high-performance design.

Eclipse Plug-ins for RealView Development Suite
RealView Development Suite integrates with the open-source Eclipse IDE. This integration combines Eclipse’s outstanding source code development tools and plug-in framework with the best-in-class compilation and debug technology in the RealView DEVELOP family of tools. The RealView Eclipse Plug-in enables developers to use Eclipse as a project manager to create, build, debug, and manage C and C++ projects for ARM targets. The plug-in provides project stationery to simplify the creation of ARM, Thumb®, and ARM/Thumb architecture-based projects, and provides comprehensive configuration panels to specify options for the RealView Development Suite.

Compilation Tools New Features of RealView Development Suite 3.0 and SP1
Key features of the RealView Development Suite 3.0 solution include support for the full line of ARM processors, including the Cortex™-A8 processor, the Cortex-M3 processor, and future Cortex family processors; support for CoreSight™ advanced debug and trace technology; an intrinsics compiler for the NEON™ SIMD technology; an enhanced compiler optimization engine that provides a 10 percent performance improvement; and interoperability with GNU tools, enabling optimal compilation of Embedded Linux applications and optional integration with Eclipse. RealView Development Suite 3.0 Service Pack 1 provides a consolidation of enhancements since the original RealView Development Suite 3.0 release, including preliminary support for Cortex-R4, improved compilation times and DWARF3 debug data sizes, an expanded SIMD NEON assembler with Programmer’s notation, an improved user interface that debugs a multi-processor MPCore target, and expanded CortexM3 examples. The following components and abilities are offered by the RealView Development Suite: • Integrated Development Environment (IDE) • A choice of IDEs • RealView Development Suite can be integrated with the Industry-standard Eclipse IDE through a plug-in or CodeWarrior v5.7 IDE The compilation tools in RealView Development Suite are recognized by the industry for providing the best performance of all available ARM-processor targeted compilers. Developed and tuned to deliver the tightest code density, the compilers produce significantly smaller executables than other leading tool suites. The compilers generate optimized code for the 32-bit ARM and 16-bit Thumb and Thumb-2 instruction sets and support full ISO standard C and C++.

Debug Tools
Designed from the ground up to support complex single- and multi-core SoC software development with Embedded OS, the debugger in RealView Development Suite sets the standard for creating and debugging deeply embedded applications. No other debug environment provides interconnectivity with both the RealView CREATE world of system-level modeling and the RealView DEVELOP world of software development.

Add-om Options
The following are available as add-on options to the RealView Development Suite: • RealView SoC Designer • RealView ICE and RealView Trace • Real-Time System Model (RTSM) for ARM1176JZ(F)-S • Eclipse IDE plug-in • Plug-ins for popular DSP support

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Supported Platforms:
• Windows 2000, XP Professional • Red Hat Enterprise Linux 3 and 4 • SPARC Solaris 9 and 10

RealView ICE
RealView ICE is ARM’s leading-edge JTAG run control hardware unit, delivering the high performance required by today’s developers working with sophisticated System-on-Chip (SoC) devices and large software images. RealView ICE provides a universal-ARM solution, i.e., one unit supports all ARM CPUs in single, multi-core, homogenous, and heterogeneous architectures, offering an unparalleled depth and breadth of support for ARM processor-based devices. RealView ICE is an essential tool in an ARM system debug environment for connection and access to devices that contain the EmbeddedICE® logic, Embedded Trace Macrocell™ (ETM™), and Embedded Trace Buffer(ETB™) components for on-chip trace data storage. The unit has the ability to be expanded with additional modules for extended functionality, such as RealView Trace for trace data capture. The recently released RealView ICE version 3.0 now enables customers to connect to the new ARM Cortex family of processors and devices containing the new CoreSight™ advanced debug and trace technology. RealView ICE and Trace fully complement the RealView Development Suite in providing best-in-class integrated tools for hardware/software co-development of optimized ASIC, SoC, and FPGA-based systems.

• Support for variable JTAG clock frequencies, 2 kHz to 20 MHz (standard cable) or 50 MHz (LVDS cable) • Very low JTAG clock frequencies (sub-1 kHz) support ASIC-emulation environments • Wide target-voltage support, from 1.0V to 5.0V • Tightly coupled, synchronized multi-core control • ETM trace data capture with plug-in RealView Trace module • ETB trace data access via the JTAG port • Debug using GDB and KGDB capability • USB 1.1 and 2.0 compatible connection (Windows platform only) • Ethernet 10/100baseT remote and local host connection

Supported ARM Processors:
RVI-Supported cores include the following ARM processorbased families: ARM7™, ARM9™, ARM9E™, ARM10™, ARM11™, and Cortex™

RealView Trace
RealView Trace interfaces with ARM on-chip trace data storage Embedded Trace Macrocell (ETM™) components for the ARM7™, ARM9™, ARM9E™, ARM10™, and ARM11™ core families, and in conjunction with RealView Debugger. RealView Trace provides non-intrusive real-time tracing of instructions, data and profiling for performance analysis. It’s an optional add-on expansion module for RealView ICE.

Main Features
• Non-intrusive real-time tracing of instructions and data up to 250 MHz trace clock • Up to eight million frames deep trace buffer (up to four million frame deep buffer with time stamps) • 4-/8-/16-bit data width trace port • Trigger synchronization with external events • Fully variable trigger position • Fast on-the-fly trace data upload • Shares RealView ICE connection to the host computer • ETM trace ports modes supported – ETM protocols v1.x, v2.x, v3.x for ETM7TM, ETM9TM, ETM10TM, and ETM11TM – Single and doubled-edged clocking – Normal and multiplexed ports • Time stamp (48-bit) 10 ns resolution with 32-day duration

Other New Features
• JTAG run control for the new Cortex™-A8 and Cortex-M3 processors • CoreSight DK11 run control support for the ARM1136, ARM1156, and ARM1176 processors • TrustZone® secure and non-secure code views for the Cortex-A8 and ARM1176 processors RealView ICE can be connected to most types of host platforms by Ethernet for extended and remote connection, or locally by USB, to provide the optimum debug coupling and performance with the RealView Debugger.

Main Features
• High-performance debug control • Code download up to 1300 KBytes/sec with the RealView Debugger • High-speed single-stepping; up to 100 steps/sec • JTAG Debug Communications Channel (DCC) support Platforms supported are Windows 2000 and XP Note: Cannot be used standalone. This product is designed to be used in conjunction with a RealView ICE

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