“reg” Field Bit Assignments

:
16-Bit (w=1) 000 AX 001 CX 010 DX 011 BX 100 SP 101 BP 110 SI 111 DI 8-Bit (w=0) 000 AL 001 CL 010 DL 011 BL 100 AH 101 CH 110 DH 111 BH Segment 00 01 10 11 ES CS SS DS

MOV – MOVE (BYTE OR WORD) Direction:
D=0 D=1 SRC=REG DST=REG Operation Flags Affected Description (DEST) (SRC) None MOV destination, source MOVE transfers a byte or a word from the source operand to the destination operand. Encoding

Word:
W=0 W=1 8-Bit 16-Bit

mod reg r/m

“mod” Field Bit Assignments:
mod Displacement 00 DISP = 0*, disp-low and disp-high are absent 01 DISP = disp-low sign-extended to 16-bits, disp-high is absent 10 DISP = disp-high:disp-low 11 r/m is treated as “reg” field DISP follows 2nd byte of instruction (before data if required). *except if mod = 00 and r/m = 110 then EA = disp-high:disp-low

Memory or Register Operand to/from Register Operand 1 0 0 0 1 0 d w mod reg r/m data low If d = 1 then SRC = EA, DEST = REG, else SRC = REG, DEST = EA. Immediate Operand to Memory or Register Operand 1 1 0 0 0 1 1 w mod 0 0 0 r/m SRC = data, DEST = EA. Immediate Operand to Register 1 0 1 1 w reg SRC = data, DEST = REG.

data high

Data

data if w=1

data

data if w=1

“r/m” Field Bit Assignments:
r/m 000 001 010 011 100 101 110 111 Operand Address (BX) + (SI) + DISP (BX) + (DI) + DISP (BP) + (SI) + DISP (BP) + (DI) + DISP (SI) + DISP (DI) + DISP (BP) + DISP (BX) + DISP

Memory Operand to Accumulator 1 0 1 0 0 0 0 w addr-low addr-high If w = 0 then SRC = addr, DEST = AL, else SRC = addr + 1:addr, DEST = AX. Accumulator to Memory Operand 1 0 1 0 0 0 1 w addr-low addr-high If w = 0 then SRC = AL, DEST = addr, else SRC = AX, DEST = addr + 1:addr. Memory or Register Operand to/from Segment Register 1 0 0 0 1 1 d 0 mod 0 reg r/m d must be set such that segment register is encoded by 2-bit reg field. CS cannot be DST. Clocks 6 5 9 7 8 11 12 MOV Operands memory, accumulator accumulator, memory register, register register, memory memory, register register, immediate memory, immediate seg-reg, reg16 seg-reg, mem16 reg16, seg-reg memory, seg-reg Clocks 10 10 2 8 + EA 9 + EA 4 10 + EA 2 8 + EA 2 9 + EA Transfers 1 1 1 1 1 1 1 Bytes 3 3 2 2-4 2-4 2-3 3-6 2 2-4 2 2-4 MOV Coding Example MOV ARRAY, AL MOV AX, TEMP_RESULT MOV AX, CX MOV BP, STACK_TOP MOV COUNT[DI], CX MOV CL, 2 MOV MASK[BX][SI], 2CH MOV ES, CX MOV DS, SEGMENT_BASE MOV BP, SS MOV [BX]SEG_SAVE,CS

Table 3-14 Effective Address Calculation Time
EA Components Displacement Only Base or Index Only (BX,BP,SI,DI) Disp + Base or Index (BX,BP,SI,DI) + DISP BP + DI, BX + SI Base + Index BP + SI, BX + DI BP + DI + DISP BX + SI + DISP Disp + Base + Index BP + SI + DISP BX + DI + DISP

ADD – ADDITION
Operation Flags Affected Description (DEST) (LSRC) + (RSRC)

DEC – DECREMENT
Operation Flags Affected Description (DEST) (DEST) – 1 AF, OF, PF, SF, ZF DEC (Decrement) subtracts one from the destination operand. The operand may be a byte or a word and is treated as an unsigned binary number (see AA and DAA). DEC updates AF, OF, PF, SF and ZF; it does not affect CF.

AF, CF, OF, PF, SF, ZF ADD destination, source The sum of the two operands, which may be bytes or words, replaces the destination operand. Both operands may be signed or unsigned binary numbers (see AAA and DAA). ADD updates AF, CF, OF, PF, SF and ZF.

Encoding Memory or Register Operand with Register Operand
0 0 0 0 0 0 d w mod reg r/m data low data high

Encoding 8-bit Register or Memory
1 1 1 1 1 1 1 w mod 0 0 1 r/m

If d=1 then LSRC = REG, RSRC = EA, DEST = REG, else LSRC = EA, RSRC = REG, DEST = EA. Immediate Operand to Memory or Register Operand
1 0 0 0 0 0 s w mod 0 0 0 r/m data data if w=1

DEST = EA. 16-bit Register Operand
0 1 0 0 1 reg

LSRC = EA, RSRC = data, DEST = EA. Immediate Operand to Accumulator
0 0 0 0 0 1 0 w data data if w=1

DEST = REG. DEC Operands reg16 reg8 memory Clocks 3 3 15 + EA Transfers 2 Bytes 1 2 2-4 ADD Coding Example DEC AX DEC AL DEC ARRAY[SI]

If w=0 then LSRC = AL, RSRC = data, DEST = AL, else LSRC = AX, RSRC = data, DEST = AX. ADD Operands register,register register,memory memory,register register,immediate memory,immediate accumulator,immediate Clocks 3 9 + EA 16 + EA 4 17 + EA 4 Transfers 1 2 2 Bytes 2 2-4 2-4 3-4 3-6 2-3 ADD Coding Example ADD CX, DX ADD ADD ADD ADD MOV DI, [BX]ALPHA TEMP, CL CL,2 ALPHA,2 AX, 200

JNE – JUMP ON NOT EQUAL / JNZ – JUMP ON NOT ZERO
Operation Flags Affected Description If (ZF) = 0 then (IP) none (IP) + disp (sign extended to 16-bits)

JNE (Jump on Not Equal to)/JNZ (Jump on Not Zero) transfers control to the target operand (IP + displacement) if the condition tested (ZF = 0) is true.

Encoding
0 1 1 1 0 1 0 1 Disp

JNE/JNZ Operands Short-label

Clocks 16 or 4

Transfers -

Bytes 2

ADD Coding Example JNE NOT_EQUAL