High Performance High Capacity Emulation Systems

















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m e nto r. enabling complete functional verification of today’s complex system-on-chip (SoC) designs. highestcapacity emulation platform on the market. It provides visibility of all nodes at all times. which enables hundreds of global users to simultaneously run verifications remotely on the same machine. The Veloce2 architecture introduces the VirtuaLAB environment. around-the-clock resource for the entire company.Veloce2 Emulation Systems NEXT GENERATION VELOCE2 EMULATION PLATFORM WITH VIRTUALAB CAPABILITIES Mentor Graphics Veloce®2 is the best-in-class. rather than a localized piece of lab equipment accessible to only a single user at a single location. Veloce2 is the best platform for pre-and-post-silicon debug. This makes Veloce2 a globally-accessible. and fast turnarounds. Veloce2 has a scalable capacity from 16 million to 2 billion gates. enabling it to handle a wide range of design sizes and the most advanced verification tasks and methodologies. Its custom emulationon-chip technology delivers highly-reliable compiles. superior throughput. co m 2 . ■ Advanced methodology-based verification ■ IP and system-level verification in a targeted application environment ■ Software and firmware verification ■ Power analysis and power island verification ■ Assertion-based verification and coverage collection Veloce2 Quattro High-Performance Total Verification Platform w w w. simulation-like interactive debug.

multimedia.A Billion Gate Emulator w w w. co m 3 . high-performance virtual lab environment that is reproducible. and readily available for sharing between multiple verification teams. including SATA. holding 64 logic boards ■ Veloce2 Double Maximus – 2 billion gate system. Veloce2 doubles the capacity and performance of Veloce. so customers protect their investment when their designs require a larger chassis or additional logic boards. and Ethernet. expandable. Veloce and Veloce2 run with common software and have the same user interface. Distinct hardware chassis accommodate the verification needs of various design sizes. holding 16 logic boards ■ Veloce2 Maximus – 1 billion gate system. enabling a seamless transition from Veloce to Veloce2.Veloce2 Emulation Systems VELOCE2 HIGHLIGHTS SCALABLE CAPACITY UP TO TWO BILLION GATES Veloce2 is built on the proven hardware and software architecture of the Veloce family. USB. ■ Veloce2 Quattro – 256 million gate system. delivering four times the productivity in the same footprint and with the same power consumption. Veloce2 Maximus . All Veloce2 chassis use the same logic boards. m e nto r. It delivers multiple application solutions for the verification of complex SoC designs with multiple chip interfaces. PCIe. holding 128 logic boards VIRTUALAB ENVIRONMENT VirtuaLAB creates a non-intrusive.

7 days-a-week to worldwide design and verification teams. IP Replay is a unique feature that enables SoC designers to isolate a problem in third-party IP — without having to emulate the entire design or stimulus setup — reproduce the problem in a standalone environment. and waveform capture. trackers. Veloce2 supports powerful debug features like RTL line break pointing. single-stepping the RTL source. The Veloce2 Check Point feature allows users to move directly to the failure point instead of starting the test from the beginning. as is necessary with traditional in-circuit emulation (ICE). ADVANCED DEBUG The Veloce2 simulation-like debug environment eliminates the learning curve for new emulation users. emulation runs. RTL source-level value annotation. co m environment to the IP vendor. ENTERPRISE-STYLE EMULATION Veloce2 offers an enterprise-style verification environment to hundreds of verification engineers globally. The IP provider can then run the same database on their Veloce2 emulator. instead of a limited group of emulation experts. high-throughput co-model channels enable faster communication between the DUT and testbench. Once the IP is modified. Verification engineers and software developers are not required to know the details of the emulation system in order to complete activities such as compile. IP Replay enables the IP provider to validate that the fix truly resolved the issue within the target environment before the corrected IP is sent back to the user. and then send that w w w. Through the Mentor Graphics industry-leading co-modeling technology. Veloce2 IP Replay Flow 4 . In a scenario where the verification environment is testbench dominated. Multiple. advanced techniques beyond the traditional simulation style debug. Veloce2 delivers unique. m e nto r. visibility into all design nodes all the time. quickly reproducing the problem and debugging it in their IP. and schematic and path browsing views for interactive debug. Additionally. such as assertions. For these users. The Veloce2 Backup Replay feature enables users to rewind and rerun a test with added debug visibility. Veloce2 is available 24 hours. $display. memory/ register peek-and-poke. such as IP Replay and Backup Replay. This feature is very powerful for an environment exhibiting nondeterministic behavior because it repeats exactly the same sequence of stimulus as the original run. Veloce2 is a fast compute-farm residing in a data center accessed via industry-standard queuing software very much like accessing a Linux server on a network. increasing verification productivity and significantly reducing verification time compared to software simulation. the Backup Replay feature provides a huge boost in time-to-visibility. This allows engineers to run regressions at full emulation speed and then re-run the failed tests with added debug visibility from the nearest time point of the failure. this feature potentially saves hours or days in IP or SoC verification. For long emulation runs. Consequently. and debug. as testbench execution is not required for replay sessions. a “virtual device” running on a workstation is connected to the user’s design-under-test (DUT) executing in Veloce2.Veloce2 Emulation Systems VirtuaLAB eliminates the need to connect external hardware peripherals to a Veloce2 emulator. monitors.

power. physical. Veloce2 supports the use of software or hardware based stimuli or a mix of both. and. users can add even more capacity to a single Veloce2 chassis by simply adding more logic boards. they typically focus on the cost of the emulator and overlook the cost of ownership. However. floor space. SystemVerilog. Veloce2 significantly reduces development schedule risks while leveraging the transaction models used during simulation. IP and chip-level verification. or a combination of all of these. as the entire capacity is housed within a single chassis—instead of connecting multiple modules using hundreds of cables. Additionally. This saves a lot of engineering time and money by not requiring maintenance of different platforms for different verification needs over the life span of an SoC. Veloce2 has efficient data packing. Veloce2 can be used for block-level simulation acceleration. and cooling are collectively very expensive overheads. C++. Veloce2 accelerates testbench environment development using C. the Universal Verification Methodology (UVM). The Veloce2 setup is highly reliable. which can be used for a single design or shared among many designs running simultaneously. w w w. m e nto r. software and driver validation. Veloce2 is the only hardware platform addressing the complete verification cycle for an SoC. finally. system-level validation. SystemC. buffering. Veloce2 requires four times less floor space and three times less power and cooling compared to equivalent systems on the market. COST OF OWNERSHIP When customers buy an emulation system. Additionally. Thus. Veloce2 accelerates an existing simulation environment by many thousands of times the speed 5 . allowing users to choose the most suitable stimulus for a given interface or application. co-model links for design verification environments that require larger communication bandwidths between the testbench and the design. By accelerating both block-level and full SoC regression tests.Veloce2 Emulation Systems Veloce2 Advanced Debug Using Backup Replay UNLIMITED THROUGHPUT Veloce2 increases communication bandwidth by accommodating multiple. TESTBENCH ACCELERATION Using the TestBench Xpress (TBX™) technology. Veloce2 provides hundreds of communication links. often comparable to the cost of the emulator itself. and dispatching mechanisms to ensure the best utilization of the available bandwidth for a given co-model channel. as emulation needs grow. co m USE MODES Veloce2 provides flexibility by supporting several verification use modes.

$finish. users can avoid the development costs associated with creating complex testbenches for a specific protocol and use real stimulus to exercise their design.Veloce2 Emulation Systems of software simulators. SAS. virtual interfaces. either by using standard. leading to additional acceleration over normal simulation runs. networking. and $random are some examples of behavioral constructs that are accelerated by TBX. virtual interface. these can be used in pre-and-post silicon verification. $readmemh. behavioral clock modeling. Veloce2 Accelerated Modern Verification Environment Flow w w w. This creates a powerful environment for generating billions of cycles of test data to exercise the DUT and then analyze the activity in the Veloce2 debug environment. $display. or SystemVerilog environment on a host PC and the SoC DUT in a Veloce2 emulator. multimedia video/audio. such as USB. along with the user design The transaction-level communications between testbenches running on a host PC and an SoC modeled in Veloce2 is based upon SCE-MI standards. IN-CIRCUIT EMULATION In-circuit emulation (ICE) allows customers to connect real-world stimulus to their target applications. SystemC. The acceleration mainly comes from two technologies: ■ Infrequent. information-rich. Typical ICE applications available to users are wireless. By synthesizing and mapping these constructs into Veloce2 hardware. for/while loops. Veloce2 speeds transactor modeling by using the most commonly used SystemVerilog behavioral constructs for ease-of-modeling. In this way. Such verification capabilities enable true. and other industry-standard bus protocols. hardwaresoftware concurrent verification and reduce risks of errors in designs. m e nto r. and SATA. SystemVerilog DPI import/export tasks and transaction pipes. $final. transaction-level communication between testbench and DUT ■ Advanced compiler technology for synthesizing and mapping more of the testbench into Veloce2 hardware. TBX automatically generates a direct communication interface between the C/C++. adding to the return on investment of the Veloce2 platform. PCI express. TBX accelerates part of the testbench environment. Additionally. off-the-shelf solutions from Mentor (called “iSolve™ solutions”) or by connecting their own application-specific target boards to the Veloce2 emulator. The SystemVerilog interface. implicit state machines. co m 6 . and TLM FIFOs are the primary transaction modeling constructs of TBX.

Lauterbach probes.Veloce2 Emulation Systems standard JTAG debug signals from the emulated processor core and maps them to physical signals. ultimately delivering them to the standard JTAG debug interface. Codelink provides a traditional software debugger view of the activity on a processor — but after the emulation has completed. Veloce2 virtual probes perfectly complement the VirtuaLAB concept. Through a TBX interface. This eliminates the need to bring signals to an I/O board. and eliminates the physical probe itself. This allows interactions with the design—both hardware and software— while observing the state of the complete system through the Veloce GUI and the software debugger. For batch-oriented software debug. the Codelink replay server acts as a virtual debug target. Veloce2 allows traditional physical JTAG probes to be attached to a design running in the emulator through the iSolveTM JTAG solution. The emulation can complete and the emulator can move on to other jobs while software debug takes place off line. enabling complete state reconstruction to take place after emulation is completed. It also delivers debug visibility into what’s happening on the processor cores in the design in two ways: interactively through a debug probe and off-line using Veloce®Codelink™. This solution works well with emulation runs that are done in batch or executed off an LSF queue. Yet it delivers all the functionality of a physical debug probe connection to the target. This gives the 7 Typical ICE Setup SOFTWARE VALIDATION Software is an integral part of the functionality of an SoC. During emulation. After emulation. iSolve JTAG brings the w w w. This can be connected to any popular JTAG debug probes (including the Mentor Embedded Sourcery Probes (MESP™). Veloce2 delivers the raw performance needed for software execution. enabling all connected devices — including debug connections — to be controlled and synchronized through the TBX interface. the full functionality of the debug probe can be embodied in a transactor. and others) for interactive debug with one or more processors in the design. so it is important to validate and debug the software in the context of the SoC before tape out. Debug probes use the debug facilities on the processor core to gain control of the core and perform debug operations. co m . Veloce2 integrates with Veloce’s Codelink solution. ARM’s DSTREAM™. m e nto r. Codelink logs activity in and around the processor. Veloce2 also enables a “virtual” probe to be used to connect to the processor cores in the design. Debug probes are usually based on industry standards like JTAG. eliminates clock synchronization and speed bridges to the target system.

breakpoints can be set at any location in the program. collect coverage data. Veloce2 delivers full software debug visibility for designs that contain processor cores. Codelink enables cross visibility into hardware trace views in the Veloce GUI. intelligent checking 8 w w w. This enables a breakpoint to be set on a failure condition from which the software developer can step backward to easily discover the cause of the failure. Veloce2 allows verification engineers to retain simulator verification capabilities — including modern Low Power Management Verification Using Veloce2 – Object-oriented modeling. Since an unchanged testbench runs on the simulator. and verify power-related functionalities. Veloce2 testbench acceleration is designed to accelerate UVM/OVM based verification environments by keeping testbench components and the DUT unchanged. Highlights of advanced methodology acceleration using Veloce2: ■ Enables a single-sourced testbench for simulation and acceleration ■ Leverages power of SystemVerilog and OVM/ UVM testbench features: METHODOLOGIES The Veloce2 architecture natively extends support to modern verification methodologies used to develop intelligent. The replay server allows the program to be run forward or backwards. Veloce2 delivers the broadest set of software execution and debug capabilities to emulated designs. They can view source code.Veloce2 Emulation Systems software developer a complete software debugger view of the activity of the processor at any point in emulation. There are clear guidelines to establish transaction-based communication between a testbench running on a host PC (simulator) and a DUT executing in Veloce2. memory. while accelerating them using hardware assisted verification. constrained-random generation. single source environment for acceleration and simulation. variables. and the call stack. reusable verification components and testbenches. Typically communication is through simple function calls based on IEEE 1800 SystemVerilog DPI or TLM FIFO. coverage-driven. Whether interactive or batch. They can also minimize the changes required for acceleration and maintain interoperability between simulation and acceleration. These fit seamlessly into current verification flows and fulfill today’s needs when other tools reach their limits in capacity and performance. users can leverage simulator debug and controllability. and assertionbased techniques — as well as prevalent verification methodologies — such as the Universal Verification Methodology (UVM). UVM The UVM and OVM advanced verification methodologies empower verification at a high level of abstraction by virtue of modular. co m . reusable testbenches. constrained-random. along with associated simulator capabilities for analysis and debug. coverage-driven verification. the Veloce2 acceleration environment is truly interoperable with software simulation and enables a true. or through transaction pipes based on Accellera SCE-MI standards. m e nto r. Users can preserve the benefits of using these verification methodologies. registers. Being fully standardscompliant. through a virtual interface.

Simulation and other verification tools can help handle these tests at the block level by using directed unit level tests but fall short for system-level verification and applications needing long sequences. LOW POWER VERIFICATION As node geometry shrinks. users can validate domain power on/off often and quickly to mimic real-world behavior. Just like assertions. This requires 9 .Veloce2 Emulation Systems – TLM interfaces. Veloce2 supports key aspects of low power verification: ■ Power ON/OFF a domain ■ Validation of isolation logic ■ Validation of retention schemes ■ Mimic corruption scenarios ■ Voltage level shifter functionality POWER ANALYSIS To avoid over or under specification of an SoC and to design an efficient battery. Veloce2 generates a report capturing every assertion firing for post-process debug. configuration. Because Veloce2 can execute long tests very quickly. factory. or QVL verification languages. Users are free to use various operations using assertions — such as send a message to a testbench when an assertion fires — or write a trigger or event to capture a particular state in their designs. Veloce2 automatically implements dynamic checks for monitoring low power functionality and alerts users when there is an unexpected behavior. involving both software and hardware. while the control logic itself resides in the hardware. co m long initialization sequences. making the environment interoperable with other tools and platforms. The Veloce2 low power functionality is based on the IEEE P1801 Unified Power Format (UPF) standard. Coverage is logged to a coverage database for offline analysis. maps them inside the hardware. it is very important to know the realistic average and peak power consumptions. and accelerates them at the same speed as design RTL. This aspect can be verified only at the systemlevel by running real applications. Veloce2 also provides compile and run time controllability to enable or disable assertions to perform targeted verification. such as OS boot. The majority of designers and verification users today implement assertions and coverage to catch unexpected scenarios and to observe verification coverage in order to make educated tape out decisions. Designers need to run long tests to be sure actual power peaks are captured. SoC designers also want to characterize how much retention logic they should incorporate to bring a particular functionality to life within a given time range. level shifters. helping designers decide whether to put more retention logic or accommodate a longer wakeup time. power becomes a significant concern for chip designers. sequences ■ Unobtrusive to established verification best practices: – SystemVerilog testbench acceleration guidelines largely complement verification methodology features and guidelines ASSERTION AND COVERAGE DRIVEN VERIFICATION The use of assertions and coverage are an integral part of today’s verification process. merging with coverage collected from other tests or platforms for generating global statistics. coverage constructs are synthesized by the Veloce2 compiler and mapped in the hardware to run at full emulation speeds. Low power techniques used today include power domain off/on. PSL. Veloce2 synthesizes assertions written in SVA. The actual power value can only be determined by applying application-specific stimuli instead of a fabricated stimulus. and so on. phasing. Some applications have w w w. There are various ways to reduce power consumption in order to increase the life span and reduce the size of a battery. Veloce2 complements and extends the verification task from the point where simulators run out of performance. that must occur before a domain can be powered on or off. it is critical to verify the low power management aspects at the system level. m e nto r. clock gating. Because the power ON/OFF controls come from application-level software. OVL.

They can make some performance adjustments or make appropriate cooling arrangements. designers can generate FSDB data for detailed power analysis. m e nto r. many are built using standard memories. and I/O interfaces. and select an optimal die size for the SoC. ISOLVE . high-performance SoC verification environments. While every SoC is different. VELOCE EMULATION SOLUTIONS Veloce provides flexible options when it comes to stimulating a given interface. Once the peak switching areas have been identified. processors. This helps them understand whether the power rails in their design can sustain and carry power for the duration of the peak power without overheating. software debug.PHYSICAL DEVICE SOLUTIONS The iSolve family of specialized software and hardware sub-systems addresses the SoC modeling and realworld testing requirements that are necessary to quickly build complete. multimedia data streaming and analysis. buses.Veloce2 Emulation Systems Power Analysis Using Veloce2 running real applications and long sequences to avoid making wrong assumptions about power consumption. Users can identify what areas of the chip or which application is causing power peaks and take appropriate actions before fabricating the chip. w w w. Veloce2 draws a histogram showing switching activity over long emulation runs (billion cycles) to help designers identify real peak switching areas. co m 10 . and industry-standard bus and communication interfaces. Veloce2 enables average power calculations over hundreds of million cycles. The Veloce2 power analysis capability addresses all of the above concerns. ARM embedded processors. iSolve Application Solutions provide complementary solutions for Veloce2 systems in the areas of memory modeling. instead of making a software workaround afterward.

monitors. VIP can be used in various HVL testbench environments. and system-level verification. VIP delivers acceleratable solutions that run up to 10. block to system level accelerated verification flow. Virtualization makes emulation more readily available to all design teams and increases the flexibility. and scoreboarding capabilities used with the OVM/UVM standards. significantly reducing verification times and regression testing for increased productivity. delivering a scalable verification solution for popular protocols and standard interfaces that can be used for RTL. A Virtual Device Package VELOCE VIRTUALAB SOLUTIONS In combination with Veloce2 and the TBX co-modeling technology. and deliver the stimulus generators. visibility. users can integrate VirtuaLAB solutions into an environment using OVM/UVM for testbench protocol interfaces and Mentor Verification IP. Connected directly to a highperformance emulation environment. Thus. VirtuaLAB solutions offer the same functionality as traditional In-Circuit (ICE) solutions but without the need for additional cables and hardware units. VIP is easy and convenient to use. and capacity of emulation environments while increasing verification productivity and design quality. including SystemC and SystemVerilog. By using a TBX co-model link to package a software stack running on a co-model host workstation with communication protocol IP running on Veloce2. reducing overall testbench development time and completing more verification with less effort. users of VirtuaLAB can verify their IP at the device driver level and verify the DUT with realistic software. ■ Easier and more flexible remote usage because the solution can be installed with no additional hardware connected to Veloce2 ■ Greater flexibility for sharing a single Veloce2 resource among multiple design teams because there are no cables to connect and there are fewer partition constraints on the DUT running in the emulator ■ Visibility over the target protocol software stack running on the function controller can be defined without the constraint of a specific access mechanism into the dedicated hardware ■ Visibility/traceability over the target protocol function controller core can be defined in terms of simple IP protection for the delivered RTL source code ■ Access to standard buses is readily available for monitors and checkers A Veloce Standard Bus Protocol Transactor Module w w w. VirtuaLAB offers the following additional advantages.000 times the speed of pure software simulation. VERIFICATION IP Verification IP (VIP) apply the appropriate stimulus for the SoC executing in Veloce2. m e nto r. co m 11 . TLM.Veloce2 Emulation Systems Because the VirtuaLAB flow supports SystemC and SystemVerilog with both Veloce2 and Questa. Mentor Graphics Veloce VirtuaLAB solutions deliver a fully virtual.

This document contains information that is proprietary to Mentor Graphics Corporation and may be duplicated in whole or in part by the original recipient for internal business purposes only. m e n t o r . OVL. QVL Fast Compile Up to 40 MG per hour Asynchronous Clocks Clocks can be supplied using function generators or external PLLs OS Support Power RH 4 & 5. TLM. gate-level netlist. SystemVerilog UVM. SystemVerilog. VHDL. all rights reserved. SystemC. C++.Veloce2 Emulation Systems PRODUCT SPECIFICATIONS Capacity Number of Users Design Languages Testbench Languages Methodologies Up to 2 billion gates Up to 128 Verilog. MGC 10-13 TECH11520-w . and encrypted IP C. PSL. c o m ©2013 Mentor Graphics Corporation. All trademarks mentioned in this document are the trademarks of their respective owners. the recipient agrees to make every reasonable effort to prevent unauthorized use of this information. SUSE 10 & 11 11 KW for Veloce2 Quattro (for a fully-loaded system) For the latest product information. call us or visit: w w w . VMM Assertion Languages SVA. provided that this entire notice appears in all copies. In accepting this document. OVM.