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Execution Models for VHDL Programs

• Two classes of execution models govern the application of VHDL
programs
• Simulation
• discrete event simulation
• understanding is invaluable in debugging programs
• Synthesis
• inference of hardware
• a function of the building blocks used for implementation

Simulation vs. Synthesis
entity my_ckt is
port(x , y :in bit;
z : out bit)
end entity my_ckt;
architecture behavioral of
my_ckt is synthesis
begin
-- some code here
--
end architecture behavioral;

entity my_ckt is
port (x, y :in bit;
z : out bit)
end entity my_ckt; simulation
architecture behavioral of
my_ckt is
begin
-- some code here
--
end architecture behavioral;

• Simulation and synthesis are complementary processes
Simulation of Digital Systems
1
0
@5 ns

@15 ns

0

@10 ns
Head
0→1 1→0 0→1
@15ns @10ns @5ns
Event List

• Digital systems propagate events
• Discrete event simulations manage the generation and recording of events

Discrete Event Simulation: An Example
Event

a

b

sum

carry

5 10 15 20 25 30 35 40
Time (ns)

a
sum
b

carry
Discrete Event Simulation: Data Structures:
simulator clock 5 ns

U →1 U→0 1→ 0
carry@5ns sum@5ns a@5ns

5 ns

0→1 1→ 0 0→1 1→ 0
sum@10ns carry@10ns a@10ns b@10ns

10 ns

1→ 0
a@15ns

• Management of simulation time: ordering of events
• Two step model of the progression of time

Simulation Modeling
HDL
Description

Discrete event
simulator

Altera, Viewlogic, Xilinx

• VHDL programs describe the generation of events in digital
systems
• Discrete event simulator manages event ordering and
progression of time
• Now we can quantitatively understand accuracy vs. time trade-
offs
Synthesis and Hardware Inference
HDL
Description

Designer

Synthesis
Compiler

• Both processes can produce very different results!

Inferring Combinational Logic
--
-- pseudo code for a single bit arithmetic/
logic unit
--
s1 <= in1 and in2;
s2 <= in1 or in2;
s3 <= in1 xor in2; -- perform the sum opera-
tion
c_out <= (in1 and c_in) or (in1 and in2)
or (in2 and c_in);
out <= s1 when sel = “00” else
s2 when sel = “01” else
s3 when sel = “10” else
‘0’;

• Each statement implies a logic component
Inferring Sequential Logic
--
-- a simple conditional code block
--
if (sel = ‘0’) then
z <= in1 nor in2;
end if;

• Inference of sequential components is more subtle
• Results are very sensitive to the manner in which code is written
• Inferences of latches vs. flip flops

Target Primitives
A
A
B B
C C
B B
C
C

D
B
B C

A

C

D

B

B

ABC + BC + DB

• The resulting circuit depends on the available building blocks
Field Programmable Gate Arrays: Principles
C LB C LB C LB

C LB C LB C LB

C LB C LB C LB

• The chip is tiled with Configurable Logic Blocks (CLBs)
• each block can “implement” a few gates and flip flops
• A switching matrix is interleaved with this array of CLBs
• Usage: partition, place, and route a design

Inside a Configurable Logic Block (CLB)
C1 • • • C4
4

H1 DIN /H2 SR/H0 EC

G4 Logic
S/R
Function Control Bypass
of G1 –G4
G3 D IN YQ
F´ SD
G´ G´
D Q
G2 H´

G1 Logic
Function of F,́
G´ EC
G,́ and H1 RD
H´ H´
1
Y

F4 Logic
Function
S/R
of F1 –F4 Control
F3 D IN XQ
F´ SD
D Q
F´ G´
F2 H´

F1

EC
RD
K
(CLOCK) 1

X

Multiplexer Controlled by
Configuration Program

• Combinational and sequential components
Inside a I/O Block (IOB)
Passive
Slew Rate Pull-Up/
Control Pull-Dwon

T

0 Output MUX

1 Flip-Flop
Output
Out D Q
Buffer
Pad
CE

Output Clock Input
Buffer

I1

Flip-Flop/
Latch
I2 Delay Delay
Q D

Q D

Fast Latch
Clock Enable CE
Capture
Latch G

Input Clock

• Pin multiplexing and distinct clocks

Implementing Combinational Logic in a CLB
A
B
O ut
C
D
• Boolean functions
implemented as look-up
tables
A
• Combinations of lookup
tables for multivariable
B
O ut
functions
• Implementation of behavior
• Sequential circuits use CLB
C
latches/flip flops
D
Wiring Resources

12 Quad

8 Single

4 Double

3 Long

Direct
CLB 2
Connect

3 Long

12 4 4 6 4 8 4 2

Quad Long Global Long Double Single Global Carry Direct
Clock Clock Chain Connect

• Optimize signal delay
• “Chip length” signals can be configured as buses
• Global nets for low skew clocks and reset signals

Specialized Resources
• Carry chains between columns of CLBs
• Configuration of CLB RAM as memories rather than lookup
tables
• Core generators
• optimized libraries of components
• vendor supplied
• What about editing the bit stream directly!
Chip Configuration (Xilinx)
• Configuration bits for CLBs
• bits for loading the LUTs
• bits for configuring the flip flops
• bits for setting multiplexors
• Configuration bits for the switch matrix
• connecting horizontal and vertical lines
• tristate devices within the CLBs
• Configuration bits for the IOBs
• IO clocks
• storage vs. direct “access” to the pin
• Equivalent concepts for all vendors

Design Flow
Model Development

HDL State Machine Schematic
Editor Editor Capture

Behavioral Simulation

Core Synthesis
Generation
Utilitites
Functional Simulation

Place and Route

Verification

Programming

Device Programming

• Design flow is a function of the target implementation, for
example, FPGAs
Summary
• Simulation Model
• discrete event execution model for VHDL programs
• accuracy vs. time
• Synthesis Model
• need for inference from language constructs
• basic principles behind the use of FPGAs
• challenges in the design flow