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CHAMELEON CHIPS INTRODUCTION Today's microprocessors sport a general p!rpose design "#ic# #as its o"n ad$antages and disad$antages%  Ad$& One c#ip can r!n a range o' programs% T#at's "#y yo! don't need separate comp!ters 'or di''erent (o)s* s!c# as cr!nc#ing spreads#eets or editing digital p#otos  Disad$& For any one application* m!c# o' t#e c#ip's circ!itry isn't needed* and t#e presence o' t#ose +"asted+ circ!its slo"s t#ings do"n% ,!ppose* instead* t#at t#e c#ip's circ!its co!ld )e tailored speci'ically 'or t#e pro)lem at #and say* comp!ter aided design and t#en re"ired* on t#e 'ly* "#en yo! loaded a ta- preparation program% One set o' c#ips* little )igger t#an a credit card* co!ld do almost anyt#ing* e$en c#anging into a "ireless p#one% T#e mar.et 'or s!c# $ersatile mar$els "o!ld )e #!ge* and "o!ld translate into lo"er costs 'or !sers% ,o comp!ter scientists are #atc#ing a no$el concept t#at co!ld increase n!m)er cr!nc#ing po"er and trim costs as "ell% Call it t#e c#ameleon c#ip% C#ameleon c#ips "o!ld )e an e-tension o' "#at can already )e done "it# 'ield programma)le gate arrays /FP0A,1% An FP0A is co$ered "it# a grid o' "ires% At eac# crosso$er* t#ere's a s"itc# t#at can )e semipermanently opened or closed )y sending it a special signal% 2s!ally t#e c#ip m!st 'irst )e inserted in a little )ot#at sends t#e programming signals% 3!t no"* la)s in E!rope* 4apan* and t#e 2%,% are de$eloping tec#ni5!es to re"ire FP0A li.e c#ips anytime and e$en so't"are t#at can map o!t circ!itry t#at's optimi6ed 'or speci'ic pro)lems% T#e c#ips still "on't c#ange colors% 3!t t#ey may "ell color t#e "ay "e !se comp!ters in years to come% it is a '!sion )et"een c!stom integrated circ!its and programma)le logic%in t#e case "#en "e are doing #ig#ly per'ormance oriented tas.s c!stom c#ips t#at do one or t"o t#ings spectac!larly rat#er t#an lot o' t#ings a$eragely is !sed% No" !sing 'ield programmed c#ips "e #a$e c#ips t#at can )e re"ired in an instant% T#!s t#e )ene'its o' c!stomi6ation can )e )ro!g#t to t#e mass mar.et% A recon'ig!ra)le processor is a microprocessor "it# erasa)le #ard"are t#at can re"ire itsel' dynamically% T#is allo"s t#e c#ip to adapt e''ecti$ely to t#e programming tas.s demanded )y t#e partic!lar so't"are t#ey are inter'acing "it# at any gi$en time% Ideally* t#e recon'ig!ra)le processor can trans'orm itsel' 'rom a $ideo c#ip to a central processing !nit /cp!1 to a grap#ics c#ip* 'or e-ample* all optimi6ed to allo" applications to r!n at t#e #ig#est possi)le speed% T#e ne" c#ips can )e called a "chip o !ema !." In practical terms* t#is a)ility can translate to immense 'le-i)ility in terms o' de$ice '!nctions% For e-ample* a single de$ice co!ld ser$e as )ot# a camera and a tape recorder /among n!mero!s ot#er possi)ilities1& yo! "o!ld simply do"nload t#e desired so't"are and t#e processor "o!ld recon'ig!re itsel' to optimi6e per'ormance 'or t#at '!nction% Recon'ig!ra)le processors* competing in t#e mar.et "it# traditional #ard "ired c#ips and se$eral types o' programma)le microprocessors% Programma)le c#ips #a$e )een in e-istence 'or o$er ten years% Digital signal processors /D,Ps1* 'or e-ample* are #ig# per'ormance programma)le c#ips !sed in cell p#ones* a!tomo)iles* and $ario!s types o' m!sic players% Anot#er $ersion* programma)le logic c#ips are e5!ipped "it# arrays o' memory cells t#at can )e programmed to per'orm #ard"are '!nctions !sing so't"are tools% T#ese are more 'le-i)le t#an t#e speciali6ed D,P c#ips )!t also slo"er and more e-pensi$e% Hard "ired c#ips are t#e oldest* c#eapest* and 'astest )!t also t#e least 'le-i)le o' all t#e options% Chame"eo chips Hig#ly 'le-i)le processors t#at can )e recon'ig!red remotely in t#e 'ield* C#ameleon's designed to simpli'y comm!nication system design "#ile deli$ering increased

c#ips

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protocols and data 'ormats% AD#ANTA$ES AND APPLICATIONS Its applications are in*  data intensi$e Internet  D.er t#an e$er% T#o!g# eac# o' t#ese goals is indi$id!ally attaina)le* t#e #at tric.8.e t#e one in yo!r PC* )!t t#at "o!ld )e slo" as "ell as e-pensi$e% For t#ese reasons* c#ip designers are t!rning increasingly to recon'ig!ra)le #ard"areBintegrated circ!its "#ere t#e arc#itect!re o' t#e internal logic elements can )e arranged and rearranged on t#e 'ly to 'it partic!lar applications% Designers o' m!ltimedia systems 'ace t#ree signi'icant c#allenges in today's !ltra competiti$e mar.com FREE TECHNICAL PAPER DOWNLOAD .Newtechpapers.ing t#em s!ita)le 'or #ig# end applications% /T#e densest o' t#e c!rrent FP0As #a$e appro-imately .1* >*::: .< )it million m!ltiply acc!m!lates per second /==AC.et and cell processing protocols Its a!%a ta&es are  can create c!stomi6ed comm!nications signal processors  increased per'ormance and c#annel co!nt  can more 5!ic.FREE TECHNICAL PAPER DOWNLOAD –www.::*::: reprogramma)le logic gates%1 Wit# an anticipated do!)ling o' gate densities e$ery .ly adapt to ne" re5!irements and standards  lo"er de$elopment costs and red!ce ris.C<:s )y a researc#er at 2CLA* recon'ig!ra)le comp!ting is a relati$ely ne" 'ield o' st!dy% T#e decades long delay #ad mostly to do "it# a lac.1* and pro$ide ?: c#annels o' CD=A8::: c#ip rate processing% T#e :%8? micron c#ip* t#e C.Newtechpapers.ind o' a c#ip is a c#ameleon c#ip%t#is can also )e called a @c#ip on demandA @Recon'ig!ra)le comp!ting goes a step )eyond programma)le c#ips in t#e matter o' 'le-i)ility% It is not only possi)le )!t relati$ely commonplace to +re"rite+ t#e silicon so t#at it can per'orm ne" '!nctions in a split second% Recon'ig!ra)le c#ips are simply t#e e-treme end o' programma)ility%A T#e o$erall per'ormance o' t#e AC= can s!rpass t#e D.P )eca!se t#e AC= only constr!cts t#e act!al #ard"are needed to e-ec!te t#e so't"are* "#ereas D.8 is an e-ample% T#ese ne" c#ips are a)le to re"ire t#emsel$es on t#e 'ly to create t#e e-act #ard"are needed to r!n a piece o' so't"are at t#e !tmost speed% an e-ample o' s!c# . is generally !nac#ie$a)le "it# traditional design and implementation tec#ni5!es% Fort!nately* some ne" tec#ni5!es are emerging 'rom t#e st!dy o' recon'ig!ra)le comp!ting t#at ma.L concentrators  'i-ed "ireless local loop  m!ltic#annel $oice compression  m!ltiprotocol pac..Ps and microprocessors 'orce t#e so't"are to 'it its gi$en arc#itect!re% One reason t#at t#is type o' $ersatility is not possi)le today is t#at #and#eld gadgets are typically )!ilt aro!nd #ig#ly optimi6ed specialty c#ips t#at do one t#ing really "ell% T#ese c#ips are 'ast and relati$ely c#eap* )!t t#eir circ!its are literally "ritten in stone or at least in silicon% A m!ltip!rpose gadget "o!ld #a$e to #a$e many speciali6ed c#ips a costly and cl!msy sol!tion% Alternately* yo! co!ld !se a general p!rpose microprocessor* li.–www.e 'ield programma)le gate arrays /FP0As1 #a$e )een aro!nd 'or many years* )!t t#ese c#ips #a$e only recently reac#ed gate densities ma.% -2.et 5!ic.etplace& O!r prod!cts m!st do more* cost less* and )e )ro!g#t to t#e mar. o' accepta)le recon'ig!ra)le #ard"are% Reprogramma)le logic c#ips li.< )it million operations per second /=OP.e it possi)le to design systems t#at satis'y all t#ree re5!irements sim!ltaneo!sly% Alt#o!g# originally proposed in t#e late .P  "ireless )asestations  $oice compression  so't"are de'ined radio  #ig# per'ormance em)edded telecom and datacom applications  -D.D mont#s* t#e sit!ation "ill only )ecome more 'a$ora)le 'rom t#is point 'or"ard% T#e primary prod!ct is a gro!ndstation e5!ipment 'or satellite comm!nications% T#is application in$ol$es #ig# rate comm!nications* signal processing* and a $ariety o' net"or.com price7per'ormance n!m)ers% T#e c#ameleon c#ip is a #ig# )and"idt# recon'ig!ra)le comm!nications processor /RCP1%it aims at c#anging a system's design 'rom a remote location% T#is "ill mean more $ersatile #and#elds% Processors operate at 89*::: .

s1% Deterministic so't"are is s!ited 'or controlling #ard"are% As s!c#* it can )e !sed to e''iciently manage t#e content o' system data and t#e 'lo" o' s!c# data 'rom a cp! to an FP0A% FP0A de$elopers can "or.ICsBt#ey can )e re"ired and reprogrammed at any time 'rom a remote location t#ro!g# so't"are% Alt#o!g# it too.Newtechpapers.et press!res* it is increasingly critical t#at all system le$el components )e easy to integrate* especially since t#e p#ase in$ol$ing t#e integration o' m!ltiple tec#nologies #as )ecome t#e most time cons!ming part o' a prod!ct's de$elopment cycle% To Integrating Hard"are and . into a plat'orm )ased approac# remo$es many o' t#e de$elopment )arriers t#at still limit t#e '!nctionality o' em)edded applications% De$elopment* pro'iling* and analysis tools are a$aila)le t#at can )e !sed to analy6e comp!tational #ot spots in code and to per'orm lo" le$el timing analysis in m!ltitas.?: )illion transistors* se$en times more t#an a Penti!m class microprocessor% 0i$en today's time to mar.s can per'orm t#e same #ig# speed #ard"are '!nctions as 'i-ed '!nction A. se$eral seconds or more to c#ange connections in t#e earliest FP0As* FP0As today can )e con'ig!red in milliseconds% Field programma)le gate arrays #a$e #istorically )een applied as "#at is called gl!e logic in em)edded systems* connecting de$ices "it# dissimilar )!s arc#itect!res% T#ey #a$e o'ten )een !sed to lin.e "it# ot#er integrated circ!its* de$elopers can alter )ot# t#e logic '!nctions per'ormed "it#in t#e )loc.s t#at are str!ng toget#er t#ro!g# so't"are commands to implement #ig#er order logic '!nctions% Logic )loc.ly identi'y '!nctionality t#at is 're5!ently !sed or comp!tationally intensi$e% .e ad$antage o' deterministic real time operating systems /RTO.com 'P$A One o' t#e most promising approac#es in t#e realm o' recon'ig!ra)le arc#itect!re is a tec#nology called +'ield programma)le gate arrays%+ T#e strategy is to )!ild !ni'orm arrays o' t#o!sands o' logic elements* eac# o' "#ic# can ta. can )e streamlined )y means o' an en#anced application programming inter'ace /API1% T#e )lending o' #ard"are* 'irm"are* application so't"are* and an RTO.o't"are systems designers prod!cing mi-ed cp! and FP0A designs can ta. digital signal processorsBcp!s !sed 'or digital signal processingBto general p!rpose cp!s% T#e gro"t# in FP0A tec#nology #as li'ted t#e arrays )eyond t#e simple role o' pro$iding gl!e logic% Wit# t#eir c!rrent capa)ilities* t#ey clearly no" can )e classed as system le$el components (!st li.–www. "it# RTO.s and t#e connections )et"een t#e )loc.!c# '!nctions may )e prime candidates 'or mo$ing 'rom so't"are to FP0A #ard"are% An integrated s!ite o' r!n time analysis tools "it# a r!n time error c#ec.com FREE TECHNICAL PAPER DOWNLOAD .er and $is!al interacti$e pro'iler can #elp de$elopers create #ig#er 5!ality* #ig#er per'ormance code in little time% -3.FREE TECHNICAL PAPER DOWNLOAD –www.Newtechpapers.ing en$ironments% One "ay de$elopers can !se t#ese analytical tools is to determine "#en to design a '!nction in #ard"are or so't"are% Pro'iling ena)les t#em to 5!ic.e on t#e personality o' di''erent* '!ndamental components o' digital circ!itryE t#e s"itc#es and "ires can )e reprogrammed to operate in any desired pattern* e''ecti$ely re"iring a c#ip's circ!itry on demand% A designer can do"nload a ne" "iring pattern and store it in t#e c#ip's memory* "#ere it can )e easily accessed "#en needed% Not so #ard a'ter all Recon'ig!ra)le #ard"are 'irst )ecame practical "it# t#e introd!ction a 'e" years ago o' a de$ice called a @'ield programma)le gate arrayA /FP0A1 )y Filin-* an electronics company t#at is no" )ased in .s are similar to s"itc#es "it# m!ltiple inp!ts and a single o!tp!t* and are !sed in digital circ!its to per'orm )inary operations% 2nli. s!ppliers to 'acilitate t#e design and deployment o' systems !sing com)inations o' t#e t"o tec#nologies% FP0As operating in con(!nction "it# em)edded design tools pro$ide an ideal plat'orm 'or de$eloping #ig# per'ormance recon'ig!ra)le comp!ting sol!tions 'or medical instr!ment applications% T#e plat'orm s!pports t#e design* de$elopment* and testing o' em)edded systems )ased on t#e C lang!age% Integration o' FP0A tec#nology into systems !sing a deterministic RTO.an 4ose* Cali'ornia% An FP0A is a c#ip consisting o' a large n!m)er o' @logic cellsA% T#ese cells* in t!rn* are sets o' transistors "ired toget#er to per'orm simple logical operations% E$ol$ing FP0As FP0As are arrays o' logic )loc.s o' FP0As )y sending signals t#at #a$e )een programmed in so't"are to t#e c#ip% FP0A )loc.e cp!s and D.ICs* andBto disting!is# t#em 'rom A.Ps% T#e largest o' t#e FP0A de$ices made )y t#e company "it# "#ic# one o' t#e a!t#ors o' t#is article is a''iliated* 'or e-ample* #as more t#an .

s and speci'ic '!nction )loc.com An FP0A consists o' an array o' con'ig!ra)le logic )loc.s t#at implement t#e logical '!nctions% In FP0A's* t#e logic '!nctions per'ormed "it#in t#e logic )loc.ed !p% .ed logic circ!its* an FP0A can )e programmed to do almost anyt#ing t#at a con$entional 'i-ed piece o' logic circ!itry can do* (!st )y loading t#e rig#t n!m)ers into its memory% And )y loading in a di''erent set o' n!m)ers* it can )e recon'ig!red in t#e t"in.ind o' c#ameleon de$ice "o!ld )e t#e .s are similar in str!ct!re to t#e gate arrays !sed in some A.s* and sending signals to t#e c#ip can alter t#e connections )et"een t#e )loc. ro!ters and s"itc#es* ena)ling circ!it designs to )e easily !pdated electronically "it#o!t replacing c#ips% In t#ese early applications* #o"e$er* t#e speed at "#ic# t#e c#ips recon'ig!re t#emsel$es is not critical% To )e 5!ic.etplace s!c# as Intel* =icroso't and A=D "ill )e cr!cial to t#eir s!r$i$al% T#e precise )e#a$io!r o' eac# cell is determined )y loading a string o' n!m)ers into a memory !nderneat# it% T#e "ay in "#ic# t#e cells are interconnected is speci'ied )y loading anot#er set o' n!m)ers into t#e c#ip% C#ange t#e 'irst set o' n!m)ers and yo! c#ange "#at t#e cells do% C#ange t#e second set and yo! c#ange t#e "ay t#ey are lin.iller app o' recon'ig!ra)le comp!ting+ T#ese e-perts predict t#at in t#e ne-t co!ple o' years recon'ig!ra)le systems "ill )e !sed in cell p#ones to #andle t#ings li.ICJs% T#e applications o' FP0AJs are in  image processing  encryption  mo)ile comm!nication  memory management and digital signal processing  telep#one !nits  mo)ile )ase stations% Alt#o!g# it is $ery #ard to predict t#e direction t#is tec#nology "ill ta.Newtechpapers.–www.: to . eno!g# 'or personal in'ormation de$ices* t#e c#ips "ill need to completely recon'ig!re t#emsel$es in a millisecond or less% +T#at .IC's* )!t "#ereas standard gate arrays are con'ig!red and 'i-ed d!ring man!'act!re* t#e con'ig!ra)le logic )loc.FREE TECHNICAL PAPER DOWNLOAD –www.e c#anges in telecomm!nications systems or standards as !sers tra$el )et"een calling regions or )et"een co!ntries% As it is getting more e-pensi$e and di''ic!lt to pattern* or etc#* t#e ela)orate circ!itry !sed in microprocessorsE many e-perts #a$e predicted t#at maintaining t#e c!rrent rate o' p!tting more circ!its into e$er smaller spaces "ill* sometime in t#e ne-t .et Fle-i)ility and 2pgrade ad$antages C#eap to ma.Newtechpapers.ly* since a c#ip can )e con'ig!red )y so't"are% A c#ip can also )e recon'ig!red* eit#er d!ring e-ec!tion time* or as part o' an !pgrade to allo" ne" applications* simply )y loading ne" con'ig!ration into t#e c#ip% T#e ad$antages can )e seen in terms o' cost* speed and po"er cons!mption% T#e added '!nctionality o' m!lti parallelism allo"s one FP0A to replace m!ltiple A.ely t#at t#e tec#nology "ill #a$e to c#ange o$er t#e coming years* and t#e rate o' c#ange 'or ma(or players in todays mar.e* it seems more t#an li.s* s!c# as 'loating point !nits% It is #ard to predict at t#is early stage* )!t it loo.? years* res!lt in 'eat!res on microc#ips no )igger t#an a 'e" atoms* "#ic# "o!ld demand a nearly impossi)le le$el o' precision in 'a)ricating circ!itry 3!t recon'ig!ra)le c#ips don't need t#at type o' precision and "e can ma.ince e$en t#e most complec#ip is* at its #eart* not#ing more t#an a )!nc# o' interlin.ely t#at '!t!re silicon c#ips "ill )e a com)ination o' programma)le logic* memory )loc.and Altera are "idely !sed 'or net"or.e %We can con'ig!re an FP0A !sing Gery Hig# Density Lang!age HGHDLI Handel C 4a$a %FP0AJs are !sed presently in Encryption Image Processing =o)ile Comm!nications %FP0AJs can )e !sed in 90 mo)ile comm!nication T#e ad$antages o' FP0As are t#at Field programma)le gate arrays o''er companies t#e possi)ility o' de$elloping a c#ip $ery 5!ic.s in ne" FP0A's can )e re"ired and reprogrammed repeatedly in aro!nd a microsecond% One ad$antages o' FP0A is t#at it needs small time to mar.e comp!ters t#at '!nction at t#e nanoscale le$el CS())( /a recon'ig!ra)le processor de$eloped )y c#ameleon systems1 -4.com FREE TECHNICAL PAPER DOWNLOAD .s li.s% T#ese )loc.ling o' an eye% 3asic recon'ig!ra)le circ!its already play a #!ge role in telecomm!nications% For instance* relati$ely simple $ersions made )y companies s!c# as Filin.

: to .L/digital s!)scri)er line1  Hig# end dsp operations 80 >0 "ireless )ase stations  so't"are de'ined radio  sec!rity processing +Traditional sol!tions s!c# as FP0As and D.ernels and t#e rest o' t#e standard C '!nction%C#ameleon's C .ernels* in C#ameleon's recon'ig!ra)le assem)ly lang!age li.:: 'old% T#e designer creates e5!i$alent '!nctions 'or t#ose )loc.ernels t#at t#e designer can $eri'y "it# commercial Gerilog sim!lators% 2sing t#ese tools* t#e designer can compare test)enc# res!lts 'or t#e original C '!nctions "it# similar res!lts 'or t#e Gerilog .8.e design entry lang!age% T#e assem)ler t#en a!tomatically generates standard Gerilog 'or t#ese .D= de$elopment .com RCP arc#itect!re is designed to )e as 'le-i)le as an FP0A* and as easy to program as a digital signal processor /D..8's recon'ig!ra)le processing 'a)ric% In addition to code generation tools* t#e pac.Newtechpapers.s* called .Ps lac.et press!res* not to mention t#e constant 'l!.e de)!gging* incl!ding 'eat!res li.8.IDE so't"are s!ite incl!des tools !sed to compile C and assem)ly code 'or e-ec!tion on t#e C.8 de$elopment en$ironment ma..oC s!)system* incl!ding an em)edded microprocessor* PCI core* D=A '!nction* and #ig# speed )!sE and t#ird )y consolidating t#e design and de)!g en$ironment into a single plat'orm )ased design system t#at a''ords t#e designer compre#ensi$e $isi)ility and control% T#e C .ernels% In t#e ne-t p#ase* t#e designer synt#esises t#e Gerilog .8.ICs* eac# o' "#ic# re5!ires a !ni5!e design and de)!g en$ironment% T#e RCP plat'orm "as designed 'rom t#e gro!nd !p to alle$iate t#is pro)lem& 'irst )y signi'icantly e-ceeding t#e per'ormance and c#annel capacity o' t#e 'astest D.it* ena)les c!stomers to de$elop and de)!g comm!nication and signal processing systems r!nning on t#e RCP% T#e RCP's de$elopment en$ironment #elps o$ercome a '!ndamental design and de)!g c#allenge 'acing comm!nication system designers%In order to )!ild s!''icient per'ormance* c#annel capacity* and 'le-i)ility into t#eir systems* today's designers #a$e )een 'orced to employ an amalgamation o' D..8 Pac.points% 3e'ore act!ally prod!ctising t#e system* t#e designer m!st o'ten per'orm a system le$el sim!lation o' t#e data 'lo" "it#in t#e conte-t o' t#e o$erall system% C#ameleon's de$elopment )oard ena)les t#e designer to connect m!ltiple RCPs to ot#er de$ices in t#e system !sing t#e PCI )!s and7or programma)le I7O pins% T#is #elps pro$e t#e design concept* and ena)les t#e designer to pro'ile t#e per'ormance o' t#e "#ole )asestation system in a real "orld en$ironment% Wit# telecomm!nications OE=s 'acing s#rin.8's em)edded microprocessor* and Gerilog sim!lation and synt#esis tools !sed to create parallel datapat# .IDE compiler and lin.Ps* FP0As and A.o' protocols and standards* it's more necessary t#an e$er to #a$e a plat'orm t#at's recon'ig!ra)le% T#is is "#ere t#e c#ameleon c#ips are going to ma.IDE so't"are tool s!ite and CT8.er tec#nology ma.–www.ICs inc!r !naccepta)le limits Eac# prod!ct in t#e -5.ernels "#ic# r!n on t#e C.age is a #ig# )and"idt#* recon'ig!ra)le comm!nications processor aimed at  second and t#ird generation "ireless )ase stations 'i-ed point "ireless local loop /WLL1  $oice o$er IP D.e single stepping and setting )rea. t#e per'ormance 'or #ig# )and"idt# applications* and 'i-ed '!nction sol!tions li.es t#is integration step transparent to t#e designer% T#e C..P1* "it# real time* $is!al de)!gging capa)ility% T#e de$elopment en$ironment* comprising C#ameleon's C .com FREE TECHNICAL PAPER DOWNLOAD .s* t#e designer implements t#em in t#e RCP to accelerate t#em )y .es all c#ip registers and memory locations accessi)le t#ro!g# a de$elopment console t#at ena)les '!ll processor li.age contains so!rce le$el de)!gging tools t#at s!pport sim!lation and real time de)!gging% C#ameleon's design approac# le$erages t#e met#ods employed )y most o' today's comm!nications system designers% T#e designer starts "it# a C program t#at models signal processing '!nctions o' t#e )ase)and system% Ha$ing identi'ied t#e data'lo" intensi$e '!nctional )loc.Newtechpapers.e its e''ect 'elt% T#e C#ameleon C..e A.ing prod!ct li'e cycles and increasing mar.8.PsE second )y integrating a complete .8.ernels !sing C#ameleon's synt#esis tools targeting C#ameleon tec#nology% At t#e end* t#e tools o!tp!t a )it 'ile t#at is !sed to con'ig!re t#e RCP%T#e designer t#en integrates t#e application le$el C code "it# Gerilog .FREE TECHNICAL PAPER DOWNLOAD –www.

8?=H6 <9 )it memory controller >8 )it PCI controller recon'ig!ra)le processing 'a)ric /RPF1 #ig# speed system )!s programma)le I7O /.8::: 'amily #as t#e same '!ndamental '!nctional )loc.com C.lices "it# > Tiles in eac#% Eac# tile can )e recon'ig!red at r!ntime Tiles contain & • • • • Datapat# 2nits Local .IC and FP0A design 'lo"s* according to C#ameleon% .es a #ard"are component 'rom t#e li)rary /"#ic# is stored as so't"are in memory1 and p!ts it on t#e c#al. ro!ter* a D..ly adapt to n!mero!s and 'ast c#anging standards% Pl!s* t#ey claim to ac#ie$e #ig#er per'ormance "it#o!t adding silicon area* cost* design time* or po"er cons!mption% In essence* )eca!se t#e arc#itect!re isn't rigid* t#e -6.Newtechpapers.till* recon'ig!ra)le c#ips represent an attempt to com)ine t#e )est 'eat!res o' #ard "ired c!stom c#ips* "#ic# are 'ast and c#eap* and programma)le logic de$ice /PLD1 c#ips* "#ic# are 'le-i)le and easily )ro!g#t to mar.tore =emories .programma)le logic de$ices /CPLDs1% O' t#e t"o* FP0As o''er t#e #ig#est amo!nt o' logic density* t#e most 'eat!res* and t#e #ig#est per'ormance FP0As are !sed in a "ide $ariety o' applications ranging 'rom data processing and storage* to instr!mentation* telecomm!nications* and digital signal processing% To o$ercome t#ese limitations and o''er a 'le-i)le* cost e''ecti$e sol!tion* many ne" entrants to t#e D.Newtechpapers.IDE design system is a '!lly integrated tool s!ite* "it# C compiler* Gerilog synt#esi6er* '!ll c#ip sim!lator* as "ell as a de)!g and $eri'ication en$ironment an element not readily 'o!nd in A.FREE TECHNICAL PAPER DOWNLOAD –www.<-89 )it m!ltipliers* and a control logic !nit% *ASIC ARCHITECTURE Compo e ts+         >8 )it Risc ARC processor K.et are e-tolling t#e $irt!es o' con'ig!ra)le and recon'ig!ra)le D.–www.et% 2nli.)oard /t#e c#ip1% T#e c#ip "ires itsel' instantly to r!n t#e so't"are and dispatc#es it% T#e #ard"are can t#en )e erased 'or t#e ne-t cycle% Wit# t#is style o' comp!ting* its c#ips can operate D: times as 'ast as a c!stom c#ip )!t still cons!me less po"er and )oard space* "#ic# translates into lo"er costs% T#e company )elie$es t#at +so't silicon*+ or c#ips t#at can )e recon'ig!red on t#e 'ly* can )e t#e #eart o' m!lti'!nction camcorders or digital tele$ision sets% Wit# programma)le logic de$ices* designers !se ine-pensi$e so't"are tools to 5!ic.ly programmed into a de$ice* and immediately tested in a li$e circ!it% T#e PLD t#at is !sed 'or t#is prototyping is t#e e-act same PLD t#at "ill )e !sed in t#e 'inal prod!ction o' a piece o' end e5!ipment* s!c# as a net"or.)oards% 2pon recei$ing instr!ctions 'rom so't"are* t#e c#ip ta.<-89 m!ltipliers Control Logic 2nit T#e C .P mar.e PLDs* L!ic.L modem* a DGD player* or an a!tomoti$e na$igation system% T#e t"o ma(or types o' programma)le logic de$ices are 'ield programma)le gate arrays /FP0As1 and comple.s o' local store memory* t"o .com FREE TECHNICAL PAPER DOWNLOAD .!)system =ore on t#e arc#itect!re o' RPF 9 . o' t#e c#ips as consisting o' li)raries "it# preset #ard"are designs and c#al.!)system Con'ig!ration .il$er's recon'ig!ra)le c#ips can )e reprogrammed e$ery 'e" nanoseconds* re"iring circ!its so t#ey are processing glo)al positioning satellite signals one moment or CD=A cell!lar signals t#e ne-t* T#in.P designs% T#is latest )reed o' D.C processor* a '!ll 'eat!red memory controller* a PCI controller* and a recon'ig!ra)le processing 'a)ric* all o' "#ic# are interconnected )y a #ig# speed system )!s% T#e a)o$e mentioned 'a)ric comprises an array o' recon'ig!ra)le tiles !sed to implement t#e desired algorit#ms% Eac# tile contains se$en >8 )it recon'ig!ra)le datapat# !nits* 'o!r )loc.<: pins1 D=A .P arc#itect!res promises greater 'le-i)ility to 5!ic.ly de$elop* sim!late* and test t#eir designs% T#en* a design can )e 5!ic.s& a >8 )it RI.

(!st one second at a 8? =H6 cloc.DP1% T#o!g# t#e .Newtechpapers.* ac#ie$ing t#e rig#t si6e and cost 'or t#e target application% =oreo$er* t#e same plat'orm can )e re!sed 'or ot#er applications% 3eca!se de$elopment tools are a critical part o' t#is sol!tionBin 'act* t#ey're tr!e ena)lersBt#e ne"comers also ens!re t#at t#e tools are ro)!st and tig#tly lin.? p#ase o''sets in a )asic m!ltipat# searc# algorit#m is >%9 seconds% T#e AC= test c#ip too.C core* and it "ill s!pport a m!c# #ig#er cloc.Newtechpapers.FREE TECHNICAL PAPER DOWNLOAD –www.–www.ing c#anges )ecomes as simple as do"nloading a ne" con'ig!ration into t#e c#ip% C#ameleon .1% In t#e set maintenance application* t#e c#ip is almost t#ree times 'aster t#an an A.e 'inger* and set maintenance% For e-ample* t#e A.DP sometime in t#e 'irst 5!arter o' 8::>% W#ile C#ameleon is in t#e redesign mode* L!ic. cycle% C#ameleon designers are re$ising t#e arc#itect!re to create a c#ip t#at can address a m!c# )roader range o' applications% Pl!s* t#e s!pplier is preparing a ne"* more !ser 'riendly s!ite o' tools 'or traditional D.ome o' t#e ne" con'ig!ra)le D. process to meet t#e signal processing needs o' a m!c# )roader mar.IC* claims L!ic.et% RECON'I$URA*LE PROCESSORS A recon'ig!ra)le processor is a microprocessor "it# erasa)le #ard"are t#at can re"ire itsel' dynamically% T#is allo"s t#e c#ip to adapt e''ecti$ely to t#e programming tas. rate% Additionally* it "ill )e implemented in a :%..IC's nominal speed 'or searc#ing 8.ystems also de$elops recon'ig!ra)le c#ips 'or t#e #ig# end telecom s"itc#ing mar.P lets t#e de$eloper tailor t#e #ard"are 'or a speci'ic tas.s is )ot# a strengt# and a "ea.P designers% T#!s* t#e company is dropping t#e term recon'ig!ra)ility 'or t#e ne" arc#itect!re and going "it# a more traditional name* t#e streaming data processor /.et% F!rt#er details a"ait t#e release o' .DP "ill incl!de a recon'ig!ra)le processing 'a)ric* it "ill )e s!)stantially altered* t#e company says% 2nli.ed to t#e de$ices' 'le-i)le arc#itect!res% W#ile pro$iding an int!iti$e* integrated de$elopment en$ironment 'or t#e designers* t#e man!'act!rers ens!re a''orda)ility as "ell% RECON'I$URIN$ THE ARCHITECTURE .s demanded )y t#e partic!lar so't"are t#ey are inter'acing "it# at any gi$en time% Ideally* t#e recon'ig!ra)le processor can trans'orm itsel' 'rom a $ideo c#ip to a central processing !nit /cp!1 to a grap#ics c#ip* 'or e-ample* all optimi6ed to allo" applications to r!n at t#e #ig#est possi)le speed% T#e ne" c#ips -7.e t#e older RCP* t#e ne" c#ip "on't #a$e t#e AR= RI. speed to per'orm t#e same n!m)er o' searc#es in a cdma8::: #andset% Li.P arc#itect!res are recon'ig!ra)le tooBt#at is* de$elopers can modi'y t#eir landscape on t#e 'ly* depending on t#e incoming data stream% T#is capa)ility permits dynamic recon'ig!ra)ility o' t#e arc#itect!re as demanded )y t#e application% Proponents o' s!c# c#ips are proclaiming an era o' +c#ip on demand*+ "#erein ne" algorit#ms can )e accommodated on c#ip in real time $ia so't"are% T#is eliminates t#e c!m)ersome (o) o' 'itting t#e latest algorit#ms and protocols into e-isting rigid #ard"are% A recon'ig!ra)le comm!nications processor /RCP1 can recon'ig!red 'or di''erent processing algorit#ms in one cloc.e"ise* t#e de$ice accomplis#es o$er ?N*::: adaptations per second in ra.s as processing > D grap#ics* decoding and playing mo$ies* and processing so!ndBt#ings t#at co!ld* in t#eory* )e done )y t#e )asic microprocessorBto specialist c#ips% T#ese c#ips are designed to do t#eir partic!lar (o)s e-tremely 'ast* )!t t#ey are in'le-i)le in comparison "it# a microprocessor* "#ic# does its )est to )e a (ac. o' all trades% .top PC mig#t* 'or e-ample* )e )ro"sing t#e Internet one min!te* and r!nning a spreads#eet or entering t#e $irt!al "orld o' a comp!ter game t#e ne-t% 3!t t#e a)ility o' a microprocessor /t#e c#ip t#at is at t#e #eart o' any PC1 to #andle s!c# a $ariety o' tas.> Mm C=O.IC in processing comp!te intensi$e cdma8::: algorit#ms* li.il$er Tec#nologies is in t#e test mode% T#is recon'ig!ra)le proponent* "#ic# pre'ers to call its arc#itect!re an adapti$e comp!ting mac#ine or AC=* #as reali6ed its 'irst silicon test c#ip% In 'act* t#e tests indicate t#at it o!tper'orms a #ard"ired* 'i-ed '!nction A.com FREE TECHNICAL PAPER DOWNLOAD .o t#e #ard"are approac# is 'aster* )!t !sing so't"are is more 'le-i)le% At t#e moment* s!c# recon'ig!ra)le c#ips are !sed mainly as a "ay o' con(!ring !p specialist #ard"are in a #!rry% Rat#er t#an designing and )!ilding an entirely ne" c#ip to carry o!t a partic!lar '!nction* a circ!it designer can !se an FP0A instead% T#is speeds !p t#e design process enormo!sly* )eca!se ma.e system ac5!isition* ra.nessB)eca!se #ard"are dedicated to a partic!lar (o) can do t#ings so m!c# 'aster% Recognising t#is* t#e designers o' modern PCs o'ten #and o$er s!c# tas.il$er% THE po"er o' a comp!ter stems 'rom t#e 'act t#at its )e#a$io!r can )e c#anged "it# little more t#an a dose o' ne" so't"are% A des.com recon'ig!ra)le D.e 'inger operation to cycle t#ro!g# all operations in t#is application e$ery ?8 Ms /Fig% ..

s% T#e .FREE TECHNICAL PAPER DOWNLOAD –www.IC% In t#is scenario* t#e FP0A is present only on t#e prototype #ard"are and is replaced )y t#e corresponding A.Newtechpapers.s "it# #ig# '!nctional di$ersity* microprocessors !se silicon more e''iciently t#an recon'ig!ra)le de$ices% T#e 3RA.)ene'it in comp!tational density o$er microprocessors* and o'ten o''ering anot#er potential . a)o!t recon'ig!ra)le comp!ting "eJre !s!ally tal." In practical terms* t#is a)ility can translate to immense 'le-i)ility in terms o' de$ice '!nctions% For e-ample* a single de$ice co!ld ser$e as )ot# a camera and a tape recorder /among n!mero!s ot#er possi)ilities1& yo! "o!ld simply do"nload t#e desired so't"are and t#e processor "o!ld recon'ig!re itsel' to optimi6e per'ormance 'or t#at '!nction% Recon'ig!ra)le processors* competing in t#e mar.ing a)o!t FP0A )ased system designs% 2n'ort!nately* t#at doesnJt 5!ali'y t#e term precisely eno!g#% .Ps1* 'or e-ample* are #ig# per'ormance programma)le c#ips !sed in cell p#ones* a!tomo)iles* and $ario!s types o' m!sic players% W#ile microprocessors #a$e )een t#e dominant de$ices in !se 'or general p!rpose comp!ting 'or t#e last decade* t#ere is still a large gap )et"een t#e comp!tational e''iciency o' microprocessors and c!stom silicon% Recon'ig!ra)le de$ices* s!c# as FP0As* #a$e come closer to closing t#at gap* o''ering a .:-* t#an con$entional processors% T#e #ig# '!nctional density c#aracteristic o' recon'ig!ra)le de$ices comes at t#e e-pense o' t#e #ig# '!nctional di$ersity c#aracteristic o' microprocessors% =icroprocessors #a$e e$ol$ed to a #ig#ly optimi6ed con'ig!ration "it# clear cost7per'ormance ad$antages o$er recon'ig!ra)le arrays 'or a large set o' tas.impro$ement in yielded '!nctional density on lo" gran!larity operations% On #ig#ly reg!lar comp!tations* recon'ig!ra)le arc#itect!res #a$e a clear s!periority to traditional processor arc#itect!res% On tas.:.–www.et "it# traditional #ard "ired c#ips and se$eral types o' programma)le microprocessors% Programma)le c#ips #a$e )een in e-istence 'or o$er ten years% Digital signal processors /D.com FREE TECHNICAL PAPER DOWNLOAD ..ey to t#eir cost7per'ormance ad$antage is t#at con$entional processors are o'ten limited )y instr!ction )and"idt# and e-ec!tion restrictions or )y an ins!''icient n!m)er or type o' '!nctional !nits% Recon'ig!ra)le logic e-ploits more program parallelism% 3y dedicating signi'icantly less instr!ction memory per acti$e comp!ting element* recon'ig!ra)le de$ices ac#ie$e a .:impro$ement in '!nctional density o$er microprocessors% At t#e same time t#is lo"er memory ratio allo"s recon'ig!ra)le de$ices to deploy acti$e capacity at a 'iner grained le$el* allo"ing t#em to reali6e a #ig#er yield o' t#eir ra" capacity* sometimes as m!c# as .!c# systems retain t#e e-ec!tion speed o' dedicated #ard"are )!t also #a$e a great deal o' '!nctional -8. pro(ect is de$eloping a co!pled arc#itect!re "#ic# allo" a recon'ig!ra)le array and processor core to cooperate e''iciently on comp!tational tas.s* e-ploiting t#e strengt#s o' )ot# arc#itect!res% We are de$eloping an arc#itect!re and a prototype component t#at "ill com)ine a processor and a #ig# per'ormance recon'ig!ra)le array on a single c#ip% T#e recon'ig!ra)le array e-tends t#e !se'!lness and e''iciency o' t#e processor )y pro$iding t#e means to tailor its circ!its 'or special tas.s% T#e processor impro$es t#e e''iciency o' t#e recon'ig!ra)le array 'or irreg!lar* general p!rpose comp!tation% We anticipate t#at a processor com)ined "it# recon'ig!ra)le reso!rces can ac#ie$e a signi'icant per'ormance impro$ement o$er eit#er a separate processor or a separate recon'ig!ra)le de$ice on an interesting range o' pro)lems dra"n 'rom em)edded comp!ting applications% As s!c#* "e #ope to demonstrate t#at t#is composite de$ice is an ideal system element 'or em)edded processing% Recon'ig!ra)le de$ices #a$e pro$en e-tremely e''icient 'or certain types o' processing tas.s "it# #ig# '!nctional di$ersity% 3y com)ining a recon'ig!ra)le array "it# a processing core "e #ope to ac#ie$e t#e )est o' )ot# "orlds% W#ile it is possi)le to com)ine a con$entional processor "it# commercial recon'ig!ra)le de$ices at t#e circ!it )oard le$el* integration radically c#anges t#e i7o costs and design point 'or )ot# de$ices* res!lting in a 5!alitati$ely di''erent system% Nota)ly* t#e lo"er on c#ip comm!nication costs allo" e''icient cooperation )et"een t#e processor and array at a 'iner grain t#an is sensi)le "it# discrete designs% RECON'I$URA*LE COMPUTIN$ W#en "e tal.:.IC in t#e 'inal prod!ction system% T#is !se o' FP0As #as not#ing to do "it# recon'ig!ra)le comp!ting% Ho"e$er* many system designers are c#oosing to lea$e t#e FP0As as part o' t#e prod!ction #ard"are% Lo"er FP0A prices and #ig#er gate co!nts #a$e #elped dri$e t#is c#ange% .com can )e called a "chip o !ema !.ystem designers !se FP0As in many di''erent "ays% T#e most common !se o' an FP0A is 'or prototyping t#e design o' an A.Newtechpapers.

"apping #ard"are o)(ects into and o!t o' t#e recon'ig!ra)le logic Per'orming ro!ting )et"een #ard"are o)(ects or )et"een #ard"are o)(ects and t#e #ard"are o)(ect 'rame"or.–www.!c# c#anges e-tend t#e !se'!l li'e o' t#e system* t#!s red!cing li'etime costs% 'inal ad$antage o' recon'ig!ra)le comp!ting is red!ced time to mar. protocol* yo! can redesign t#e internal logic o' t#e FP0A and send t#e en#ancement to t#e a''ected c!stomers )y email% Once t#eyJ$e do"nloaded t#e ne" logic design to t#e system and restarted it* t#eyJll )e a)le to !se t#e ne" $ersion o' t#e protocol% T#is is con'ig!ra)le comp!tingE recon'ig!ra)le comp!ting goes one step '!rt#er% Recon'ig!ra)le comp!ting in$ol$es manip!lation o' t#e logic "it#in t#e FP0A at r!n time% In ot#er "ords* t#e design o' t#e #ard"are may c#ange in response to t#e demands placed !pon t#e system "#ile it is r!nning% Here* t#e FP0A acts as an e-ec!tion engine 'or a $ariety o' di''erent #ard"are '!nctions B some e-ec!ting in parallel* ot#ers in serial B m!c# as a CP2 acts as an e-ec!tion engine 'or a $ariety o' so't"are t#reads% We mig#t e$en go so 'ar as to call t#e FP0A a recon'ig!ra)le processing !nit /RP21% Recon'ig!ra)le comp!ting allo"s system designers to e-ec!te more #ard"are t#an t#ey #a$e gates to 'it* "#ic# "or.ystems )ased on recon'ig!ra)le comp!ting are !pgrada)le in t#e 'ield% .or cell!lar telep#one* it may e$en )e possi)le to ma.% O' co!rse* #a$ing so't"are manage t#e recon'ig!ra)le #ard"are !s!ally means #a$ing an em)edded processor or microcontroller on )oard% /We e-pect se$eral $endors to introd!ce single c#ip sol!tions t#at com)ine a CP2 core and a )loc.e a set top )o.e s!c# en#ancements "it#o!t c!stomer in$ol$ement% RECON'I$URA*LE HARD.com 'le-i)ility% T#e logic "it#in t#e FP0A can )e c#anged i' or "#en it is necessary* "#ic# #as many ad$antages% For e-ample* #ard"are )!g 'i-es and !pgrades can )e administered as easily as t#eir so't"are co!nterparts% In order to s!pport a ne" $ersion o' a net"or.ed prod!ct li.com FREE TECHNICAL PAPER DOWNLOAD . in terms o' li'etime system costs to see t#e sa$ings% .IC is a )ig #elp in t#is respect% T#ere are no c#ip design and prototyping cycles* "#ic# eliminates a large amo!nt o' de$elopment e''ort% In addition* t#e logic design remains 'le-i)le rig#t !p !ntil /and e$en a'ter1 t#e prod!ct s#ips% T#is allo"s an incremental design 'lo"* a l!-!ry not typically a$aila)le to #ard"are designers% Oo! can e$en s#ip a prod!ct t#at meets t#e minim!m re5!irements and add 'eat!res a'ter deployment% In t#e case o' a net"or. o' recon'ig!ra)le logic )y yearJs end%1 T#e em)edded so't"are t#at r!ns t#ere is called t#e r!n  T#e -9.Newtechpapers.FREE TECHNICAL PAPER DOWNLOAD –www.ARE Traditional FP0As are con'ig!ra)le* )!t not r!n time recon'ig!ra)le% =any o' t#e older FP0As e-pect to read t#eir con'ig!ration o!t o' a serial EEPRO=* one )it at a time% And t#ey can only )e made to do so )y asserting a c#ip reset signal% T#is means t#at t#e FP0A m!st )e reprogrammed in its entirety and t#at its pre$io!s internal state cannot )e capt!red )e'ore#and% T#o!g# t#ese 'eat!res are compati)le "it# con'ig!ra)le comp!ting applications* t#ey are not s!''icient 'or recon'ig!ra)le comp!ting% In order to )ene'it 'rom r!n time recon'ig!ration* it is necessary t#at t#e FP0As in$ol$ed #a$e some or all o' t#e 'ollo"ing 'eat!res% T#e more o' t#ese 'eat!res t#ey #a$e* t#e more 'le-i)le can )e t#e system design% Deciding "#ic# #ard"are o)(ects to e-ec!te and "#en .et% T#e 'act t#at yo!Jre no longer !sing an A.Newtechpapers.s especially "ell "#en t#ere are parts o' t#e #ard"are t#at are occasionally idle% One t#eoretical application is a smart cell!lar p#one t#at s!pports m!ltiple comm!nication and data protocols* t#o!g# (!st one a time% W#en t#e p#one passes 'rom a geograp#ic region t#at is ser$ed )y one protocol into a region t#at is ser$ed )y anot#er* t#e #ard"are is a!tomatically recon'ig!red% T#is is recon'ig!ra)le comp!ting at its )est* and !sing t#is approac# it is possi)le to design systems t#at do more* cost less* and #a$e s#orter design and implementation cycles% Recon'ig!ra)le comp!ting #as se$eral ad$antages%  First* it is possi)le to ac#ie$e greater '!nctionality "it# a simpler #ard"are design% 3eca!se not all o' t#e logic m!st )e present in t#e FP0A at all times* t#e cost o' s!pporting additional 'eat!res is red!ced to t#e cost o' t#e memory re5!ired to store t#e logic design% Consider again t#e m!ltiprotocol cell!lar p#one% It "o!ld )e possi)le to s!pport as many protocols as co!ld )e 'it into t#e a$aila)le on )oard RO=% It is e$en concei$a)le t#at ne" protocols co!ld )e !ploaded 'rom a )ase station to t#e #and#eld p#one on an as needed )asis* t#!s re5!iring no additional memory%  T#e second ad$antage is lo"er system cost* "#ic# does not mani'est itsel' e-actly as yo! mig#t e-pect% On a lo" $ol!me prod!ct* t#ere "ill )e some prod!ction cost sa$ings* "#ic# res!lt 'rom t#e elimination o' t#e e-pense o' A.IC design and 'a)rication% Ho"e$er* 'or #ig#er $ol!me prod!cts* t#e prod!ction cost o' 'i-ed #ard"are may act!ally )e lo"er% We #a$e to t#in.

Newtechpapers.ICsBc#ips t#at #andle a limited set o' tas.ol!tions in$ol$ing com)inations o' cp!s and FP0As allo" #ard"are '!nctionality to )e reprogrammed* e$en in deployed systems* and ena)le medical instr!ment OE=s to de$elop ne" plat'orms 'or applications t#at re5!ire rapid adaptation to inp!t% T#e tec#nologies com)ined pro$ide t#e )est o' )ot# "orlds 'or system le$el design% Care'!l analysis o' comp!tational re5!irements re$eals t#at many algorit#ms are "ell s!ited to #ig# speed se5!ential processing* many can )ene'it 'rom parallel processing capa)ilities* and many can )e )ro.ing on general p!rpose tas.ly as o!r competitors )eca!se recon'ig!ra)le comp!ting ena)les t#e addition o' ne" 'eat!res in t#e 'ield* allo"s rapid implementation o' ne" standards and protocols on an as needed )asis* and protects t#eir in$estment in comp!ting #ard"are% W#et#er yo! do it 'or yo!r c!stomers or 'or yo!rsel$es* yo! s#o!ld at least consider !sing recon'ig!ra)le comp!ting in yo!r ne-t design% Oo! may 'ind* as "e #a$e* t#at t#e )ene'its 'ar e-ceed t#e initial learning c!r$e% And as recon'ig!ra)le comp!ting )ecomes more pop!lar* t#ese )ene'its "ill only increase% AD#ANTA$ES O' RECON'I$URA*ILITT#e term recon'ig!ra)le comp!ting #as come to re'er to a loose class o' em)edded systems% =any system on a c#ip /.ICs* and general p!rpose cp!sBis t#at t#e logical #ard"are '!nctions cannot )e modi'ied once t#e silicon design is complete and 'a)ricated% Conse5!ently* de$elopers are typically 'orced to amorti6e t#e cost o' .e decisions )ased !pon it% T#e reason "e need a r!n time en$ironment at all is t#at t#ere are decisions to )e made "#ile t#e system is r!nning% And as #!man designers* "e are not a$aila)le to ma.o "e impart t#ese responsi)ilities to a piece o' so't"are% T#is allo"s !s to "rite o!r application so't"are at a $ery #ig# le$el o' a)straction% To do t#is* t#e r!n time en$ironment m!st 'irst locate space "it#in t#e RP2 t#at is large eno!g# to e-ec!te t#e gi$en #ard"are o)(ect% It m!st t#en per'orm t#e necessary ro!ting )et"een t#e #ard"are o)(ectJs inp!ts and o!tp!ts and t#e )loc.com FREE TECHNICAL PAPER DOWNLOAD .oCs and A.s s!c# as data analysis* and more time comm!nicating "it# a printer or ot#er e5!ipment% -10.* reprogram t#e internal logic* and restart t#e RP2% Once t#e o)(ect starts to e-ec!te* t#e r!n time en$ironment m!st contin!o!sly monitor t#e #ard"are o)(ectJs stat!s 'lags to determine "#en it is done e-ec!ting% Once it is done* t#e caller can )e noti'ied and gi$en t#e res!lts% T#e r!n time en$ironment is t#en 'ree to reclaim t#e recon'ig!ra)le logic gates t#at "ere ta.e t#ese decisions% .Ps1* "#ile FP0As e-cel at #ig# speed parallel processing% T#e general p!rpose capa)ility o' t#e cp! ena)les it to per'orm system management $ery "ell* and allo"s it to )e !sed to control t#e content o' t#e FP0As contained in t#e system% T#is sym)iotic relations#ip )et"een cp!s and FP0As also means t#at t#e FP0A can o'' load comp!tationally intensi$e algorit#ms 'rom t#e cp!* allo"ing t#e processor to spend more time "or.oCs* A.oCs o''er c#oices* t#e !ser can c#oose only among '!nctions t#at already reside inside t#e de$ice% De$elopers also create A.es sense to al"ays !se t#e )est tec#nology 'or t#e (o) at #and% Processors are )est s!ited to general p!rpose processing and #ig# speed se5!ential processing /as are D.en do"n into components t#at are split )et"een t#e t"o% Wit# t#is in mind* it ma.s o' memory reser$ed 'or eac# data stream% Ne-t* it m!st stop t#e appropriate cloc.#ard"are de$icesB.oC1 comp!ter designs pro$ide recon'ig!ra)ility options t#at pro$ide t#e #ig# per'ormance o' #ard"are "it# t#e 'le-i)ility o' so't"are% To most designers* .e t#reads* #ard"are o)(ects may #a$e priorities* deadlines* and conte-ts* etc% It is t#e (o) o' t#e r!n time en$ironment to organi6e t#is in'ormation and ma.FREE TECHNICAL PAPER DOWNLOAD –www.–www.es doing more "it# less a reality% In o!r o"n )!siness "e #a$e seen tremendo!s cost sa$ings* simply )eca!se o!r systems do not )ecome o)solete as 5!ic.com time en$ironment and is analogo!s to t#e operating system t#at manages t#e e-ec!tion o' m!ltiple so't"are t#reads% Li.P1 coresBalong "it# memory* inp!t7o!tp!t de$ices* and ot#er #ard"are into a single c#ip% T#ese $ersatile c#ips can per'orm many di''erent '!nctions% Ho"e$er* "#ile .ICs o$er a prod!ct li'etime t#at may )e e-tremely s#ort in today's $olatile tec#nology en$ironment% .ly% T#e limitation o' most types o' comple.en !p )y t#at #ard"are o)(ect and to "ait 'or additional re5!ests to arri$e 'rom t#e application so't"are% T#e principal )ene'its o' recon'ig!ra)le comp!ting are t#e a)ility to e-ec!te larger #ard"are designs "it# 'e"er gates and to reali6e t#e 'le-i)ility o' a so't"are )ased sol!tion "#ile retaining t#e e-ec!tion speed o' a more traditional* #ard"are )ased approac#% T#is ma.Newtechpapers.oC means encaps!lating one or more processing elementsBt#at is* general p!rpose em)edded processors and7or digital signal processor /D.s )!t do t#em $ery 5!ic.

FREE TECHNICAL PAPER DOWNLOAD –www.com FREE TECHNICAL PAPER DOWNLOAD .Newtechpapers.L concentrators*'i-ed "ireless local loop* m!ltic#annel $oice compression* m!ltiprotocol pac.et and cell processing protocols% Its ad$antages are t#at it can create c!stomi6ed comm!nications signal processors *it #as increased per'ormance and c#annel co!nt* and it can more 5!ic.ind o' c#ip may res#ape t#e semicond!ctor landscape% T#e c#ip adapts to any programming tas.ind o' a c#ip is a c#ameleon c#ip%t#is can also )e called a @c#ip on demandA @Recon'ig!ra)le comp!ting goes a step )eyond programma)le c#ips in t#e matter o' 'le-i)ility% It is not only possi)le )!t relati$ely commonplace to +re"rite+ t#e silicon so t#at it can -11.ind o' a c#ip is a c#ameleon c#ip%t#is can also )e called a @c#ip on demandA Recon'ig!ra)le comp!ting goes a step )eyond programma)le c#ips in t#e matter o' 'le-i)ility% It is not only possi)le )!t relati$ely commonplace to +re"rite+ t#e silicon so t#at it can per'orm ne" '!nctions in a split second% Recon'ig!ra)le c#ips are simply t#e e-treme end o' programma)ility%A Hig#ly 'le-i)le processors t#at can )e recon'ig!red remotely in t#e 'ield* C#ameleon's c#ips are designed to simpli'y comm!nication system design "#ile deli$ering increased price7per'ormance n!m)ers% T#e c#ameleon c#ip is a #ig# )and"idt# recon'ig!ra)le comm!nications processor /RCP1%it aims at c#anging a system's design 'rom a remote location%t#is "ill mean more $ersatile #and#elds% Its applications are in* data intensi$e Internet*D.–www.% A FUTURISTIC DREAM One day* someone "ill ma.com CONCLUSION T#ese ne" c#ips called c#ameleon c#ips are a)le to re"ire t#emsel$es on t#e 'ly to create t#e e-act #ard"are needed to r!n a piece o' so't"are at t#e !tmost speed%an e-ample o' s!c# .e a c#ip t#at does e$eryt#ing 'or t#e !ltimate cons!mer de$ice% T#e c#ip "ill )e smart eno!g# to )e t#e )rains o' a cell p#one t#at can transmit or recei$e calls any"#ere in t#e "orld% I' t#e reception is poor* t#e p#one "ill a!tomatically ad(!st so t#at t#e 5!ality impro$es% At t#e same time* t#e de$ice "ill also ser$e as a #and#eld organi6er and a player 'or m!sic* $ideos* or games% 2n'ort!nately* t#at c#ip doesn't e-ist today% It "o!ld re5!ire • • • • 'le-i)ility #ig# per'ormance lo" po"er and lo" cost 3!t "e mig#t )e getting closer% No" a ne" .ly adapt to ne" re5!irements and standards and it #as lo"er de$elopment costs and red!ce ris.Newtechpapers. )y e''ecti$ely erasing its #ard"are design and regenerating ne" #ard"are t#at is per'ectly s!ited to r!n t#e so't"are at #and% T#ese c#ips* re'erred to as recon'ig!ra)le processors* co!ld tilt t#e )alance o' po"er t#at #as preser$ed a decade long stando'' )et"een programma)le c#ips and #ard "ired c!stom c#ips% T#ese ne" c#ips are a)le to re"ire t#emsel$es on t#e 'ly to create t#e e-act #ard"are needed to r!n a piece o' so't"are at t#e !tmost speed%an e-ample o' s!c# .P*"ireless )asestations* $oice compression* so't"are de'ined radio* #ig# per'ormance em)edded telecom and datacom applications* -D.

P c#ips )!t slo"er and more e-pensi$e For cons!mers* t#is means t#at t#e day isn't 'ar a"ay "#en a cell p#one can )e !sed to tal. o' t#e possi)ilities 'or t#e 'ic. t#e static #ard "ired sol!tions% And i' silicon can indeed )ecome dynamic* t#en so "ill t#e gadgets o' t#e in'ormation age% No longer "ill yo! #a$e to )!y a camera and a tape recorder% Oo! co!ld (!st )!y one gadget* and t#en do"nload a ne" '!nction 'or it "#en yo! "ant to ta.* transmit $ideo images* connect to t#e Internet* maintain a calendar* and ser$e as entertainment d!ring tra$el delays "it#o!t t#e need to pl!g in adapter #ard"are RE'ERENCES *OO.com per'orm ne" '!nctions in a split second% Recon'ig!ra)le c#ips are simply t#e e-treme end o' programma)ility%A I' t#ese adapta)le c#ips can reac# a cost per'ormance parity "it# #ard "ired c#ips* c!stomers "ill c#!c.E*SITES • • • • • • • """%c#ameleon systems%com """%t#in.com FREE TECHNICAL PAPER DOWNLOAD .digit%com """%seminartopics%in'o """%ieee%org """%iec%org """%5!ic.e some pict!res or ma.% .S • • Wei Lin Presentation * Oct 8::: /T#e part o' t#e presentation regarding C.sil$er tec#nologies%com """%-ilin-%com -12.–www.le cons!mer% Programma)le logic c#ips* "#ic# are arrays o' memory cells t#at can )e programmed to per'orm #ard"are '!nctions !sing so't"are tools* are more 'le-i)le t#an D.FREE TECHNICAL PAPER DOWNLOAD –www.e a recording% 4!st t#in.8::: is co$ered in t#is page1 IEEE con'erence on Tele comm!nication* 8::.Newtechpapers.Newtechpapers.