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All Logic Gates (Gate Level modelling) module all_logic_gate_level(or_out,and_out,xor_out,not_out,nand_out,nor_out,xnor_out,x,y); input x,y; output or_out,and_out,xor_out,not_out,nand_out,nor_out,xnor_out; or g1(or_out,x,y); and g2(and_out,x,y);

xor g3(xor_out,x,y); not g4(not_out,x); nand g5(nand_out,x,y); nor g6(nor_out,x,y); xnor g7(xnor_out,x,y); endmodule All Logic Gates (Dataflow modelling) module all_logic_dataflow(or_out,and_out,xor_out,not_out,nand_out,nor_out,xnor_out,x,y); input x,y; output or_out,and_out,xor_out,not_out,nand_out,nor_out,xnor_out; assign or_out = x|y; assign and_out = x&y; assign xor_out = x^y; assign not_out = ~x; assign nand_out = ~(x&y); assign nor_out = ~ (x|y); assign xnor_out = ~(x^y); endmodule