You are on page 1of 5

KKKC6024

1

Instruction: Answer ALL questions (100 marks). (SOLUTION)

1. a) In general, the MOS transistor is considered to be a three-terminal gate with drain,
source, and gate ports. But in reality, the MOS transistor has a fourth terminal that is
connected to a dc supply depending on the transistor type. What is the name of the
fourth terminal? Where is this terminal connected to for NMOS and PMOS
transistors?
(10 marks)
The fourth terminal is called the substrate. This terminal is connected to GND for
NMOS and VDD for PMOS. The fourth terminal is often not shown in schematics
and is assumed to be connected to the appropriate supply.

b) Differentiate between bipolar and MOS transistors in terms of definition, function,
and advantages/disadvantages.
(15 marks)
Bipolar MOS
npn, pnp NMOS, PMOS
Small current into very thin base layer
controls large currents between emitter and
collector
Voltage applied to insulated gate
controls current between source and
drain
Base currents limit integration density Low power allows very high
integration

c) A junction between a p-type and n-type semiconductor forms a diode, which is the
basic foundation of a MOS transistor. With the help of a p-n junction diagram and
also a MOS transistor cross-section diagram, explain how the working function of a
simple diode contributes to the formation of a MOS transistor.
(25 marks)




Figure 1 Figure 2
Figure 1 shows a p-n junction that forms a diode. The p-type silicone material has free
holes moving around while the n-type has free electrons. When a positive voltage is
applied at the p-type material, holes are repelled from the positive voltage, towards
the junction, and electrons are attracted towards the junction. This in turn created a
p-type n-type
anode
cathode
n+
p
Gate Source Drain
bulk Si
SiO
2
Polysilicon
n+
D
1
S
KKKC6024
2

flow of electrons (current) in the p-n diode, where the flow of current is opposite of
the flow of electrons. Using this fundamental knowledge, the p-n junction is applied
to the MOS transistor where there exist 2 different p-n junctions (n-p and p-n). When
a positive voltage is applied to the Gate of the MOS transistor, then same
phenomenon happened which result in current flow from Drain to Source.


2. In IC design, a multiplexer chooses one of many inputs to steer to its single output
under the direction of its control inputs.

a) Recall the design of a 2:1 multiplexer. Write down the Boolean equation, and then
present the gate-level design of a 2:1 mux. How many transistors are needed?
(15 marks)

̅

, 20 transistors



















4
4
D1
D0
S
Y
4
2
2
2
Y
2
D1
D0
S
KKKC6024
3

b) A non-restoring mux can be constructed using transmission gates. Draw the circuit
of a non-restoring mux using only transmission gates. How many transistors are
needed?
(15 marks)
4 transistors















c) What’s the difference between a D latch and D flip-flop? Explain with reasoning
how you would design a D latch using minimum transistors.
(20 marks)
D latch:
 When CLK = 1, latch is transparent
 Q follows D (a buffer with a Delay)
 When CLK = 0, the latch is opaque
 Q holds its last value independent of D
 a.k.a. transparent latch or level-sensitive latch

D flip-flop:
 When CLK rises, D is copied to Q
 At all other times, Q holds its value
 a.k.a. positive edge-triggered flip-flop, master-slave flip-flop










S
S
D0
D1
Y S
D
CLK
Q
D
CLK
Q
KKKC6024
4












From the basic design of a D flip-flop, it can be seen that it requires a 2:1 mux.
This 2:1 mux can be implemented with minimum transistors by using
transmission gate mux with only 4 transistors.




‘SELAMAT MAJU JAYA’












1
0
D
CLK
Q
CLK
CLK
CLK
CLK
D
Q
Q
Q
KKKC6024
5

APPENDIX
Formula sheet
( )
f SB f to t
V V V | | ¸ 2 2 ÷ + + =

I
DS_linear
=
DS
DS
t GS n
V
V
V V
L
W
k |
.
|

\
|
÷ ÷
2
'

I
DS_saturation
= ( )
2
'
2
1
t GS n
V V
L
W
k ÷

ox n
C k µ = '

r
rV
V
DD
M
+
~
1
, for large values of V
DD


DSATn n
DSATp p
V k
V k
r =







( )
g
V
g
V V
V V
DD OL OH
IL IH
÷
=
÷
÷ = ÷


g
V V
V V
M DD
M IL
÷
+ =

IH DD MH
V V N ÷ =
IL ML
V N =


p n
DSATp p DSATn n
M D
V k V k
V I
g
ì ì ÷
+
÷ =
) (
1




g
V
V V
M
M IH
÷ =
L
W
k k
n n
' =
L
W
k k
p p
' =