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EC-2254 LINEAR INTEGRATED CIRUITS

II YEAR / IV SEMESTER ECE SUBJECT NOTES
SYLLABUS
EC 2254 LINEAR INTEGRATED CIRCUITS 3 0 0 3

AIM: To teach the basic concepts in the design of electronic circuits using linear integrated circuits and their applications in the processing of analog signals. OBJECTIVES • To introduce the basic building blocks of linear integrated circuits. • To teach the linear and non-linear applications of operational amplifiers. • To introduce the theory and applications of analog multipliers and PLL. • To teach the theory of ADC and DAC • To introduce the concepts of waveform generation and introduce some special function Cs. UNIT - I IC FABRICATION AND CIRCUIT CONFIGURATION FOR LINEAR ICS 9 Advantages of Cs over discrete components ! "anufacturing process of monolithic cs ! Construction of monolithic bipolar transistor ! "onolithic diodes ! ntegrated #esistors ! "onolithic Capacitors ! nductors. Current mirror and current sources$ Current sources as active loads$ %oltage sources$ %oltage #eferences$ &'T Differential amplifier with active loads$ (eneral operational amplifier stages -and internal circuit diagrams of C )*+$ DC and AC performance characteristics$ slew rate$ ,pen and closed loop configurations. UNIT - II APPLICATIONS OF OPERATIONAL AMPLIFIERS 9 -ign Changer$ -cale Changer$ Phase -hift Circuits$ %oltage .ollower$ %-to- and -to-% converters$ adder$ subtractor$ nstrumentation amplifier$ ntegrator$ Differentiator$ Logarithmic amplifier$ Antilogarithmic amplifier$ Comparators$ -chmitt trigger$ Precision rectifier$ peak detector$ clipper and clamper$ Low-pass$ high-pass and band-pass &utterworth filters. UNIT - III ANALOG MULTIPLIER AND PLL 9 Analog "ultiplier using /mitter Coupled Transistor Pair - (ilbert "ultiplier cell - %ariable transconductance techni0ue$ analog multiplier Cs and their applications$ ,peration of the basic PLL$ Closed loop analysis$ %oltage controlled oscillator$ "onolithic PLL C 121$ application of PLL for A" detection$ ." detection$ .-3 modulation and demodulation and .re0uency synthesi4ing. UNIT - IV ANALOG TO DIGITAL AND DIGITAL TO ANALOG CONVERTERS 8

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Analog and Digital Data Conversions$ D5A converter ! specifications - weighted resistor type$ #-6# Ladder type$ %oltage "ode and Current-"ode R − 2 R Ladder types - switches for D5A converters$ high speed sample-and-hold circuits$ A5D Converters ! specifications - .lash type - -uccessive Appro7imation type -ingle -lope type - Dual -lope type - A5D Converter using %oltage-to-Time Conversion - ,ver-sampling A5D Converters. UNIT - V AVEFORM GENERATORS AND SPECIAL FUNCTION IC! 9 -ine-wave generators$ "ultivibrators and Triangular wave generator$ -aw-tooth wave generator$ CL89:8 function generator$ Timer C 111$ C %oltage regulators - Three terminal fi7ed and ad;ustable voltage regulators - C )6: general purpose regulator - "onolithic switching regulator$ -witched capacitor filter C ".+9$ .re0uency to %oltage and %oltage to .re0uency converters$ Audio Power amplifier$ %ideo Amplifier$ solation Amplifier$ ,pto-couplers and fibre optic C. TOTAL : 45 PERIODS TE"T BOO#S: +. -ergio .ranco$ Design with operational amplifiers and analog integrated circuits$ : rd /dition$ Tata "c(raw-<ill$ 699). 6. D.#oy Choudhry$ -hail 'ain$ Linear ntegrated Circuits$ =ew Age nternational Pvt. Ltd.$ 6999. REFERENCES: +. &.-.-onde$ -ystem design using ntegrated Circuits $ =ew Age Pub$ 6nd /dition$ 699+ 6. (ray and "eyer$ Analysis and Design of Analog ntegrated Circuits$ >iley nternational$ 6991. :. #amakant A.(ayakwad$ ,P-A"P and Linear Cs$ Prentice <all 5 Pearson /ducation$ * th /dition$ 699+. *. '."ichael 'acob$ Applications and Design with Analog ntegrated Circuits$ Prentice <all of ndia$ +??2. 1. >illiam D.-tanley$ ,perational Amplifiers with Linear ntegrated Circuits$ Pearson /ducation$ 699*. 2. 3 Lal 3ishore$ ,perational Amplifier and Linear ntegrated Circuits$ Pearson /ducation$ 6992. ). -.-alivahanan @ %.-. 3anchana &haskaran$ Linear ntegrated Circuits$ T"<$ 6998.

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UNIT -I IC FABRICATION AND CIRCUIT CONFIGURATION FOR LINEAR IC! I$%&'()%&* C+(,-+%!:

An integrated circuit A CB is a miniature$ low cost electronic circuit consisting of active and passive components fabricated together on a single crystal of silicon. The active components are transistors and diodes and passive components are resistors and capacitors. A*.)$%)'&! /0 +$%&'()%&* ,+(,-+%!: "iniaturi4ation and hence increased e0uipment density. Cost reduction due to batch processing. ncreased system reliability due to the elimination of soldered ;oints. mproved functional performance. "atched devices. ncreased operating speeds. #eduction in power consumption C1)!!+0+,)%+/$: ntegrated circuits can be classified into analog$ digital and mi7ed signal Aboth analog and digital on the same chipB. &ased upon above re0uirement two different C technology namely "onolithic Technology and <ybrid Technology have been developed. n monolithic C $all circuit components $both active and passive elements and their interconnections are manufactured into or on top of a single chip of silicon. n hybrid circuits$ separate component parts are attached to a ceramic substrate and interconnected by means of either metalli4ation pattern or wire bounds.

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Digital integrated circuits can contain anything from one to millions of logic gates$ flip-flops$ multiple7ers$ and other circuits in a few s0uare millimeters. The small si4e of these circuits allows high speed$ low power dissipation$ and reduced manufacturing cost compared with board-level integration. These digital Cs$ typically microprocessors$ D-Ps$ and micro controllers work using binary mathematics to process ConeC and C4eroC signals. Analog Cs$ such as sensors$ power management circuits$ and operational amplifiers$ work by processing continuous signals. They perform functions like amplification$ active filtering$ demodulation$ mi7ing$ etc. Analog Cs ease the burden on circuit designers by having e7pertly designed analog circuits available instead of designing a difficult analog circuit from scratch. Cs can also combine analog and digital circuits on a single chip to create functions such as A5D converters and D5A converters. -uch circuits offer smaller si4e and lower cost$ but must carefully account for signal interference C1)!!+0+,)%+/$ /0 IC!: ntegrated Circuits

"onolithic Circuits

<ybrid Circuits

&ipolar

Dnipolar

p-n ;unction solation

Dielectric solation

",-./T

'./T

*

G&$&()%+/$! SSI2 MSI )$* LSI The first integrated circuits contained only a few transistors. Called C-mall--cale ntegrationC A-- B$ digital circuits containing transistors numbering in the tens provided a few logic gates for e7ample$ while early linear Cs such as the Plessey -L69+ or the Philips TAA:69 had as few as two transistors. The term Large -cale ntegration was first used by &" scientist #olf Landauer when describing the theoretical concept$ from there came the terms for -- $ "- $ %L- $ and DL- . They began to appear in consumer products at the turn of the decade$ a typical application being ." inter-carrier sound processing in television receivers. The ne7t step in the development of integrated circuits$ taken in the late +?29s$ introduced devices which contained hundreds of transistors on each chip$ called C"edium--cale ntegrationC A"- B. They were attractive economically because while they cost little more to produce than -- devices$ they allowed more comple7 systems to be produced using smaller circuit boards$ less assembly work Abecause of fewer separate componentsB$ and a number of other advantages. VLSI The final step in the development process$ starting in the +?89s and continuing through the present$ was Cvery large-scale integrationC A%L- B. The development started with hundreds of thousands of transistors in the early +?89s$ and continues beyond several billion transistors as of 699). n +?82 the first one megabit #A" chips were introduced$ which contained more than one million transistors. "icroprocessor chips passed the million transistor mark in +?8? and the billion transistor mark in 6991 ULSI2 SI2 SOC )$* 3D-IC

To reflect further growth of the comple7ity$ the term DL- that stands for CDltra-Large -cale ntegrationC was proposed for chips of comple7ity of more than + million transistors. 1

>afer-scale integration A>- B is a system of building very-large integrated circuits that uses an entire silicon wafer to produce a single Csuper-chipC. Through a combination of large si4e and reduced packaging$ >- could lead to dramatically reduced costs for some systems$ notably massively parallel supercomputers. The name is taken from the term %ery-Large--cale ntegration$ the current state of the art when >- was being developed. -ystem-on-a-Chip A-oC or -,CB is an integrated circuit in which all the components needed for a computer or other system are included on a single chip. The design of such a device can be comple7 and costly$ and building disparate components on a single piece of silicon may compromise the efficiency of some elements. <owever$ these drawbacks are offset by lower manufacturing and assembly costs and by a greatly reduced power budgetE because signals among the components are kept on-die$ much less power is re0uire. Three Dimensional ntegrated Circuit A:D- CB has two or more layers of active electronic components that are integrated both vertically and hori4ontally into a single circuit. Communication between layers uses on-die signaling$ so power consumption is much lower than in e0uivalent separate circuits. 'udicious use of short vertical wires can substantially reduce overall wire length for faster operation.

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C/$!%(-,%+/$ /0 ) M/$/1+%3+, B+4/1)( T()$!+!%/(: The fabrication of a monolithic transistor includes the following steps. +. /pita7ial growth 6. ,7idation :. Photolithography *. solation diffusion 1. &ase diffusion 2. /mitter diffusion ). Contact mask 8. Aluminium metalli4ation ?. Passivation The letters P and = in the figures refer to type of doping$ and a minus A-B or plus AFB with P and = indicates lighter or heavier doping respectively. 56 E4+%)7+)1 '(/8%3: The first step in transistor fabrication is creation of the collector region. >e normally re0uire a low resistivity path for the collector current. This is due to the fact that$ the collector contact is normally taken at the top$ thus increasing the collector series resistance and the % C/A-atB of the device.

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The higher collector resistance is reduced by a process called buried layer as shown in figure. n this arrangement$ a heavily doped G=H region is sandwiched between the =-type epita7ial layer and P ! type substrate. This buried =F layer provides a low resistance path in the active collector region to the collector contact C. n effect$ the buried layer provides a low resistance shunt path for the flow of current. .or fabricating an =P= transistor$ we begin with a P-type silicon substrate having a resistivity of typically +I-cm$ corresponding to an acceptor ion concentration of +.* J +9 +1 atoms5cm: . An o7ide mask with the necessary pattern for buried layer diffusion is prepared. This is followed by masking and etching the o7ide in the buried layer mask. The =-type buried layer is now diffused into the substrate. A slow-diffusing material such as arsenic or antimony us used$ so that the buried layer will stay-put during subse0uent diffusions. The ;unction depth is typically a few microns$ with sheet resistivity of around 69I per s0uare. Then$ an epita7ial layer of lightly doped =-silicon is grown on the P-type substrate by placing the wafer in the furnace at +699 9 C and introducing a gas containing phosphorus Adonor impurityB. The resulting structure is shown in figure. The subse0uent diffusions are done in this epita7ial layer. All active and passive components are formed on the thin =-layer epita7ial layer grown over the P-type substrate. ,btaining an epita7ial layer of the proper thickness and doping with high crystal 0uality is perhaps the most formidable challenge in bipolar device processing. 26 O7+*)%+/$:

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As shown in figure$ a thin layer of silicon dio7ide A-i, 6B is grown over the =-type layer by e7posing the silicon wafer to an o7ygen atmosphere at about +9999 C.

36 P3/%/1+%3/'()439:

The prime use of photolithography in C manufacturing is to selectively etch or remove the -i,6 layer. As shown in figure$ the surface of the o7ide is first covered with a thin uniform layer of photosensitive emulsion APhoto resistB. The mask$ a black and white negative of the re0uied pattern$ is placed over the structure. >hen e7posed to ultraviolet light$ the photo resist under the transparent region of the mask becomes poly-meri4ed. The mask is then removed and the wafer is treated chemically that removes the une7posed portions of the photoresist film. The polymeri4ed region is cured so that it becomes resistant to corrosion. Then the chip is dipped in an etching solution of hydrofluoric acid which removes the o7ide layer not protected by the polymeri4ed ?

photoresist. This creates openings in the -i, 6 layer through which P-type or =-type impurities can be diffused using the isolation diffusion process as shown in figure. After diffusion of impurities$ the polymeri4ed photoresist is removed with sulphuric acid and by a mechanical abrasion process. 46 I!/1)%+/$ D+00-!+/$: The integrated circuit contains many devices. -ince a number of devices are to be fabricated on the same C chip$ it becomes necessary to provide good isolation between various components and their interconnections. The most important techni0ues for isolation areE +. P= ;unction solation 6. Dielectric solation n P= ;unction isolation techni0ue$ the PF type impurities are selectively diffused into the =-type epita7ial layer so that it touches the P-type substrate at the bottom. This method generated =-type isolation regions surrounded by P-type moats. f the P-substrate is held at the most negative potential$ the diodes will become reverse-biased$ thus providing isolation between these islands. The individual components are fabricated inside these islands. This method is very economical$ and is the most commonly used isolation method for general purpose integrated circuits. n dielectric isolation method$ a layer of solid dielectric such as silicon dio7ide or ruby surrounds each component and this dielectric provides isolation. The isolation is both physical and electrical. This method is very e7pensive due to additional processing steps needed and this is mostly used for fabricating CHs re0uired for special application in military and aerospace. The P= ;unction isolation diffusion method is shown in figure. The process take place in a furnace using boron source. The diffusion depth must be atleast e0ual to the epita7ial thickness in order to obtain complete isolation. Poor isolation results in device failures as all transistors might get shorted together. The =-type island shown in figure forms the collector region of the =P= transistor. The heavily doped P-type regions marked PF are the isolation regions for the active and passive components that will be formed in the various =-type islands of the epita7ial layer. 5 B)!& *+00-!+/$: .ormation of the base is a critical step in the construction of a bipolar transistor. The base must be aligned$ so that$ during diffusion$ it does not come into contact with either the isolation region or the buried layer. .re0uently$ the base diffusion step is also used in parallel to fabricate diffused resistors for the circuit. The value of these resistors depends on the diffusion conditions and the +9

width of the opening made during etching. The base width influences the transistor parameters very strongly. Therefore$ the base ;unction depth and resistivity must be tightly controlled. The base sheet resistivity should be fairly high A699- 199I per s0uareB so that the base does not in;ect carriers into the emitter. .or =P= transistor$ the base is diffused in a furnace using a boron source. The diffusion process is done in two steps$ pre deposition of dopants at ?99 9 C and driving them in at about +6999 C. The drive-in is done in an o7idi4ing ambience$ so that o7ide is grown over the base region for subse0uent fabrication steps. .igure shows that P-type base region of the transistor diffused in the =-type island Acollector regionB using photolithography and isolation diffusion processes. :6 E;+%%&( D+00-!+/$: /mitter Diffusion is the final step in the fabrication of the transistor. The emitter opening must lie wholly within the base. /mitter masking not only opens windows for the emitter$ but also for the contact point$ which provides a low resistivity ohmic contact path for the emitter terminal. The emitter diffusion is normally a heavy =-type diffusion$ producing low-resistivity layer that can in;ect charge easily into the base. A Phosphorus source is commonly used so that the diffusion time id shortened and the previous layers do not diffuse further. The emitter is diffused into the base$ so that the emitter ;unction depth very closely approaches the base ;unction depth. The active base is then a P-region between these two ;unctions which can be made very narrow by ad;usting the emitter diffusion time. %arious diffusion and drive in cycles can be used to fabricate the emitter. The #esistivity of the emitter is usually not too critical. The =-type emitter region of the transistor diffused into the P-type base region is shown below. <owever$ this is not needed to fabricate a resistor where the resistivity of the P-type base region itself will serve the purpose. n this way$ an =P= transistor and a resistor are fabricated simultaneously. <6 C/$%),% M)!=: After the fabrication of emitter$ windows are etched into the =-type regions where contacts are to be made for collector and emitter terminals. <eavily concentrated phosphorus =F dopant is diffused into these regions simultaneously. The reasons for the use of heavy =F diffusion is e7plained as followsE Aluminium$ being a good conductor used for interconnection$ is a P-type of impurity when used with silicon. Therefore$ it can produce an unwanted diode or rectifying contact with the lightly doped =++

material. ntroducing a high concentration of =F dopant caused the -i lattice at the surface semimetallic. Thus the =F layer makes a very good ohmic contact with the Aluminium layer. This is done by the o7idation$ photolithography and isolation diffusion processes. 86 M&%)11+>)%+/$: The C chip is now complete with the active and passive devices$ and the metal leads are to be formed for making connections with the terminals of the devices. Aluminium is deposited over the entire wafer by vacuum deposition. The thickness for single layer metal is +K m. "etalli4ation is carried out by evaporating aluminium over the entire surface and then selectively etching away aluminium to leave behind the desired interconnection and bonding pads as shown in figure. "etalli4ation is done for making interconnection between the various components fabricated in an C and providing bonding pads around the circumference of the C chip for later connection of wires . 96 P)!!+.)%+/$/ A!!&;?19 )$* P),=)'+$': "etalli4ation is followed by passivation$ in which an insulating and protective layer is deposited over the whole device. This protects it against mechanical and chemical damage during subse0uent processing steps. Doped or undoped silicon o7ide or silicon nitride$ or some combination of them$ are usually chosen for passivation of layers. The layer is deposited by chemical vapour deposition AC%DB techni0ue at a temperature low enough not to harm the metalli4ation. T()$!+!%/( F)?(+,)%+/$: P=P TransistorE The integrated P=P transistors are fabricated in one of the following three structures. +. -ubstrate or %ertical P=P 6. Lateral or hori4ontal P=P and :. Triple diffused P=P -ubstrate or %ertical P=PE +6

The P-substrate of the C is used as the collector$ the =-epita7ial layer is used as the base and the ne7t P-diffusion is used as the emitter region of the P=P transistor. The structure of a vertical monolithic P=P transistor L+ is shown in figure. The base region of an =P= transistor structure is formed in parallel with the emitter region of the P=P transistor. The method of fabrication has the disadvantage of having its collector held at a fi7ed negative potential. This is due to the fact that the P-substrate of the C is always held at a negative potential normally for providing good isolation between the circuit components and the substrate. Triple diffused P=PE This type of P=P transistor is formed by including an additional diffusion process over the standard =P= transistor processing steps. This is called a triple diffusion process$ because it involves an additional diffusion of P-region in the second =-diffusion region of a =P= transistor. The structure of the triple diffused monolithic P=P transistor L 6 is also shown in the below figure. This has the limitations of re0uiring additional fabrication steps and sophisticated fabrication assemblies. L)%&()1 /( @/(+>/$%)1 PNP: This is the most commonly used form of integrated P=P transistor fabrication method. This has the advantage that it can be fabricated simultaneously with the processing steps of an =P= transistor and therefore it re0uires as the base of the P=P transistor. During the P-type base diffusion process of =P= transistor$ two parallel P-regions are formed which make the emitter and collector regions of the hori4ontal P=P transistor.

Comparison of monolithic =P= and P=P transistorE +:

=ormally$ the =P= transistor is preferred in monolithic circuits due to the following reasonsE +. The vertical P=P transistor must have his collector held at a fi7ed negative voltage. 6. The lateral P=P transistor has very wide base region and has the limitation due to the lateral diffusion of P-type impurities into the =-type base region. This makes the photographic mask making$ alignment and etching processes very difficult. This reduces the current gain of lateral P=P transistors as low as +.1 to :9 as against 19 to :99 for a monolithic =P= transistor. :. The collector region is formed prior to the formation of base and emitter diffusion. During the later diffusion steps$ the collector impurities diffuse on either side of the defined collector ;unction. -ince the =-type impurities have smaller diffusion constant compared to P-type impurities the =type collector performs better than the P-type collector. This makes the =P= transistor preferable for monolithic fabrication due to the easier process control. Transistor with multiple emittersE The applications such as transistor- transistor logic ATTLB re0uire multiple emitters. The below figure shows the circuit sectional view of three =-emitter regions diffused in three places inside the P-type base. This arrangement saves the chip area and enhances the component density of the C.

+*

S,3/%%=9 B)((+&( D+/*&:

The metal contacts are re0uired to be ohmic and no P= ;unctions to be formed between the metal and silicon layers. The =F diffusion region serves the purpose of generating ohmic contacts. ,n the other hand$ if aluminium is deposited directly on the =-type silicon$ then a metal semiconductor diode can be said to be formed. -uch a metal semiconductor diode ;unction e7hibits the same type of %- Characteristics as that of an ordinary P= ;unction.

+1

The cross sectional view and symbol of a -chottky barrier diode as shown in figure. Contact + shown in figure is a -chottky barrier and the contact 6 is an ohmic contact. The contact potential between the semiconductor and the metal generated a barrier for the flow of conducting electrons from semiconductor to metal. >hen the ;unction is forward biased this barrier is lowered and the electron flow is allowed from semiconductor to metal$ where the electrons are in large 0uantities. The minority carriers carry the conduction current in the -chottky diode whereas in the P= ;unction diode$ minority carriers carry the conduction current and it incurs an appreciable time delay from ,= state to ,.. state. This is due to the fact that the minority carriers stored in the ;unction have to be totally removed. This characteristic puts the -chottky barrier diode at an advantage since it e7hibits negligible time to flow the electron from =-type silicon into aluminum almost right at the contact surface$ where they mi7 with the free electrons. The other advantage of this diode is that it has less forward voltage Aappro7imately 9.*%B. Thus it can be used for clamping and detection in high fre0uency applications and microwave integrated circuits. S,3/%%=9 %()$!+!%/(:

The cross-sectional view of a transistor employing a -chottky barrier diode clamped between its base and collector regions is shown in figure. The e0uivalent circuit and the symbolic representation of the -chottky transistor are shown in figure. The -chottky diode is formed by allowing aluminium metalli4ation for the base lead which makes contact with the =-type collector region also as shown in figure.

+2

>hen the base current is increased to saturate the transistor$ the voltage at the collector C reduces and this makes the diode Ds conduct. The base to collector voltage reduces to 9.*%$ which is less the cut-in-voltage of a silicon base-collector ;unction. Therefore$ the transistor does not get saturated. M/$/1+%3+, *+/*&!: The diode used in integrated circuits are made using transistor structures in one of the five possible connections. The three most popular structures are shown in figure. The diode is obtained from a transistor structure using one of the following structures. +. The emitter-base diode$ with collector short circuited to the base. 6. The emitter-base diode with the collector open and :. The collector !base diode$ with the emitter open-circuited. The choice of the diode structure depends on the performance and application desired. Collectorbase diodes have higher collector-base arrays breaking rating$ and they are suitable for commoncathode diode arrays diffused within a single isolation island. The emitter-base diffusion is very popular for the fabrication of diodes$ provided the reverse-voltage re0uirement of the circuit does not e7ceed the lower base-emitter breakdown voltage.

+)

I$%&'()%&* R&!+!%/(!: A resistor in a monolithic integrated circuit is obtained by utili4ing the bulk resistivity of the diffused volume of semiconductor region. The commonly used methods for fabricating integrated resistors are +. Diffused 6. epita7ial :. Pinched and *. Thin film techni0ues. D+00-!&* R&!+!%/(: The diffused resistor is formed in any one of the isolated regions of epita7ial layer during base or emitter diffusion processes. This type of resistor fabrication is very economical as it runs in parallel to the bipolar transistor fabrication. The =-type emitter diffusion and P-type base diffusion are commonly used to reali4e the monolithic resistor. The diffused resistor has a severe limitation in that$ only small valued resistors can be fabricated. The surface geometry such as the length$ width and the diffused impurity profile determine the resistance value. The commonly used parameter for defining this resistance is called the sheet resistance. t is defined as the resistance in ohms5s0uare offered by the diffused area. n the monolithic resistor$ the resistance value is e7pressed by # M #s +5w where #M resistance offered Ain ohmsB #s M sheet resistance of the particular fabrication process involved Ain ohms5s0uareB +8

l M length of the diffused area and w M width of the diffused area. The sheet resistance of the base and emitter diffusion in 699I5-0uare and 6.6I5s0uare respectively. .or e7ample$ an emitter-diffused strip of 6mil wide and 69 mil long will offer a resistance of 66I. .or higher values of resistance$ the diffusion region can be formed in a 4ig-4ag fashion resulting in larger effective length. The poly silicon layer can also be used for resistor reali4ation. E4+%)7+)1 R&!+!%/(:

The =-epita7ial layer can be used for reali4ing large resistance values. The figure shows the crosssectional view of the epita7ial resistor formed in the epita7ial layer between the two = F aluminium metal contacts. P+$,3&* (&!+!%/(:

The sheet resistance offered by the diffusion regions can be increased by narrowing down its cross-sectional area. This type of resistance is normally achieved in the base region. .igure shows a pinched base diffused resistor. t can offer resistance of the order of mega ohms in a comparatively smaller area. n the structure shown$ no current can flow in the =-type material +?

since the diode reali4ed at contact 6 is biased in reversed direction. ,nly very small reverse saturation current can flow in conduction path for the current has been reduced or pinched. Therefore$ the resistance between the contact + and 6 increases as the width narrows down and hence it acts as a pinched resistor. T3+$ 0+1; (&!+!%/(:

The thin film deposition techni0ue can also be used for the fabrication of monolithic resistors. A very thin metallic film of thickness less than +Km is deposited on the silicon dio7ide layer by vapour deposition techni0ues. =ormally$ =ichrome A=iCrB is used for this process. Desired geometry is achieved using masked etching processes to obtain suitable value of resistors. ,hmic contacts are made using aluminium metalli4ation as discussed in earlier sections. The cross-sectional view of a thin film resistor as shown in figure. -heet resistances of *9 to *99I5 s0uare can be easily obtained in this method and thus 69kI to 19kI values are very practical. The advantages of thin film resistors are as followsE +. They have smaller parasitic components which makes their high fre0uency behaviour good. 6. The thin film resistor values can be very minutely controlled using laser trimming. :. They have low temperature coefficient of resistance and this makes them more stable. The thin film resistor can be obtained by the use of tantalum deposited over silicon dio7ide layer. The main disadvantage of thin film resistor is that its fabrication re0uires additional processing steps. 69

M/$/1+%3+, C)4),+%/(!:

"onolithic capacitors are not fre0uently used in integrated circuits since they are limited in the range of values obtained and their performance. There are$ however$ two types available$ the ;unction capacitor is a reverse biased P= ;unction formed by the collector-base or emitter-base diffusion of the transistor. The capacitance is proportional to the area of the ;unction and inversely proportional to the depletion thickness. C N A$ where a is the area of the ;unction and C N T $ where t is the thickness of the depletion layer. The capacitance value thus obtainable can be around +.6n.5mm6 . The thin film or metal o7ide silicon capacitor uses a thin layer of silicon dio7ide as the dielectric. ,ne plate is the connecting metal and the other is a heavily doped layer of silicon$ which is formed during the emitter diffusion. This capacitor has a lower leakage current and is nondirectional$ since emitter plate can be biased positively. The capacitance value of this method can be varied between 9.: and 9.8n.5mm6 . I$*-,%/(!: =o satisfactory integrated inductors e7ist. f high L inductors with inductance of values larger than 1K< are re0uired$ they are usually supplied by a wound inductor which is connected e7ternally to the chip. Therefore$ the use of inductors is normally avoided when integrated circuits are used.

6+

CURRENT MIRROR AND CURRENT SOURCES: C/$!%)$% ,-((&$% !/-(,&AC-((&$% M+((/(B: A constant current source makes use of the fact that for a transistor in the active mode of operation$ the collector current is relatively independent of the collector voltage. n the basic circuit shown in fig +

Transistors L+@L6 are matched as the circuit is fabricated using C technology. &ase and emitter of L+@L6 are tied together and thus have the same %&/. . n addition$ transistor L+ is connected as a diode by shorting it s collector to base. The input current diode connected transistor L+ and thus establishes a voltage across L+. This voltage in turn appears between the base and emitter of L 6 .-ince L6 is identical to L+$ the emitter current of L6 will be e0ual to emitter current of L+ which is appro7imately e0ual to
ref ref

flows through the

As long as L6 is maintained in the active region $its collector current appro7imately e0ual to
ref . ref

C6M o

will be

-ince the output current o is a reflection or mirror of the reference current often referred to as a current mirror. A$)19!+!: The collector current e7pressed as IC5 t α I e F ES IC2 t α I e F ES
V
BE + ffffffffffff VT

$ the circuit is

C+

and

C6

for the transistor L+ and L6 can be appro7imately

---------A5B

V

BE 6 fffffffffffff VT

------------A2B

.rom e0uation A+B@A6B 66

f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f BE 6 BE + Iff f f f f f f f C 6 -----------------A3B = e VT I C+

V

@V

-ince %&/+M%&/6 we obtain C6M C+M CM , Also since both the transistors are identical $ β+ =β 6 = β 3CL at the collector of L+ gives refM C+F &+F &6 f g Iff 6 f ff f f f If f f f f f f f f f f f C + C 6 = I C+ + + = IC + + β+ β 6 β ----------A*B solving /0 A*B. β f f ff f f ff f f ff f f ff I ------------A1B β + 6 ref >here ref from fig can be seen to be V V f f f f f f f f f f f f f f f f f f f f f f f f I ref = V CC @ BE OO CC Aas %&/M9.)% is smallB R+ R+ β f f f f f f f f f f f f f f f f .rom /0.1 for β PP+, is almost unity and the output current 9 is e0ual to the reference β+6 current$ ref which for a given #+ is constant. Typically o varies by about :Q for 19 R β R699. IC = t is possible to obtain current transfer ratio other than unity simple by controlling the area of the emitter-base ;unction A/&'B of the transistor L 6 . .or e7ample$ if the area of /&' of L 6 is * times that of L+$then M* I ref The output resistance of the current source is the output resistance$r9 of L6$ V V f f f f f f f f f f f f f f f f f f f A A #9M 96M OM I S%A is the /arly voltageT IO ref The circuit however operates as a constant current source as long as L 6 remains in the active region.
, C

may be e7pressed as

6:

+*1)( ,-((&$% !/-(,&: >idlar current source which is particularly suitable for low value of currents. The circuit differs from the basic current mirror only in the resistance # / that is included in the emitter lead of L6. t can be seen that due to #/ the base-emitter voltage %&/6 is les than %&/+ and conse0uently current o is smaller than
C+

The ratio of collector currents C+@ C6 using V @ V f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f BE 6 BE + Iff f f f f f f f C 6 VT ------------A5B =e I C+ Taking natural logarithm of both sides$ we get h i Iff f f f f f f C + k -------A2B VBE5-VBE2CVT lnj I C6 >riting 3%L for the emitter base loop %&/+M%&/6FA or
&6

F

C6

B#/ ----------------A:B
C6

%&/+-%&/6MA+5 β F+B

#/ -----------A*B

.rom e0n A6B@A*B we obtain f g IC + f f f f f f f f f f + + + I c6 RE = V T ln ff --------------A5B β I C6 O( V f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f If f f f f f f T C + e RE = d ln f I + C6 --------------A:B + + ffff I C6
β

A relation between collector point of L+
ref

C+

and the reference current

ref

is obtained by writing 3CL at the

M

C+

F

&+

F

&6

6*

IC + ff f f f f f f f f 6 + ff C I C+ + + ----------------A<B β β AAssuming β 6 =β+ = β for identical transistorsB n the >idlar current source
f
C6

f

g

UU

C+

$therefore the term

+ f f f f Thus I ref t I C+ + + β β f f f f f f f f f f f f f f f f I C+M β + + ref V @ V cc f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f BE >here I ref = R+ t I .or β PP+ C+ I ref +1!/$ ,-((&$% !/-(,&: The >ilson current source shown in fig

g

Iff f f f f f f C 6 may be neglected in A)B β

t provides an output current o$ which is very nearly e0ual to % high output resistance. A$)19!+!: -ince %&/+M%&/6 C+M C6 and At nodeHbH

ref

and also e7hibits a very

&+

M

&6

M

&

6 f f f f + + I C6 -----------A+B /:M6 & F C6M β /: is e0ual to f g + f f f f ++ β -----------A6B M F M
/: C: &: C:

f

g

.rom /0n A+B@A6B we obtain 61

+ 6 I C: + + ffff = I C6 + + ffff β β f g β + 6 f f f f f f f f f f f f f f f f I C: = I o = I β + + C6 -ince C+M C6 f g β+6 I o = ffffffffffffffff I C+ β++ At node GaH 6 β++ +ffff 6 β + 6 Io f f f f β f f f f f f f f f f f f f f f f f f f f f f I ref = I C+ + I B: = ffffffffffffffffI o + ff = ffffffffff Io 6 β+6 β β + 6β 6 β + 6 β f ff f f ff f f ff f f ff f f ff f f ff f f ff f f ff f f I o = fff6 I ref β + 6 β + 6 or V CC @ 6 V f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f BE I ref = ffff R+ where 6 f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f I ref is e7tremely small error for modest The difference I O @I ref = 6 β + 6β + 6 values of β d e rff f f f f o t β The output resistance of a >ilson current mirror is substantially greater 6 than simple current mirror or >idlar current mirror. C-((&$% !/-(,&! )! A,%+.& 1/)*!: The current source can be used as an active load in both analog and digital CHs. The active load reali4ed using current source in place of the passive load Ai.e. a resistorB in the collector arm of differential amplifier makes it possible to achieve high voltage gain without re0uiring large power supply voltage. The active load so achieved is basically r9 of a P=P transistor. V/1%)'& S/-(,&!: A voltage source is a circuit that produces an output voltage %9 $ which is independent of the load driven by the voltage source$ or the output current supplied to the load. The voltage source is the circuit dual of the constant current source. A number of C applications re0uire a voltage reference point with very low ac impedance and a stable dc voltage that is not affected by power supply and temperature variations. There are two methods which can be used to produce a voltage source$ namely$

f

g

f

g

62

+. using the impedance transforming properties of the transistor$ which in turn determines the current gain of the transistor and 6. using an amplifier with negative feedback. V/1%)'& !/-(,& ,+(,-+% -!+$' I;4&*)$,& %()$!0/(;)%+/$: The voltage source circuit using the impedance transforming property of the transistor is shown in figure. The source voltage % s drives the base of the transistor through a series resistance #- and the output is taken across the emitter. .rom the circuit$ the output ac resistance looking into emitter is given by dV RSffffffff f f f f f f f f f f f f f 9 = R9 = ffffffff +r dI 9 β + + eb RSffffffff with values as high as +99 forβ , RS is transfor ed to a value of ffffffff A β++

t is to be noted that$ e0n is applicable only for small changes in the output current. The load regulation parameter indicates the changes in %9 resulting from large changes in output current
9

$ #eduction in %9 occurs as

9

goes from no-load current to full-load current and this

factor determines the output impedance of the voltage sources.

6)

E;+%%&( D 0/11/8&( /( C/;;/$ C/11&,%/( T94& V/1%)'& !/-(,&: The figure shows an emitter follower or common collector type voltage source. This voltage source is suitable for the differential gain stage used in op-amps. This circuit has the advantages of +. Producing low ac impedance and 6. resulting in effective decoupling of ad;acent gain stages. The low output impedance of the common-collector stage simulates a low impedance voltage source with an output voltage level of %9 represented by R6 f f f f f f f f f f f k V 9 = V ccj fffffffffff R+ + R6 The diode D+ is used for offsetting the effect of dc value % &/ $ across the /-& ;unction of the transistor$ and for compensating the temperature dependence of % &/ drop of L+. The load VL shown in dotted line represents the circuit biased by the current through L+. The impedance #9 looking into the emitter of L+ derived from the hybrid W model is given by V fffff ffffffff R+ R f f f f f f f f f f f f f f f f f f f f f f 6 c R9 = ffffT + b ffff I+ β R + R
+ 6

h

i

V/1%)'& S/-(,& !-+$' T&;4&()%-(& ,/;4&$!)%&* A.)1)$,3& D+/*&: The voltage source using common collector stage has the limitations of its vulnerability for changes in bias voltage %= and the output voltage %9 with respect to changes in supply voltage %cc. This is overcome in the voltage source circuit using the breakdown voltage of the baseemitter ;unction shown below. 68

The emitter ! follower stage of common ! collector is eliminated in this circuit$ since the impedance seen looking into the bias terminal = is very low. The current source node = is given by %9 M %& F%&/ >here %& is the breakdown voltage of diode D & and %&/ is the diode drop across D+. The breakdown diode D& is normally reali4ed using the base-emitter ;unction of the transistor. The diode D+ provides partial compensation for the positive temperature coefficient effect of % &. n a monolithic C structure$ D& and D+ can be conveniently reali4ed as a single transistor with two individual emitters as shown in figure.
+

is normally

simulated by a resistor connected between %cc and node n. Then$ the output voltage level % 9 at

T&;4&()%-(& C/;4&$!)%&* ).)1)$,3& *+/*&

V/1%)'& !/-(,& -!+$' ?(&)=*/8$ ./1%)'& /0 %3& ?)!&- &;+%%&( E-$,%+/$

The structure consists of composite connection of two transistors which are diodeconnected back-to back. -ince the transistors have their base to collector terminals common$ they can be designed as a single transistor with two emitters. The output resistance #9 looking into the output terminal in figure is given by

6?

V f f f f f f f f f T >here #& and %T 5 + are the ac resistances of the base !emitter resistance of diode I+ D& and D+ respectively. Typically #& is in the range of *9I to +99I$ and %9 in the range of 2.1% to ?%. R9 = RB + V/1%)'& S/-(,& -!+$' VBE )! ) (&0&(&$,&: The output stage of op-amp re0uires stabili4ed bias voltage source$ which can be obtained using a forward-biased diode connected transistor. The forward voltage drop for such a connection is appro7imately 9.)%$ and it changes slightly with current. >hen a voltage level greater than 9.)%$ is needed$ several diodes can be connected in series$ which can offer integral multiples of 9.)%. Alternatively$ the figure shows a multiplier circuit$ which can offer voltage levels$ that need not be integral multiplied of 9.)%. The drop across #6 e0uals %&/ drop of L+. Considering negligible base current for L+ $ current through #6 is the same as that flowing through #+ . Therefore$ the output voltage %9 can be e7pressed as V 9 = I 6 R+ + R6
b c c V ffffffffb R+ f f f f k = ffffBE R+ + R6 = V BEj fff ++ R6 R6 h i

VBE ;-1%+41+&( C+(,-+% <ence$ the voltage %9 can be any multiple of %&/ by properly selecting the resistors #+ and #6 . Due to the shunt feedback provided by # +$ the transistor current towards maintaining
6 +

automatically ad;usts itself$

and %9 relatively independent of the changes in supply voltage.

The ac output resistance of the circuit #9 is given by$

:9

dV ffff ff R+fff+ R f f f f f f f f f f f f f f f f f f f 6 t fffff R9 = fffffffff9 dI o + + g R6

R+ + R + f f f f f f f f f f f f f f f f f f f f 6 when g R6 PP +, we have R9 = fff A fffffff R6 g !sing this e"n we have, V + R f f f f f f f f f f f f R f f f f f f f f f f f f f f f f f f f 9 + 6 = fff V BE R6 Therefore, V ffffff f V + f f f f f f f V f f f f f f f f f f f f f + R9 = ffffff9 = ffffff9 V BE g V BE I C

V/1%)'& R&0&(&$,&!: The circuit that is primarily designed for providing a constant voltage independent of changes in temperature is called a voltage reference. The most important characteristic of a voltage reference is the temperature coefficient of the output reference voltage TC# $ and it is e7pressed as

TC R =

The desirable properties of a voltage reference areE +. #eference voltage must be independent of any temperature change. 6. #eference voltage must have good power supply re;ection which is as independent of the supply voltage as possible and :. output voltage must be as independent of the loading of output current as possible$ or in other words$ the circuit should have low output impedance. The voltage reference circuit is used to bias the voltage source circuit$ and the combination can be called as the voltage regulator. The basic design strategy is producing a 4ero TC # at a given temperature$ and thereby achieving good thermal ability. Temperature stability of the order of +99ppm59 C is typically e7pected.

dV fffffffffff R dT

:+

V/1%)'& R&0&(&$,& ,+(,-+% -!+$' %&;4&()%-(& ,/;4&$!)%+/$ !,3&;&: The voltage reference circuit using basic temperature compensation scheme is shown below. This design utili4es the close thermal coupling achievable among the monolithic components and this techni0ue compensates the known thermal drifts by introducing an opposing and compensating drift source of e0ual magnitude.

:6

A constant current is supplied to the avalanche diode D& and it provides a bias voltage of %& to the base of L+. The temperature dependence of the %&/ drop across L+ and those across D+ and D6 results in respective temperature coefficients. <ence$ with the use of resistors # + and #6 with tapping across them at point = compensates for the temperature drifts in the base-emitter loop of L+ . This results in generating a voltage reference %# with normally 4ero temperature coefficient. Applying 3CL at node =$ we get

V B @V BE b# c @V BE b$ c @V R R+
Assuming matched transistors$
+ + 6

ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff + +

=

V R @V BE b$ c R6

fffffffffffffffffffffffffffffff 6

V BE b# c = V BE b$ c = V BE b$ c = V BE R+ = R6

Then /0 can be e7pressed as V V BE @V R V V BE ffffffffffffffffffffffffffffffffffffffff fffffffffffffffffffffff B @6 R@ Therefore$ the voltage given by blevel %# isc

VR = 9=

R 6 V B + V BE R+ @6 R 6 ffffffffffffffffffffffffffffffffffffffffffffffffffffffffff R+ + R 6 +

Differentiating %& and %&/ in e0A6B partially with respect to temperature$ we get G fffffffffffff R6 ∂ VB FR V BE ffffffffffffffffff fffffffffff ffffffffffffffffffffff + @6 R 6 ∂

R+ + R 6 ∂ T

R+ + R 6

∂T

That is$

∂T Therefore$ it can be inferred that e0A:B is to be satisfied for obtaining 4ero temperature coefficient.

6 R+ @R+ ffffffffffff fffffffffffffffffffff ∂T = ∂V R6 ffffffffffffffff BE

∂ VB ffffffffffffff

@@@ :

` a

V/1%)'& R&0&(&$,& ,+(,-+% -!+$' A.)1)$,3& D+/*& R&0&(&$,&: A voltage reference can be implemented using the brerakdown phenomenon condition of a heavily doped P= ;unction. The 4ener breakdown is the main mechanism for ;unctions$ which breakdown at a voltage of 1% or less. .or integrated transistors $ the base-emitter breakdown voltage falls in the range of 2 to 8%. Therefore$ the breakdown in the ;unctions of the integrated transistor is primarily due to avalanche multiplication. The avalanche breakdown voltage % & of a transistor incurs a positive temperature coefficient$ typically in the range of 6m%59 C to 1m%59 C.

::

.igure depicts a current reference circuit using avalanche diode reference. The base bias for transistor L+ is provided through register #+ and it also provides the dc current needed to bias D&$ D+ and D6 . The voltage at the base of L + is e0ual to the 4ener voltage % & added with two diode drops due to D+ and D6 . The voltage across #6 is e0ual to the voltage at the base of L+ less the sum of the base ! emitter voltages of L+ and L6 .

:*

<ence$ the voltage across #6 is appro7imately e0ual to that across D& M %& . -ince L6 and L: act as a current mirror circuit$ current Therefore$ I 9 =
9

e0uals the current through #6 .

V fffffff B R6
9

t shows that$ the output current

has low temperature coefficient$ if the temperature

coefficient of #6 is low$ such as that produced by a diffused resistor in C fabrication. The 4ero temperature coefficient for output current can be achieved$ if diodes are added in series with #6 $ so that they can compensate for the temperature variation of # 6 and %& . The temperature compensated avalanche diode reference source circuit is shown in figure. The transistor L* and L1 form an active load current mirror circuit. The base voltage of L + is the voltage %& across 4ener D& . Then$ %& M A%&/ J nB F%&/ across L+ F %&/ across L6 F drop across #6 .<ere$ n is the number of diodes. ` a t can be e7pressed as V B = n + 6 V BE + I 9 B R 6 Differentiating for %& $ 9 $ #6 and %&/ partially$ with respect to temperature T$ we get a∂ ∂ VB ` V BE ∂ I9 ∂ R6 fffffffffff fffffffffffff fffffffff ffffffffff Dividing throughout by 9 #6 $ we get VB n V BE + I9 + ∂ +6 ∂ fffffffffffff fffffffffff fffffffffffff fffffffffffff fffff∂ fffffffff

∂T

= n +6 =

∂T

+ R6

∂T +

+I9

∂T +

I 9 R6 ∂ T

I 9 R6 ∂ T

I 9 ∂T ∂T

RX ∂ T ∂T

R6 + ∂ ffffffff ffffffffff

Therefore$ 4ero temperature coefficient of 9 can be obtained$ if the following condition is satisfied$ a∂ I9 VB ` V BE G fffffff R6 + + F∂ + ∂ fffff∂ fffffffff fffffffffffff fffffffffff fffffffffffff ffffffffff =9= n +6 @ That is$

I 9 ∂T

R6 I 9

R6 ∂ T

D+00&(&$%+)1 );41+0+&(:

The function of a differential amplifier is to amplify the difference

between two signals. The need for differential amplifier arises in many physical measurements where response from dc to many "<4 of fre0uency is re0uired. This forms the basic input stage of an integrated amplifier. The basic differential amplifier has the following important properties of +. /7cellent stability 6. <igh versatility and :. <igh immunity to interference signals The differential amplifier as a building block of the op-amp has the advantages of +. Lower cost 6. easier fabrication as C component and :1

:. closely matched components.

%+

A;41+0+&( 8+%3 ')+$ A*;
%6

%9

The above figure shows the basic block diagram of a differential amplifier$ with two input terminals and one output terminal. The output signal of the differential amplifier is proportional to the difference between the two input signals. That is %9 M Adm A%+ ! %6 B f %+ M %6 $ then the output voltage is 4ero. A non-4ero output voltage % 9 is obtained when %+ and %6 are not e0ual. The difference mode input voltage is defined as %m M %+ ! %6 and the common mode input voltage is defined as

Vc =

These e0uation show that if % + M %6 $ then the differential mode input signal is 4ero and common mode input signal is %cm M %+ M%6 . D+00&(&$%+)1 A;41+0+&( 8+%3 A,%+.& 1/)*: Differential amplifier are designed with active loads to increase the differential mode voltage gain. The open circuit voltage gain of an op-amp is needed to be as large as possible. This is achieved by cascading the gain stages which increase the phase shift and the amplifier also becomes vulnerable to oscillations. The gain can be increased by using large values of collector resistance. .or such a circuit$ the voltage gain is given by A d To increase the gain the C fabrication such as$ +. a large value of resistance needs a large chip area.
C

V ffffffffffffffffff + +V 6 6

= @g RC =

Iffffffffffffff C RC VT

#C product must be made very large. <owever$ there are limitations in

:2

6. for large #C$ the 0uiescent drop across the resistor increase and a large power supply will be re0uired to maintain a given operating current. :. Large monolithic resistor introduces large parasitic capacitances which limits the fre0uency response of the amplifier. *. for linear operation of the differential pair$ the devices should not be allowed to enter into saturation. This limits the ma7 input voltage that can be applied to the bases of transistors L+ and L6 the base-collector ;unction must be allowed to become forward-biased by more than 9.1 %. The large value of load resistance produces a large dc voltage drop A so that the collector voltage will be %C M %cc -A
// //

5 6B#C$

5 6B#C and it will be substantially less

than the supply voltage %cc. This will reduce the input voltage range of the differential amplifier. Due to the reasons cited above$ an active load is preferred in the differential amplifier configurations. BJT D+00&(&$%+)1 A;41+0+&( -!+$' ),%+.& 1/)*!: A simple active load circuit for a differential amplifier is the current mirror active load as shown in figure. The active load comprises of transistors L : and L* with the transistor L: connected as a diode with its base and collector shorted. The circuit is shown to drive a load # L. >hen an ac input voltage is applied to the differential amplifier$ the various currents of the circuit are given by

I C* = I C: = I C+ = I C6 = @

g V id ffffffffffffffff . >here I C* = I C: due to current mirror action. <ere$ 6
L

C6

is given by

g V id ffffffffffffffff . >e know that the load current 6

entering the ne7t stage is I % = I C6 @I C*

.Therefore$ I % = @

g V id g V id ffffffffffffffff ffffffffffffffff @ = @g V id . Then$ the output voltage from the differential 6 6

b c amplifier is given by V 9 = @I % R % = @ @g V id R % = g R % V id . The ac voltage gain of

the circuit is given by A V =

V g R % V id ffffffff ffffffffffffffffffffffff 9 = = g R % .The differential amplifier can amplify V id V id

the differential input signals and it provides single-ended output with a ground reference since the load #L is connected to only one output terminal. This is made possible by the use of the current :)

mirror active load.The output resistance #9 of the circuit is that offered by the parallel combination of transistors L6 A=P=B and L* AP=PB. t is given by #r M r96 YY r9*

:8

A$)19!+! /0 BJT *+00&(&$%+)1 );41+0+&( 8+%3 ),%+.& 1/)*:

:?

Assu ing

V ffffffff id = 9 for transistor # + and # 6 and β = 1 , then the bias current I EE 6 is divided e"uall& between # + and # 6 and hence, I C+ = I C6 = I EE The current I C+ su''lied b& # : is A ffffffffff
6

irrored as I C* at the out'ut of transitor # * A therefore, I C: = I C* = I EE and the dc current in the collector of # * is e(actl& the current needed to satisf& # 6 A when β is ver& large and V EC* = V EC: = V BE , the current irror ratio beco es e(actl& unit& A Then , the differential a 'lifier is co 'letl& balanced , and the out'ut voltage isV 9 = V CC @V BE # @'ointsE The collector currents of all the transitors are e"ual A Iffffffff that is, I C+ = I C6 = I C: = I C* = EE A 6 The Collector @e itter voltages of # + and # 6 are given b&

V CE+ = V CE6 = V C @V E = V CC @V EB @ @V EB = V CC The collector e itter voltages of # : and # * are given b&, V CE: = V CE* = V EB The in'ut offset voltagesV OS of the differential a 'lifier arises fro the is atches in the in'ut devices # + , # 6 and load drives # : , # * and fro the base current of the %oad devices A an a''ro(ia ate e('ression forV OS is given b&
f

b

c b

c

V OS = V T

∆ I S) ∆ I 6 ffffffffffff fffffffffffff ffff @ S* + I S) I S* β

g

whereβ re'resents the gain of )*) transistor and it is assu ed that ∆ I S) = I S : @I S * Iffffffffffffffffffff +I I S) = S : S * 6 ∆ I S* = I S + @I S 6 and Iffffffffffffffffffff +I I S* = S + S 6 6 ∆ Is fffffffff assu ing a worst case value of F *Q for and β of 69, Is
*9

V OS = V T 9.9* + 9.9* + 9.+ = 62 B +9@: B 9.+8 = *.28 V A E"n shows that, the offset is higher than that of a resistive loaded differential a 'lifier A This can be reduced b& the use of e itter resistors for # : and # * , and a transitor # 1 in the current irror load as shown in figure A
CMRR /0 %3& *+00&(&$%+)1 );41+0+&( -!+$' ),%+.& 1/)*: The differential amplifier using active load provides high voltage gain to the differential input signal and a single ! ended output that is referenced to the ground is obtained. The differential amplifier which provides conversion for a differential signal to a single ended signal is necessary in differential input signal ended output amplifiers. The op-amp is one such circuit. The changes in the common-mode signal of the bias current source. This induces a change in identical change in thereby a change in cancel the change in output.
C+. C6

`

a

and an

The change in

C+

will then produce a change in the P=P load devices$ and
C*

C*$

which is the collector current L*$ The current

is in such a direction as to

C6.

As a result of this$ any common mode input does not cause a change in

*+

The voltage gain of the differential amplifier is independent of the 0uiescent current This makes it possible to use very small value of voltage gain. -mall value of
// //

//.

as low as 69Ka$ while still maintaining a large is$ however$ the fact that$ it

is preferred$ since it results in a small value of bias current and a
//

large value for the input resistance. A limitation in choosing a small will result in a poor fre0uency response of the amplifier.

>hen a small value of bias current is re0uired$ the best approach is to use a './T or ",-./T differential amplifier that is operated at comparatively higher values of
//.

*6

D+00&(&$%+)1 M/*& !+'$)1 )$)19!+!: The ac analysis of the differential amplifier can be made using the circuit model as shown below. The differential input transistor pair produces e0ual and opposite currents whose amplitude us given by gm6 %id 56 at the collector of L+ and L6 . The collector current ic+ is fed by the transistor L: and it is mirrored at the output of L *. Therefore$ the total current i9 flowing through the load resistor #L is given by
g ffffffffffffffffff 6 V id = g 6 V id 6 Then the out'ut voltage is i9 = 6 V 9 = i9 R % = g
b
6

R % V id

c

and the differential ode gain A dd of the differential a 'lifier is given b& v ffffffffff A dd = 9 = g 6 R % Vd This current mirror provides a single ended output which has a voltage e0ual to the

ma7imum gain of the common emitter amplifier. *:

The power of the current mirror can be increased by including additional common collector stages at the o5p of the differential input stage. A bipolar differential amplifier structure with additional stages is shown in figure. The resistance at the output of the differential stage is now given by the parallel combination of transistors L6 and L* and the input resistance is offered by L1. Then$ the e0uivalent resistance is e7pressed by #e0 M ro6 YY r9* YY ri1 M ri1 . The gain of the differential stage then becomes A d = g

6

R e" = g

6

r i1 = β 91

Ifffffff C6 . I C1

**

B+4/1)( *+00&(&$%+)1 );41+0+&( 8+%3 ,/;;/$ ;/*& +$4-% !+'$)1!: The common mode input signal induces a common mode current i ic in each of the differential transistor pair L+ and L6 . The common current iic is given by

iic =

+ + 6g

g 6 fffffffffffffffffffffffffffffff
6

R EE

V ic

V ic ffffffffffffff 6 R EE

The current flow through the transistor L+ is supplied by the reference current of transistor L:. This current is replicated or mirrored in the transistor L* and it produces e7actly the same current needed at the collector of L6. Therefore$ the output current and hence the output voltage and common mode conversion gain Acd are all 4ero. <owever$ for an actual amplifier$ the common mode gain is determined by small imbalances generated in the bipolar transistor fabrication and the overall asymmetry in the amplifier. ,ne of the main factors is due to the current gain defect on the active load$ and it can be minimi4ed through the use of buffered current mirror using the transistor L1 as shown in figure.

*1

G&$&()1 O4&()%+/$)1 A;41+0+&(: An operational amplifier generally consists of three stages$ anmely$+. a differential amplifier 6. additional amplifier stages to provide the re0uired voltage gain and dc level shifting :. an emitter-follower or source follower output stage to provide current gain and low output resistance. A low-fre0uency or dc gain of appro7imately +9* is desired for a general purpose op-amp and hence$ the use of active load is preferred in the internal circuitry of op-amp. The output voltage is re0uired to be at ground$ when the differential input voltages is 4ero$ and this necessitates the use of dual polarity supply voltage. -ince the output resistance of op-amp is re0uired to be low$ a complementary push-pull emitter ! follower or source follower output stage is employed. "oreover$ as the input bias currents are to be very small of the order of picoamperes$ an ./T input stage is normally preferred. The figure shows a general op-amp circuit using './T input devices.

*2

I$4-% !%)'&: The input differential amplifier stage uses p-channel './Ts "+ and "6. t employs a three-transistor active load formed by L: $ L* $ and L1 . the bias current for the stage is provided by a two-transistor current source using P=P transistors L2 and L). #esistor #+ increases the output resistance seen looking into the collector of L* as indicated by #9*. This is necessary to provide bias current stability against the transistor parameter variations. #esistor #6 establishes a definite bias current through L1 . A single ended output is taken out at the collector of L* . ",-./THs are used in place of './Ts with additional devices in the circuit to prevent any damage for the gate o7ide due to electrostatic discharges. G)+$ !%)'&: The second stage or the gain stage uses Darlington transistor pair formed by L 8 and L? as shown in figure. The transistor L8 is connected as an emitter follower$ providing large input resistance. *)

Therefore$ it minimi4es the loading effect on the input differential amplifier stage. The transistor L? provides an additional gain and L+9 acts as an active load for this stage. The current mirror formed by L) and L+9 establishes the bias current for L? . The %&/ drop across L? and drop across #1 constitute the voltage drop across #* $ and this voltage sets the current through L8 . t can be set to a small value$ such that the base current of L8 also is very less. O-%4-% !%)'&: The final stage of the op-amp is a class A& complementary push-pull output stage. L++ is an emitter follower$ providing a large input resistance for minimi4ing the loading effects on the gain stage. &ias current for L++ is provided by the current mirror formed by L) and L+6$ through L+: and L+* for minimi4ing the cross over distortion. Transistors can also be used in place of the two diodes. The overall voltage gain A% of the op-amp is the product of voltage gain of each stage as given by A% M YAd Y YA6YYA:Y >here Ad is the gain of the differential amplifier stage$ A 6 is the gain of the second gain stage and A: is the gain of the output stage. IC <45 B+4/1)( /4&()%+/$)1 );41+0+&(: The C )*+ produced since +?22 by several manufactures is a widely used general purpose operational amplifier. .igure shows that e0uivalent circuit of the )*+ op-amp$ divided into various individual stages. The op-amp circuit consists of three stages. +. the input differential amplifier 6. The gain stage :. the output stage. A bias circuit is used to establish the bias current for whole of the circuit in the C. The op-amp is supplied with positive and negative supply voltages of value Z +1%$ and the supply voltages as low as Z1% can also be used. B+)! C+(,-+%: The reference bias current
#/.

for the )*+ circuit is established by the bias circuit consisting of two

diodes-connected transistors L++ and L+6 and resistor #1. The widlar current source formed by L++ $ L+9 and #* provide bias current for the differential amplifier stage at the collector of L +9. Transistors L8 and L? form another current mirror providing bias current for the differential amplifier. The *8

reference bias current

#/.

also provides mirrored and proportional current at the collector of the

double !collector lateral P=P transistor L+:. The transistor L+: and L+6 thus form a two-output current mirror with L+:A providing bias current for output stage and L+:& providing bias current for L+). The transistor L+8 and L+? provide dc bias for the output stage. .ormed by L+* and L69 and they establish two %&/ drops of potential difference between the bases of L+* and L+8 .

I$4-% !%)'&: The input differential amplifier stage consists of transistors L + through L) with biasing provided by L8 through L+6. The transistor L+ and L6 form emitter ! followers contributing to high differential input resistance$ and whose output currents are inputs to the common base amplifier using L: and L* which offers a large voltage gain. The transistors L1$ L2 and L) along with resistors # +$ #6 and #: from the active load for input stage. The single-ended output is available at the collector of L 2. the two null terminals in the input stage facilitate the null ad;ustment. The lateral P=P transistors L : and L* provide additional protection against voltage breakdown conditions. The emitter-base ;unction L: and L* have higher emitter-base breakdown voltages of about 19%. Therefore$ placing P=P transistors in series with =P= transistors provide protection against accidental shorting of supply to the input terminals. G)+$ S%)'&: The -econd or the gain stage consists of transistors L +2 and L+)$ with L+2 acting as an emitter ! follower for achieving high input resistance. The transistor L +) operates in common emitter configuration with its collector voltage applied as input to the output stage. Level shifting is done for this signal at this stage. nternal compensation through "iller compensation techni0ue is achieved using the feedback capacitor C+ connected between the output and input terminals of the gain stage. O-%4-% !%)'&: The output stage is a class A& circuit consisting of complementary emitter follower transistor pair L+* and L69 . <ence$ they provide an effective loss output resistance and current gain. The output of the gain stage is connected at the base of L 66 $ which is connected as an emitter ! follower providing a very high input resistance$ and it offers no appreciable loading effect on the

*?

gain stage. t is biased by transistor L+:A which also drives L+8 and L+?$ that are used for establishing a 0uiescent bias current in the output transistors L+* and L69. I*&)1 /4-);4 ,3)(),%&(+!%+,!: +. 6. nfinite voltage gain A. nfinite input resistance #i$ so that almost any signal source can drive it and there is no loading of the proceeding stage. :. Vero output resistance #o$ so that the output can drive an infinite number of other devices. *. Vero output voltage$ when input voltage is 4ero. 1. 2. ). nfinite bandwidth$ so that any fre0uency signals from o to [ <V can be amplified with out attenuation. nfinite common mode re;ection ratio$ so that the output common mode noise voltage is 4ero. nfinite slew rate$ so that output voltage changes occur simultaneously with input voltage changes. AC C3)(),%&(+!%+,!: .or small signal sinusoidal AACB application one has to know the ac characteristics such as fre0uency response and slew-rate. F(&F-&$,9 R&!4/$!&: The variation in operating fre0uency will cause variations in gain magnitude and its phase angle. The manner in which the gain of the op-amp responds to different fre0uencies is called the fre0uency response. ,p-amp should have an infinite bandwidth &w M[ Ai.eB if its open loop gain in ?9d& with dc signal its gain should remain the same ?9 d& through audio and onto high radio fre0uency. The op-amp gain decreases Aroll-offB at higher fre0uency what reasons to decrease gain after a certain fre0uency reached. There must be a capacitive component in the e0uivalent circuit of the op-amp. .or an op-amp with only one break AcornerB fre0uency all the capacitors effects can be represented by a single capacitor C. &elow fig is a modified variation of the low fre0uency model with capacitor C at the o5p.

19

There is one pole due to #9 C and one -69d&5decade. The open loop voltage gain of an op-amp with only one corner fre0uency is obtained from above fig.

V9=

@ +, C ffffffffffffffffffffffff

R 9 @ +, C V AO% fffffff fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff c or A = 9 = b Vd + + 6+π + R C
9

AO% Vd

@@@@ 62

`

a

or A =

AO% fffffffffffffffffffffffffffffff f g f f f f f f f f f +++ f+

@@@@@ 6) @@@ 68
` a

`

a

6π R 9 C f+ is the corner fre0uency or the upper : d& fre0uency of the op-amp. The magnitude and phase

where f + =

+ fffffffffffffffffffffff

angle of the open loop volt gain are fu of fre0uency can be written as$
L M ffffffffffffffffffffffffffffff ` a AO% L AM = v w w w w w w w w w w w w w w w w w w w w w w w w w w w w w w w w w w w w @@@@@@@ 6? u f g6 u u ffffff ff t ++ f+

f k ffffff φ = @tan@+j f+
The magnitude and phase angle characteristics from e0n A6?B and A:9B +. .or fre0uency fUU f+ the magnitude of the gain is 69 log A,L in d&. 6. At fre0uency f M f+ the gain in : d& down from the dc value of A ,L in d&. This fre0uency f+ is called corner fre0uency. :. .or fPP f+ the fain roll-off at the rate off -69d&5decade or -2d&5decade.

h

i

1+

.rom the phase characteristics that the phase angle is 4ero at fre0uency f M9. At the corner fre0uency f+ the phase angle is -*19 Alagging and a infinite fre0uency the phase angle is -?99 . t shows that a ma7imum of ?99 phase change can occur in an op-amp with a single capacitor C. Vero fre0uency is taken as te decade below the corner fre0uency and infinite fre0uency is one decade above the corner fre0uency. The voltage transfer in a --domain can be written as

A=

AO% AO% fffffffffffffffffffffffff fffffffffffffffffffffff d e f g = w fffffff f + + + fffffff + + + w+ f+ A A A fffffffffffffffffffff ffffffffffffffffffff O% @w+ = O% + +w + w+ S + - +

A=

The transfer f9 of as op-amp with : break fre0uency can be assumed as$

16

A =f

AO% fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff gf gf g 9U f + U f 6 U f f f f fffffff ffffffff ffffffff + ++ +++ +++ f+ f6 f: s + w+ s + w6 s + w:

:

@@@@ :+

` a

A=`

` a AO% w+ w6 w: fffffffffffffffffffffffffffffffffffffffffffffffffffffffff a` a` a @@@ :6 with 9Uw+ Uw6 Uw:

C+(,-+% S%)?+1+%9: A circuit or a group of circuit connected together as a system is said to be stable$ if its o5p reaches a fi7ed value in a finite time. AorB A system is said to be unstable$ if its o5p increases with time instead of achieving a fi7ed value. n fact the o5p of an unstable sys keeps on increasing until the system break down. The unstable system are impractical and need be made stable. The criterian gn for stability is used when the system is to be tested practically. n theoretically$ always used to test system for stability $ e7E &ode plots. &ode plots are compared of magnitude %s .re0uency and phase angle %s fre0uency. Any system whose stability is to be determined can represented by the block diagram.

1:

The block between the output and input is referred to as forward block and the block between the output signal and f5b signal is referred to as feedback block. The content of each block is referred \Transfer fre0uencyH .rom fig we represented it by A,L AfB which is given by A,L AfB M %9 5%in if %f M 9. -----A+B where A,L AfB M open loop volt gain. The closed loop gain Af is given by A. M %9 5%in A. M A,L 5 A+FAA,L B A&B ----A6B & M gain of feedback circuit. & is a constant if the feedback circuit uses only resistive components. ,nce the magnitude %s fre0uency and phase angle %s fre0uency plots are drawn$ system stability may be determined as follows 56 M&%3/*:5: Determine the phase angle when the magnitude of AA,L B A&B is 9d& AorB +. f phase angle is P .+899 $ the system is stable. <owever$ the some systems the magnitude may never be 9$ in that cases method 6$ must be used. 26 M&%3/* 2: Determine the phase angle when the magnitude of AA,L B A&B is 9d& AorB +. f phase angle is P .+899 $ f the magnitude is !ve decibels then the system is stable. <owever$ the some systems the phase angle of a system may reach -+89 9 $ under such conditions method + must be used to determine the system stability. S1&8 R)%&: Another important fre0uency related parameter of an op-amp is the slew rate. A-lew rate is the ma7imum rate of change of output voltage with respect to time. -pecified in %5KsB. R&)!/$ 0/( S1&8 ()%&: There is usually a capacitor within 9$ outside an op-amp oscillation. t is this capacitor which prevents the o5p voltage from fast changing input. The rate at which the volt across the capacitor increases is given by d%c5dt M 5C --------A+B -P "a7imum amount furnished by the op-amp to capacitor C. ,p-amp should have the either a higher current or small compensating capacitors. 1*

.or )*+ C$ the ma7imum internal capacitor charging current is limited to about +1KA. -o the slew rate of )*+ C is -# M d%c5dt Yma7 M ma75C . .or a sine wave input$ the effect of slew rate can be calculated as consider volt follower -P The input is large amp$ high fre0uency sine wave . f %s M %m -inwt then output %9 M %m sinwt . The rate of change of output is given by d%95dt M %m w coswt.

The ma7 rate of change of output across when coswt M+ Ai.eB -# M d%95dt Yma7 M w%m. -# M 6]f%m %5s M 6]f%m v5ms. Thus the ma7imum fre0uency fma7 at which we can obtain an undistorted output volt of peak value %m is given by fma7 A<4B M -lew rate52.68 J %m . 11

called the full power response. t is ma7imum fre0uency of a large amplitude sine wave with which op-amp can have without distortion. DC C3)(),%&(+!%+,! /0 /4-);4: Current is taken from the source into the op-amp inputs respond differently to current and voltage due to mismatch in transistor. DC output voltages are$ +. 6. :. nput bias current nput offset current nput offset voltage

*. Thermal drift I$4-% ?+)! ,-((&$%: The op-ampHs input is differential amplifier$ which may be made of &'T or ./T.  n an ideal op-amp$ we assumed that no current is drawn from the input terminals.
&

 The base currents entering into the inverting and non-inverting terminals A respectivelyB.  /ven though both the transistors are identical$ internal imbalance between the two inputs.  "anufacturers specify the input bias current
& & -

@

F &

and

F &

are not e7actly e0ual due to

-o$

I

B

Iffff + I f f ff f f ff ff ff f f ff f f ` a B Bf = Q + 6

+

@

f input voltage %i M 9%. The output %oltage %o should also be A%o M 9B & M 199nA >e find that the output voltage is offset by$ 12

Vo= I

b

@ B

c

Rf Q 6

` a

,p-amp with a +" feedback resistor %o M 1999nA ^ +" M 199m% The output is driven to 199m% with 4ero input$ because of the bias currents. n application where the signal levels are measured in m%$ this is totally unacceptable. This can be compensated. >here a compensation resistor #comp has been added between the non-inverting input terminal and ground as shown in the figure below.

Current

F &

flowing through the compensating resistor #comp$ then by 3%L we get$ -%+F9F%6-%o M 9 AorB %o M %6 ! %+ __PA:B

&y selecting proper value of #comp$ %6 can be cancelled with %+ and the %o M 9. The value of #comp is derived a %+ M
& F & F

#comp AorB

M %+5#comp __PA*B

The node GaH is at voltage A-%+B. &ecause the voltage at the non-inverting input terminal is A-%+B. -o with %i M 9 we get$
+ 6

M %+5#+ __PA1B M %65#f __PA2B M %+5#f __PA)B
-

.or compensation$ %o should e0ual to 4ero A%o M 9$ %i M 9B. i.e. from e0uation A:B %6 M %+. -o that$
6

3CL at node GaH gives$
&

M

6

F

+

1)

IB=
I
Assume
&

@

V V ffffffff ffffffff + + + R f R+
b

@ B

=V+
b

R + R + ff f f f f f f f f f f f f f f f f f f f f f f f f f f f f f ` a Q 8 R+ R f
c

c

M

F &

and using e0uation A*B @ A8B we get

V+

R+ + R f V+ ffffffffffffffffffffffffffffff ffffffffffffff = R+ R f R co '
'

R co

=

R+ + R f

R R + f f f f f f f f f f f f f f f f f f f f f f f f

#comp M #+ YY #f ___PA?B i.e. to compensate for bias current$ the compensating resistor$ # comp should be e0ual to the parallel combination of resistor #+ and #f. I$4-% /00!&% ,-((&$%:  &ias current compensation will work if both bias currents difference between
F F &

and

&

are e0ual.

 -ince the input transistor cannot be made identical. There will always be some small
&

and

&

-

. This difference is called the offset current

Y osY M &F- &- __PA+9B ,ffset current os for &'T op-amp is 699nA and for ./T op-amp is +9pA. /ven with bias current compensation$ offset current will produce an output voltage when %i M 9. %+ M &F #comp __PA++B And __PA+6B + M %+5#+ 3CL at node GaH gives$ _ 6 M A & +B
h

I 6 =I
Again %9 M %o M
6 6

@ B

j I @

+ B

R ` a co ' f f f f f f f f f f f f f f k Q +: R+

i

#f ! % + #f - &F #comp

H

V o =J I B @I B

@

+

I R co ' ffffffffffffff K

R+

R f @I B R co ' Q +*

+

`

a

-ubstitute e0uation A?B and after algebraic manipulation $ 18

R co ' ffffffffffffff K@I + V o = R f J I @I B R co R+
@ B + B

H

I

'

V o = R fI B @I B
@

@

+

R + co ' ffffffffffffff R f @I B R co R+
H
+ B

'

V o = R f I B @I
@ +

R co

V o = R f I B @I B R co
V o = R f I B @I
@ +
@ + B

I R + R+ f fffffffffffffffffffffff J K '

H

R f f f f f f f f f J + +K ' R+

I

R+

R R + f f f f f f f f f f f f f f f f f f R+
C ` a

V o = R f I B @I B R f
V o =R f I
B
@ B

@I

+ B

V o = R f I os Q +2
output offset voltage

Q +1 ` a

-o even with bias current compensation and with feedback resistor of +"$ a &'T op-amp has an %o M +" ` ^ 699nA %o M 699m% with %i M 9 /0uation A+2B the offset current can be minimi4ed by keeping feedback resistance small.  Dnfortunately to obtain high input impedance$ #+ must be kept large.  #+ large$ the feedback resistor #f must also be high. -o as to obtain reasonable gain. The T-feedback network is a good solution. This will allow large feedback resistance$ while keeping the resistance to ground low Ain dotted lineB.  The T-network provides a feedback signal as if the network were a single feedback resistor. &y T to a conversion$
6

R + 6 R R ff ff f ff ff ff ff f f ff ff ff ff f ff ff f f ff f ` a tf s tf Rf = Q +) Rs
To design T- network first pick #tUU#f56 __PA+8B Then calculate R s =

R tffffffffff ffffffffff R f 6R t

6

Q +?

`

a

1?

I$4-% /00!&% ./1%)'&: nspite of the use of the above compensating techni0ues$ it is found that the output voltage may still not be 4ero with 4ero input voltage S%o b 9 with %i M 9T. This is due to unavoidable imbalances inside the op-amp and one may have to apply a small voltage at the input terminal to make output A%oB M 9. This voltage is called input offset voltage %os. This is the voltage re0uired to be applied at the input for making output voltage to 4ero A%o M 9B.

29

Let us determine the %os on the output of inverting and non-inverting amplifier. f % i M 9 A.ig AbB and AcBB become the same as in figure AdB. The voltage %6 at the negative input terminal is given by
h i R f f f f f f f f f f f f f f f f f f f f f f f + k

V 6 =j
h

R+ + R f
i

V o Q 69
h i

`

a

AorB

R Rf ` a ++ Rf fffffffffffffffffffffff k V =j + + ffffffff k V Q 6+ V o =j 6 6 R+ R+
-ince$
L M M L V i @V 6M@ V i = 9 V os =L

V os

R ` a f ff ff f f ff k V os Q 6: V o =j + + R+
Thus$ the output offset voltage of an op-amp in closed loop is given by e0uation A6:B. T/%)1 /-%4-% /00!&% ./1%)'&: The total output offset voltage %,T could be either more or less than the offset voltage produced at the output due to input bias current A &B or input offset voltage aloneA%osB. This is because
&

L L9 =L h

@V
i

M M 6M= V

6

Q 66

`

a`

or

a

and %os could be either positive or negative with respect to ground.

Therefore the ma7imum offset voltage at the output of an inverting and non-inverting amplifier Afigure b$ cB without any compensation techni0ue used is given by many op-amp provide offset compensation pins to nullify the offset voltage.  +93 potentiometer is placed across offset null pins +@1. The wipes connected to the negative supply at pin *.  The position of the wipes is ad;usted to nullify the offset voltage.

2+

>hen the given AbelowB op-amps does not have these offset null pins$ e7ternal balancing techni0ues are used.
H I

V OT

R ` a f ffff ffff KV os + R I Q 6* =J + + B f R+
` a

>ith #comp$ the total output offset voltage H I R f ffffffff J K

V OT = + +

R+

V os + R f I os Q 61

B)1)$,+$' ,+(,-+%: I$.&(%+$' );41+0+&(:

N/$-+$.&(%+$' );41+0+&(: 26

T3&(;)1 *(+0%:  &ias current$ offset current$ and offset voltage change with temperature.  A circuit carefully nulled at 61cC may not remain. -o when the temperature rises to :1cC. This is called drift.  ,ffset current drift is e7pressed in nA5cC.  These indicate the change in offset for each degree Celsius change in temperature. O4&$ D 1//4 /4-);4 C/$0+'-()%+/$: The term open-loop indicates that no feedback in any form is fed to the input from the output. >hen connected in open ! loop$ the op-amp functions as a very high gain amplifier. There are three open ! loop configurations of op-amp namely$ +. differential amplifier 6. nverting amplifier :. =on-inverting amplifier The above classification is made based on the number of inputs used and the terminal to which the input is applied. The op-amp amplifies both ac and dc input signals. Thus$ the input signals can be either ac or dc voltage. O4&$ D 1//4 D+00&(&$%+)1 A;41+0+&(: n this configuration$ the inputs are applied to both the inverting and the non-inverting input terminals of the op-amp and it amplifies the difference between the two input voltages. .igure shows the open-loop differential amplifier configuration. The input voltages are represented by %i+ and %i6. The source resistance #i+ and #i6 are negligibly small in comparison with the very high input resistance offered by the op-amp$ and thus 2:

the voltage drop across these source resistances is assumed to be 4ero. The output voltage % 9 is given by %9 M AA%i+ ! %i6 B where A is the large signal voltage gain. Thus the output voltage is e0ual to the voltage gain A times the difference between the two input voltages. This is the reason why this configuration is called a differential amplifier. n open ! loop configurations$ the large signal voltage gain A is also called open-loop gain A.

I$.&(%+$' );41+0+&(:

2*

n this configuration the input signal is applied to the inverting input terminal of the opamp and the non-inverting input terminal is connected to the ground. .igure shows the circuit of an open ! loop inverting amplifier. The output voltage is +899 out of phase with respect to the input and hence$ the output voltage % 9 is given by$ %9 M -A%i Thus$ in an inverting amplifier$ the input signal is amplified by the open-loop gain A and in phase ! shifted by +899. N/$-+$.&(%+$' A;41+0+&(:

21

.igure shows the open ! loop non- inverting amplifier. The input signal is applied to the non-inverting input terminal of the op-amp and the inverting input terminal is connected to the ground. The input signal is amplified by the open ! loop gain A and the output is in-phase with input signal. %9 M A%i n all the above open-loop configurations$ only very small values of input voltages can be applied. /ven for voltages levels slightly greater than 4ero$ the output is driven into saturation$ which is observed from the ideal transfer characteristics of op-amp shown in figure. Thus$ when operated in the open-loop configuration$ the output of the op-amp is either in negative or positive saturation$ or switches between positive and negative saturation levels. This prevents the use of open ! loop configuration of op-amps in linear applications.

L+;+%)%+/$! /0 O4&$ D 1//4 O4 D );4 ,/$0+'-()%+/$: .irstly$ in the open ! loop configurations$ clipping of the output waveform can occur when the output voltage e7ceeds the saturation level of op-amp. This is due to the very high open ! loop gain of the op-amp. This feature actually makes it possible to amplify very low fre0uency signal of the order of microvolt or even less$ and the amplification can be achieved accurately without any

22

distortion. <owever$ signals of such magnitudes are susceptible to noise and the amplification for those application is almost impossible to obtain in the laboratory. -econdly$ the open ! loop gain of the op ! amp is not a constant and it varies with changing temperature and variations in power supply. Also$ the bandwidth of most of the open- loop op amps is negligibly small. This makes the open ! loop configuration of op-amp unsuitable for ac applications. The open ! loop bandwidth of the widely used )*+ C is appro7imately 1<4. &ut in almost all ac applications$ the bandwidth re0uirement is much larger than this. .or the reason stated$ the open ! loop op-amp is generally not used in linear applications. <owever$ the open ! loop op amp configurations find use in certain non ! linear applications such as comparators$ s0uare wave generators and astable multivibrators. C1/!&* D 1//4 /4-);4 ,/$0+'-()%+/$: The op-amp can be effectively utili4ed in linear applications by providing a feedback from the output to the input$ either directly or through another network. f the signal feedback is out- ofphase by +899 with respect to the input$ then the feedback is referred to as negative feedback or degenerative feedback. Conversely$ if the feedback signal is in phase with that at the input$ then the feedback is referred to as positive feedback or regenerative feedback. An op ! amp that uses feedback is called a closed ! loop amplifier. The most commonly used closed ! loop amplifier configurations are +. nverting amplifier A%oltage shunt amplifierB 6. =onnverting amplifier A%oltage ! series AmplifierB I$.&(%+$' A;41+0+&(: The inverting amplifier is shown in figure and its alternate circuit arrangement is shown in figure$ with the circuit redrawn in a different way to illustrate how the voltage shunt feedback is achieved. The input signal drives the inverting input of the op ! amp through resistor #+ . The op ! amp has an open ! loop gain of A$ so that the output signal is much larger than the error voltage. &ecause of the phase inversion$ the output signal is +89 9 out ! of ! phase with the input signal. This means that the feedback signal opposes the input signal and the feedback is negative or degenerative. V+(%-)1 G(/-$*: 2)

A virtual ground is a ground which acts like a ground . t may not have physical connection to ground. This property of an ideal op ! amp indicates that the inverting and non ! inverting terminals of the op !amp are at the same potential. The non ! inverting input is grounded for the inverting amplifier circuit. This means that the inverting input of the op !amp is also at ground potential. Therefore$ a virtual ground is a point that is at the fi7ed ground potential A9%B$ though it is not practically connected to the actual ground or common terminal of the circuit. The open ! loop gain of an op ! amp is e7tremely high$ typically 699$999 for a )*+. .or e7$ when the output voltage is +9%$ the input differential voltage %id is given by

V id =

V +9 fffffff ffffffffffffffffffff 9 = = 9.91 V A 699$999

.urther more$ the open ! loop input impedance of a )*+ is around 6"I. Therefore$ for an input differential voltage of 9.91m%$ the input current is only

Ii =

V 9.91 V ffffffff fffffffffffffffffffff id = = 9.61nA A Ri 6.Ω

-ince the input current is so small compared to all other signal currents$ it can be appro7imated as 4ero. .or any input voltage applied at the inverting input$ the input differential voltage % id is negligibly small and the input current is ideally 4ero. <ence$ the inverting input acts as a virtual ground. The term virtual ground signifies a point whose voltage with respect to ground is 4ero$ and yet no current can flow into it.

The e7pression for the closed ! loop voltage gain of an inverting amplifier can be obtained from figure. -ince the inverting input is at virtual ground$ the input impedance is the resistance between the inverting input terminal and the ground. That is$ Vi M #+. Therefore$ all of the input voltage appears across #+ and it sets up a current through #+ that 28

e0uals I + =

V ffffff i . The current must flow through #f because the virtual ground accepts negligible R+

current. The left end of #f is ideally grounded$ and hence the output voltage appears wholly across it. Therefore$ V 9 = @I 6 R f = @

R f fffffff V . The closed !loop voltage gain A% is given by R+ i

Av =

R V f fffffff fffffff 9 =@ . Vi R+

The input impedance can be set by selecting the input resistor # + . "oreover$ the above e0uation shows that the gain of the inverting amplifier is set by selecting a ratio of feedback resistor # f to the input resistor #+ . The ratio #f 5#+ can be set to any value less than or greater than unity. This feature of the gain e0uation makes the inverting amplifier with feedback very popular and it lends this configuration to a ma;ority of applications. P(),%+,)1 C/$!+*&()%+/$!: +. -etting the input impedance #+ to be too high will pose problems for the bias current$ and it is usually restricted to +93I. 6. The gain cannot be set very high due to the upper limit set by the fain ! bandwidth A(&> M Av J fB product. The Av is normally below +99. :. The peak output of the op ! amp is limited by the power supply voltages$ and it is about 6% less than supply$ beyond which$ the op ! amp enters into saturation. *. The output current may not be short ! circuit limited$ and heavy loads may damage the op ! amp. >hen short ! circuit protection is provided$ a heavy load may drastically distort the output voltage. P(),%+,)1 I$.&(%+$' );41+0+&(: The practical inverting amplifier has finite value of input resistance and input current$ its open voltage gain A9 is less than infinity and its output resistance #9 is not 4ero$ as against the ideal inverting amplifier with finite input resistance$ infinite open ! loop voltage gain and 4ero output resistance respectively. .igure shows the low fre0uency e0uivalent circuit model of a practical inverting amplifier. This circuit can be simplified using the TheveninHs e0uivalent circuit shown in figure. The signal source 2?

%i and the resistors #+ and #i are replaced by their TheveninHs e0uivalent values. The closed ! loop gain A% and the input impedance #if are calculated as follows. The input impedance of the op- amp is normally much larger than the input resistance # +. Therefore$ we can assume %e0 O %i and #e0 O #+ . .rom the figure we get$

V 9 = IR 9 + AV id and V id + IR f + V 9 = 9 Substituting the value ofV id fro above e"n , we get, V 9 + + A = I R 9 @ AR f V i = I R+ + R f + V 9 Substituting the value of I derived fro above e"n and obtaining the closed loo' gain A v , we get R 9 @ AR f V fffffff ffffffffffffffffffffffffffffffffffffffffffffffff ` a Av = 9 = V i R 9 + R f + R+ + + A
t can be observed from above e0n that when APP +$ # 9 is negligibly small and the product A#+ PP #9 F#f $ the closed loop gain is given by
b c ` a b c

Also using the /V% , we get

Av = @

R f fffffff R+

>hich is as the same form as given in above e0n for an ideal inverter.

I$4-% R&!+!%)$,&: )9

.rom figure we get$ V ffffffff id

I+ !sing /V%, we get, V id + I + R f + R 9 + AV id = 9 which can be si 'lified for R if as V R if f + R9 ffffffff fffffffffffffffffff R if = = I+ ++A
b c

R if =

O-%4-% R&!+!%)$,&:

)+

.igure shows the e0uivalent circuit to determine #of . The output impedance #of without the load resistance factor #L is calculated from the open circuit output voltage % oc and the short circuit output current
-C

. .rom the figure$ when the output is short circuited$ we get

V fffffffffffffffffff i @9 R+ + R f AV fffffffffffff id and I 9 = R9 we 0now that V id = @I + R f AI + Rf fffffffffffffffff Therefore, I 9 = @ R9 The short circuit current is R 9 @ AR f fffffffffffffffffffffffffffffff c I SC = I + + I 9 = V i b R 9 R+ + R f I+ = The out'ut resistance R of = V V ffffffff oc ffffffff oc and the closed o'en loo' gain A v = I sc Vi

Therefore, Rof = A V v f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f if H I R @ AR 9 f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f b cK V i J fffffff R9 R+ + R f
b c

Substituting the value of Av fro R R + R 9 + ff f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f ` a Rof = f R9 + R f + R+ + + A
R + R + R 9 + ff f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f = f F G R+ A f f f f f f f f f f f f f f f f f f f f f f f f f + + fffffffffffffffffff R9 + R+ + R f R R + R 9 + ff f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f
b c

above e"n, we get

n the above e0uation$ the numerator contains the term # 9 YY A#+ F#f B and it is smaller than #9 . The output resistance #of is therefore always smaller than #9 and from above e0n for Av -P [$ the output resistance #of -P 9. )6

N/$ DI$.&(%+$' A;41+0+&(: The non ! inverting Amplifier with negative feedback is shown in figure. The input signal drives the non ! inverting input of op-amp. The op-amp provides an internal gain A. The e7ternal resistors #+ and #f form the feedback voltage divider circuit with an attenuation factor of d. -ince the feedback voltage is at the inverting input$ it opposes the input voltage at the non ! inverting input terminals$ and hence the feedback is negative or degenerative. The differential voltage %id at the input of the op-amp is 4ero$ because node a is at the same voltage as that of the non- inverting input terminal. As shown in figure$ #f and #+ form a potential divider. Therefore$

Vi=

R+ + R f

R+ fffffffffffffffffff

BV 9 R R V ++ Rf f fffffff fffffffffffffffffff fffffff 9 = =+ + Vi Rf R+

-ince no current flows into the op-amp. /0n can be written as

<ence$ the voltage gain for the non ! inverting amplifier is given by R V f fffffff fffffff 9

AV =

Vi

=+ +

R+ R+ + R f

Dsing the alternate circuit arrangement shown in figure$ the feedback factor of the feedback R+ fffffffffffffffffff voltage divider network is β =

+ ++ Rf ffff R fffffffffffffffffff = β R+ Therefore$ the closed loop ! gain is R f fffffff =+ + R+ Av =
.rom the above e0n$ it can be observed that the closed ! loop gain is always greater than one and it depends on the ratio of the feedback resistors. f precision resistors are used in the feedback network$ a precise value of closed ! loop gain can be achieved. The closed ! loop gain does not drift with temperature changes or op ! amp replacements.

):

Closed Loop =on ! nverting Amplifier The input resistance of the op ! amp is e7tremely large Aappro7imately infinity$B since the op ! amp draws negligible current from the input signal.

P(),%+,)1 N/$ D+$.&(%+$' );41+0+&(: The e0uivalent circuit of a non- inverting amplifier using the low fre0uency model is shown below in figure. Dsing 3irchoffHs current law at node a$

)*

b

V i @V id 1 + + V id 1 i + V i @V id @V 9 1 f = 9
b c
f

c

b

c

That is, @ 1 + @1 i + 1
b

V id + 1 + + 1
b

b

c
f

V i =1 f V 9

Si ilarl& /C% at the out'ut node gives, V i @V id @V 9 1 f + AV is @V 9 1 9 = 9
b c c c

That gives @ 1 f @ A1 9 V id + 1 f V i = 1 f + 1 9 V 9 !sing this e"n for V fffffff 9 we get Vi
b c

b

c

A1 9 1 + + 1 f @1 f 1 i V fffffff ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff 9 b cb c Av = = V i ` A + +a1 1 + 1 @1 i 1 + 1 9 f + f 9 when the o'en @loo' gain A a''roaches infinit&, the e"n beco es Av = A1 1 9 1+ +1 f 1 + +1 f ffffffffffffffffffffffffffffffffffff fffffffffffffffffff fffffff = =++ + A1 9 1 f 1f 1f
b c

F&&*?),= );41+0+&(:

)1

An op-amp that was feedback is called as feedback amplifier. A feedback amplifier is sometimes referred to as closed loop amplifier because the feedback forms a closed loop between the input and output. A closed loop amplifier can be represented by using 6 blocks. +. ,ne for an op-amp 6. another for an feedback circuit. There are * ways to connect these 6 blocks according to whether volt or current. +. %oltage -eries .eedback 6. %oltage -hunt feedback :. Current -eries .eedback *. Current shunt .eedback %oltage series and voltage shunt are important because they are most commonly used.

V/1%)'& S&(+&! F&&*?),= A;41+0+&(

V/1%)'& !3-$% 0&&*?),= A;41+0+&(

)2

V/1%)'& S&(+&! F&&*?),= A;41+0+&(:

&efore Proceeding$ it is necessary to define some terms. %oltage gain of the op-amp with a without feedbackE (ain of the feedback circuit are defined as open loop volt gain Aor gain without feedbackB A M % 9 5 %id Closed loop volt gain Aor gain with feedbackB A. M %9 5%in (ain of the feedback circuit MP & M %. 5%9 . 56 N&')%+.& 0&&*?),=: 3%L e0uation for the input loop is$ %id M %in -%f %in M input voltage. %f M feedback voltage. %id M difference input voltage. The difference volt is e0ual to the input volt minus the f5b volt. AorB The feedback volt always opposes the input volt Aor out of phase by +89 9 with respect to the input voltageB hence the feedback is said to be negative. t will be performed by computing +. Closed loop volt gain 6. nput and output resistance ))
-----A+B

:. &andwidth

56 C1/!&* 1//4 ./1% ')+$: The closed loop volt gain is A. M %9 5%in %9 M Avid MAA%+ !%6 B

A M large signal voltage gain. .rom the above e0n$ %9 M AA%+ ! %6 B #efer fig$ we see that$ %+ M %in %6 M %f M #+ %9 -----#+ F#f -ince #i PP #+ %9 M A%in #+ % 9 -----#+ F#f %9 F A #+ %9 -----)8
M

A%in

#+ F#f #earranging$ we get$ R + R V + F Afffffffffffffffff ffA f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f 9 = ffffffffffffffff = f f f f f f f f f f f f f f f f f f f f f f R+ + RF + AR+ V in + + ffffffAR + A R+ + RF V in V 9 = fffffffffffffffffffffffffffffffffffffffffffffffff R+ + RF + A R+ Thus b c A R + R + F V fffff fffffffffffffffff ` a f f f f f f f f f f f f f f f f f f f f f f f f f f f AF = fffff9 = @@@ 6 V in R+ + RF + AR+ 2enerall&, A is large t&'icall& +9 , AR+ PP R+ + RF and R+ + RF + AR+ ≈ AR+ V fffff RF a ` a f f f f f` Thus AF = fffff9 = + + ffff Ideal @@@@ : V in R+ ` a The gain of the feedbac0 circuit B is the ratio ofV F andV 9 , VF ` a f f f f f B = ffff @@@ * V9 R+ f f f f f f f f f f f f B = ffffffffffff R+ + RF Co 'are e"n : and * we can conclude a ` a +` AF = fffff ideal @@@ 1 B f This eans that gain of the fffffcircuit in the reci'rocal of the closed loo' volt gain A b n other words for given #+ and #. the values of A. and & are fi7ed. /0n A1B is an alternative to e0n A:B .inally$ the closed loop voltage gain A . can be e7pressed in terms of open loop gain A and feedback circuit gain & as follows$ .rom e0n A6B$
b c b c b
1

b

c

b

R+ + R F c

c

)?

R+ + RF V fffff ffA AF = fffff9 = ffffffffffffffffffffffffffffffffffffffffff V in R+ + RF + AR+ Rearranging the E"n A
f

b

c

AF =

g R + R f f f f f f f f f f f f f f f f f f f f f f f f f f f f + F R + R + F f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f R + R AR f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f + F + + R+ + R F R+ + R F ` a V ffffff fffffffff R ffffffffffffff using e"n * B = ffffF = fffff+ V 9 R+ + R F ` a A AF = ffffffffffffffffffffffff @@@ 2 + + AB

A

where AF = closed loo' voltage gain A = o'en loo' voltage gain B = 2ain of the AB = loo' gain
F f f f f f f f circuit b

36 D+00&(&$,& +$4-% ./1%)'& +*&)119 >&(/ AV+*B #econsider e0n %9 M A %id %id M %9 5A -ince A is very large Aideally N B %id t 9 ---A).aB Ai.eB %+ t %6 --A).bB /0n A).bB says that the volt at the =on-inverting input terminal of an op-amp is appro7imately e0ual to that at the inverting input terminal provided that A$ is vey large. .rom the circuit diagram$ %+ M %in %6 M %. M #+ %9 5 #+ F#. -ub these values of %+ and %6 in e0n A).bB we get %in M #+ %9 5 #+ F#. Ai.eB A. M %9 5%in M +F#. 5#+ 46 I$4-% R&!+!%)$,& 8+%3 0&&*?),=: .rom the below circuit diagram #i -P input resistance #if -P input resistance of an op-amp with feedback Derivation of input resistance with .eedbackE

89

The input resistance with feedback is defined as$ V in f f f f f f V f f f f f f f f f f in Rif = ffff =V f f f f f f f f f f I in id
Ri

3owever, V9 A f f f f V id = ffff andV 9 = fffffffffffffffffffffV in Ah + + AB i V f f f f f f f f f f j in k Rif = Ril V
f f f f f f f f 9

A

V f f f f f f f f f f f f f f f f f f f in = ARi fff AV f f f f f f f f f f f f f f f f f f f f f f f f in V ffffffff + + AB a ` a f f f f f f f f f f f f f f f f f f f f f f f f f f = ARi ffffin V in = Ri + + AB A a ` ` a Rif = Ri + + AB @@ 8 This means that the input resistance of the op-amp with feedback is AiFA&B times that without feedback.
+ + AB ` a

8+

56 O-%4-% R&!+!%)$,& 8+%3 0&&*?),=:

This resistance can be obtained by using TheveninHs theorem. To find out o5p resistance with feedback #,. reduce independent source %in to 4ero$ apply an e7ternal voltage % 9 $ and calculate the resulting current i9 . The #,. is defined as follows$ #,. M %9 5i9 ---A?.aB 3CL at o5p node G=H we get$ i9 M ia F ib -ince AA#. F #+ BYY #i PP #9 and i9 PP ib . i9 t ia The current i9 can be found by writing 3%L e0n for the o5p loop %9 ! #9 i9 ! A%id M 9 i9 M %9 ! A%id --------#9 %id M %+ - %6 86

M 9 - %. R+ V f f f f f f f f f f f f f f f f f 9 V id = @ fffffff = @BV 9 R+ + RF V ffff+ ABV f f f f f f f f f f f f f f f f f f f f f f f f f f f 9 i9 = ffff9 R9 ` a Sub the value of in'ut is in e"n ?α Vf f f f f f f f f f f f f f f f f 9 ROF = fffffffffffffff ABV f f f f V 9 + ffffffffffffffff9
R9

V9 f f f f f f f f f f f f f f f f f = R9 ffffffffffffffffff V 9 + ABV 9 R9ffffffffff ` a ROF = fffffffffff @@@@ ? A b + + AB This result shows that the output resistance of the voltage series feedback amplifier is +5A+FA&B the output resistance of #9 the op-amp. Ai.eB The output resistance of the op-amp with feedback is much smaller than the output resistance without feedback. :6 B)$*8+*%3 8+%3 0&&*?),=: The bandwidth of the amplifier is defined as the band Arange of fre0uencyB for which the gain remains constant. The .re0uency at which the gain e0uals + is known as unity gain bandwidth AD(&B. The relationship between the breakfre0uency f9 $ open loop volt gain A$ bandwidth with feedback f. and closed loop gain A. . .or an op-amp with a single break fre0uency f 9 $ the gain bandwidth product is constant and e0ual to the unity-gain bandwidth. AD(&B. D(& M AAB Af9 B ----A+9.aB A M open loop volt gain f9 M break fre0uency of an op-amp AAorB only for a single break fre0uency op-amp D(& M A . f. ---A+9.bB A. M closed loop volt gain f. M bandwidth with feedback. /0uating e0n +9.a and +9.b Af9 M A. f. f. M Af9 5A. A. M A5A+FA&B 8: -----A+9.cB .or the non-inverting amplifier with feedback

-ub the value of A. in e0n +9.c$ we get f. M Af9 5 A5A+FA&B f. M A+F A&B f9 ----A+9.dB e0n +9.d -P bandwidth of the non-inverting amplifier with feedback is M bandwidth of the with feedback f9 times A+FA&B <6 T/%)1 //4 /00!&% ./1%)'& 8+%3 0&&*?),= AV/-%B n an open loop op-amp the total o5p offset voltage is e0ual to either the Fve or !ve saturation volt. %out M Fve AorB !ve saturation volt. >ith feedback the gain of the =on-inverting amplifier changes from A to A5A+FA&B$ the total output offset voltage with feedback must also be +5A+FA&B times the voltage without feedback. Ai.eB Total o5p offset %out with feedback M Total o5p offset volt without feedback --------------------------------------------+FA& %out M Z%sat --------+FA& +5A+FA&B is U and Z%sat M -aturation voltages. The ma7imum voltages the output of an op-amp can reach. =oteE ,pen-loop even a very small volt at the input of an op-amps can cause to reach ma7imum value AF %sat Bbecause of its very high volt gain. According to e0n for a gain op-amp circuit the %out is either Fve or !ve volt because %sat can be either Fve or !ve. Conclusion of =on- nverting Amplifier with feedbackE The char of the perfect volt AmplifierE +. t has very high input resistamce. 6. %ery low output resistance :. -table volt gain *. large bandwidth 8* ----A++B

81