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Counter Design Exercises

Engr. J. S. Cansino

Exercises on Designing of Counter Circuits
• Mod 4 Binary Up/Down Counter Example:
Design a circuit to build a Mod 4, two bit binary up/down counter. T e counter cycles !rom 0ð 1ð ð !ð 0ð 1... w en "#0 or: !ð ð 1ð 0ð !ð ... w en "#1 T is circuit can be represented by t e "tate Transition Diagram in !ig. #.$ below.
Construct t$e State %ransition Diagra& for Counter Circuit

T e "T%TE" & binary number' are represented using ( !lip)!lops* eac !lip)!lop represents $ binary digit. T e !lip)!lops can remember what has happened in the past, or what value has been stored in them. T ere will be one external input+ , w ic controls t e direction o! t e count: U- !or ,./+ and D012 !or ,.$. T e state of the flip-flops, representing the 2-bit binary number &t e count' will be t e only circuit output. 1e could design t is circuit using 34+ D or T !lip)!lops+ but in t is example we5ll use D !lip)!lops. 1 en we are !inis ed t e circuit will loo6 somet ing li6e t is incomplete circuit:
lig ts "
DB Clc 7B5 7B

$8-age

/. Cansino D% Clc 7% 7%5 c'oc( 0ur tas6 is to design t e circuit+ suc t at t e !lip !lop inputs will produce t e current )ext State outputs. (. "tarting wit D !lip !lop solution. 1e will illustrate t e solution using bot D !lip !lops and 34 !lip !lops. 4. Use 4)maps to simpli!y t e !lip)!lop input e:uations./ . Draw t e logic diagram wit !lip)!lops and combinational gates as speci!ied by t e !lip)!lop input e:uations./1 . *resent State . S..01 D/ D0 Deri9e t e next)state e:uation using t e 4)mapping met od: .Counter Design Exercises Engr. . T e design procedure we will !ollow !or t is problem will be: Design *rocedure+ $.0 0 0 " 0 1 0 1 1 1 1 0 (8-age . J. 0btain t e "tate Table !rom t e problem statement o! !rom t e "tate Transition Diagram.nputs .nput )ext State -'ip -'op . Deri9e t e !lip)!lop input e:uations !rom t e next state conditions in t e state table.0 " .

Cansino D%.Counter Design Exercises Engr. 0 1 1 1 1 0 Draw t e logic diagram !or t is counter circuit: lig ts " DB Clc 7B5 7B D% Clc 7% 7%5 c'oc( Complete t e solution using 34 !lip !lops is s own on t e !ollowing page. S. .0 0 0 " 0 1 DB./1 .8-age 0 0 0 0 1 1 1 0 0 1 1 0 0 1 .01 J/ 2/ J0 0 ð1 1 ð0 1 ð1 Complete t e 34 Excitation table 9alues to determine inputs to 34 !lip !lops+ w ic will cause correct transitions.0 " 0 1 0 1 0 1 0 .nput )ext State -'ip -'op ./ .nputs 0 ð0 20 ./. . J. *S )S J 2 input *resent State .

/./. Cansino 1 1 1 34 <=>.0 .0 0 0 . 0 1 1 1 1 0 ./.C" 0 0 0 1 1 1 1 0 3B.<=0. J. Deri9ing t e next)state e:uations using 4)mapping: JK FLIP FLOP #1 .?$ corresponds to most signi!icant bit o! t e ( bit binary number+ w ile !lip !lop ?( represents t e least signi!icant bit.0 0 0 .C" 0 0 0 1 1 1 1 0 4B .Counter Design Exercises Engr.0 . 0 1 1 1 1 0 . 0 0 0 1 1 1 1 0 48-age . S./.C" 0 0 0 1 1 1 1 0 4% .C" 0 0 0 1 1 1 1 0 3%. 0 0 0 1 1 1 1 0 JK FLIP FLOP #2 .

Counter Design Exercises Engr.. A8-age . @our counter !or t e se:uence o! numbers s ould ad9ance up or down based on a control variable input. %ssume t e se:uence wraps around at bot$ ends... <or example+ i! you a9e selected se:uence 1!43 and t e counter started up at $+ wit control input at one &C. J. S.. 1 en contro' 4ariab'e C#1. Cansino Draw t e logic diagram !or circuit implementation: -roblem ?(: Design a circuit t$at cyc'e t$roug$ t$e nu&bers+ 1ð!ð4ð3ð ð1ð!ð4ð. ad4ance forward+ w ile a control input o! C#0 s$ou'd cause a bac(ward &o4e in t e se:uence..$'+ se9en cloc6 pulses s ould cause t e !ollowing transitions: 1ð!ð4ð3ð ð1ð!ð4ð..

Cansino 1. #8-age . <ill in t e State %ab'e below+ !or your se:uence+ using t e completed 34 excitation 9alues in t e small table below. S.Counter Design Exercises Engr. Draw t$e State %ransition Diagra&+ (. J.

Present State input Next State -'ip -'op .Counter Design Exercises Engr. J. Cansino *S )S J 2 input 0ð 0 0ð 1 1ð 0 1ð 1 <or now lea9e t e rows associated wit t e unused numbers empty !or now./ 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 .nputs .C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 E 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 . 1 / . =ater a!ter we !ill in t e 4)maps we will come bac6 and explore w at appens i! t e circuit e9er gets into one o! t ese states. 1 C J/ 2/ J0 20 JC 2C 5 0 1 ! 4 3 6 7 B8-age .0 1 .0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 . S.

J. Cansino C8-age . S.Counter Design Exercises Engr.

/. J.CE 0 0 0 1 1 1 1 0 3%.CE 0 0 0 1 1 1 1 0 4% .CE 0 0 0 1 1 1 1 0 JC # 0 1 1 1 1 0 . Cansino JK FLIP FLOP #1 .0 0 0 .CE 0 0 0 1 1 1 1 0 20 # JK FLIP FLOP #3 0 0 0 1 1 1 1 0 .CE 0 0 0 1 1 1 1 0 2C # 0 0 0 1 1 1 1 0 D8-age . 0 0 0 1 1 1 1 0 JK FLIP FLOP #2 .0 . S.0 0 0 ./.CE 0 0 0 1 1 1 1 0 J0 # 0 1 1 1 1 0 ./.0 0 0 .0 ./.0 ./.Counter Design Exercises Engr. 0 1 1 1 1 0 ./.

Cansino Circuit Diagram Control Input E________________________________________________________ J/ .0 88 JC .Counter Design Exercises Engr.0 2C    $/ 8 . S. J.C 88 .C 2/ 20 ./ 88 ./ J0 .a g e .