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Chapter 8

Memory Testing and Built-In Self-Test

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EE141 VLSI Test Principles and Architectures

Ch. 8 - Memory Testing & BIST - P. 1

What is this chapter about?
Basic concepts of memory testing and BIST Memory fault models and test algorithms Memory fault simulation and test algorithm generation
RAMSES: fault simulator TAGS: test algorithm generator

Memory BIST
BRAINS: BIST generator
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EE141 VLSI Test Principles and Architectures

Ch. 8 - Memory Testing & BIST - P. 2

Typical RAM Production Flow
Wafer Full Probe Test Laser Repair Packaging

Marking

Post-BI Test

Burn-In (BI)

Pre-BI Test

Final Test

Visual Inspection

QA Sample Test

Shipping

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Ch. 8 - Memory Testing & BIST - P. 3

Memory Testing & BIST . 4 . 8 .Off-Line Testing of RAM Parametric Test: DC & AC Reliability Screening Long-cycle testing Burn-in: static & dynamic BI Functional Test Device characterization – Failure analysis Fault modeling – Simple but effective (accurate & realistic?) Test algorithm generation – Small number of test patterns (data backgrounds) – High fault coverage – Short test time 4 EE141 VLSI Test Principles and Architectures Ch.P.

P. 8 . 5 .Memory Testing & BIST .DRAM Functional Model Address Refresh Address latch Column decoder Refresh logic Row decoder Memory cell array Write driver Sense amplifiers Data register Data flow Control flow Data out Data in Read/write & chip enable 5 EE141 VLSI Test Principles and Architectures Ch.

6 .P.DRAM Functional Model Example 6 EE141 VLSI Test Principles and Architectures Ch.Memory Testing & BIST . 8 .

P.Memory Testing & BIST . New fault models are being proposed to cover new defects and failures in modern memories: New process technologies New devices 7 EE141 VLSI Test Principles and Architectures Ch. 7 .Functional Fault Models Classical fault models are not sufficient to represent all important failure modes in RAM. Functional fault models are commonly used for memories: They define functional behavior of faulty memories. 8 . Sequential ATPG is not possible for RAM.

Memory Testing & BIST .Static RAM Fault Models: SAF/TF Stuck-At Fault (SAF) Cell (line) SA0 or SA1 – A stuck-at fault (SAF) occurs when the value of a cell or line is always 0 (a stuck-at-0 fault) or always 1 (a stuckat-1 fault). a 0 and a 1 must be read. 8 . 8 . – A cell has a transition fault (TF) if it fails to transit from 0 to 1 (a <↑/0> TF) or from 1 to 0 (a <↓/1> TF). – A test that detects all SAFs guarantees that from each cell.P. 8 EE141 VLSI Test Principles and Architectures Ch. Transition Fault (TF) Cell fails to transit from 0 to 1 or 1 to 0 in specified time period.

8 . multiple cells are accessed – A certain cell can be accessed by multiple addresses 9 EE141 VLSI Test Principles and Architectures Ch. no cell will be accessed – A certain cell is never accessed by any address – Given a certain address. 9 .P.Memory Testing & BIST .Static RAM Fault Models: AF Address-Decoder Fault (AF) An address decoder fault (AF) is a functional fault in the address decoder that results in one of four kinds of abnormal behavior: – Given a certain address.

Memory Testing & BIST . a broken word line. A read to this cell will produce the previously read value.g.Static RAM Fault Models: SOF Stuck-Open Fault (SOF) A stuck-open fault (SOF) occurs when the cell cannot be accessed due to.P. 10 . 8 . 10 EE141 VLSI Test Principles and Architectures Ch.. e.

11 . 11 EE141 VLSI Test Principles and Architectures Ch. or operation on. another cell.P. Inversion Coupling Fault (CFin) – Transition in coupling cell complements (inverts) coupled cell.Memory Testing & BIST . 8 . State Coupling Fault (CFst) – Coupled (victim) cell is forced to 0 or 1 if coupling (aggressor) cell is in given state.RAM Fault Models: CF Coupling Fault (CF) A coupling fault (CF) between two cells occurs when the logic value of a cell is influenced by the content of. Idempotent Coupling Fault (CFid) – Coupled cell is forced to 0 or 1 if coupling cell transits from 0 to 1 or 1 to 0.

P. 8 . 12 .Memory Testing & BIST .Intra-Word & Inter-Word CFs 12 EE141 VLSI Test Principles and Architectures Ch.

P.RAM Fault Models: DF Disturb Fault (DF) Victim cell forced to 0 or 1 if we (successively) read or write aggressor cell (may be the same cell): – Hammer test Read Disturb Fault (RDF) – There is a read disturb fault (RDF) if the cell value will flip when being read (successively).Memory Testing & BIST . 8 . 13 EE141 VLSI Test Principles and Architectures Ch. 13 .

14 .P. 8 .RAM Fault Models: DRF Data Retention Fault (DRF) DRAM – Refresh Fault – Leakage Fault SRAM – Leakage Fault Static Data Losses---defective pull-up 14 EE141 VLSI Test Principles and Architectures Ch.Memory Testing & BIST .

6s 6.62s 10.P.23m 5.43y 23y 366y 57c 915c 15 EE141 VLSI Test Principles and Architectures Ch.9s 17s 1.Test Time Complexity (100MHz) Size 1M 16M 64M 256M 1G 4G 16G N 0.6s 26s 1.6h N1.2s 3. 15 .8m 7m 28m NlogN 0.8m 10N 0.16s 0.66s 2.Memory Testing & BIST . 8 .01s 0.1s 1.5s 42s 2.5 11s 11m 1.3m 22.4m 1.5h 12h 4d 32d 255d N2 3h 33d 1.

8 .RAM Test Algorithm A test algorithm (or simply test) is a finite sequence of test elements: A test element contains a number of memory operations (access commands) – Data pattern (background) specified for the Read and Write operation – Address (sequence) specified for the Read and Write operations A march test algorithm is a finite sequence of march elements: A march element is specified by an address order and a finite number of Read/Write operations 16 EE141 VLSI Test Principles and Architectures Ch.Memory Testing & BIST .P. 16 .

⇓ (r1. 8 .P.March Test Notation ⇑: address sequence is in the ascending order ⇓: address changes in the descending order : address sequence is either ⇑ or ⇓ r: the Read operation Reading an expected 0 from a cell (r0). reading an expected 1 from a cell (r1) w: the Write operation Writing a 0 into a cell (w0).Memory Testing & BIST . w0)} 17 EE141 VLSI Test Principles and Architectures Ch. writing a 1 into a cell (w1) Example (MATS+): {c (w0). w1).⇑ (r0. 17 .

18 .….Memory Testing & BIST . and the memory is initialized to the proper value before each march element Solid background (pattern) Complexity is 4N {c ( w 0 ). c ( w1).wb) and ⇓(rb. 8 . c ( r1)} 18 EE141 VLSI Test Principles and Architectures Ch.wa).P.Classical Test Algorithms: MSCAN Zero-One Algorithm [Breuer & Friedman 1976] Also known as MSCAN SAF is detected if the address decoder is correct (not all AFs are covered): – Theorem: A test detects all AFs if it contains the march elements ⇑(ra.…. c ( r 0 ).

DRF. and half of the TFs – Not good for AFs.P. shorts between cells.Classical Test Algorithms: Checkerboard Checkerboard Algorithm Zero-one algorithm with checkerboard pattern Complexity is 4N Must create true physical checkerboard. not logical checkerboard For SAF. 8 . and some CFs cannot be detected 1 0 1 0 1 0 1 0 1 19 EE141 VLSI Test Principles and Architectures Ch.Memory Testing & BIST . 19 .

For BC = 0 to N-1 { Complement BC. 2. CFs. Write background 1. and SAFs are detected and located 1. } 3. OC != BC. { Read BC. Repeat Step 2. } Complement BC. 20 .P.Classical Test Algorithms: GALPAT Galloping Pattern (GALPAT) Complexity is 4N**2─only for characterization A strong test for most faults: all AFs. For OC = 0 to N-1. TFs. Write background 0. 4.Memory Testing & BIST . 8 . EE141 VLSI Test Principles and Architectures BC 20 Ch. Read OC.

8 . except that BC is read only after all others are read. 21 .Classical Test Algorithms: WALPAT Walking Pattern (WALPAT) Similar to GALPAT.P.Memory Testing & BIST . Complexity is 2N**2. BC 21 EE141 VLSI Test Principles and Architectures Ch.

P. 22 . except for some CFs Complexity is 4N**1. 1 1 1 1 1 22 EE141 VLSI Test Principles and Architectures Ch.Classical Test Algorithms: Sliding Sliding (Galloping) Row/Column/Diagonal Based on GALPAT. but instead of shifting a 1 through the memory. a complete diagonal of 1s is shifted: – The whole memory is read after each shift Detects all faults as GALPAT.Memory Testing & BIST .5. 8 .

For BC = 0 to N-1 { Complement BC. } 3. Read cell @ dist south from BC. Write background 1. 23 . } 8 Complement BC. 2. dist *= 2.1 0 Read cell @ dist west from BC.Memory Testing & BIST . dist = 1. While dist <= mdist /* mdist < 0.5 col/row length */ 6 { Read cell @ dist north from BC. 8 . 9 4 5 . repeat Step 2.P. 3 Read BC. 1 Read cell @ dist east from BC. Write background 0.Classical Test Algorithms: Butterfly Butterfly Algorithm Complexity is 5NlogN All SAFs and some AFs are detected 1. EE141 VLSI Test Principles and Architectures 2 7 23 Ch.

⇑ (r1. r0). w1. r0)} – Parametric (12NlogN): for Read access time 2 successive Reads @ 2 different addresses with different data for all 2-address sequences differing in 1 bit Repeat T2~T5 for each address bit GALPAT---all 2-address sequences 24 EE141 VLSI Test Principles and Architectures Ch.Classical Test Algorithms: MOVI Moving Inversion (MOVI) Algorithm For functional and AC parametric test – Functional (13N): for AF. r1). and most CF {⇓ (w0).⇓ (r0.⇑ (r0. 24 .P. TF. w0. r1). w0. 8 . SAF. w1.⇓ (r1.Memory Testing & BIST .

Memory Testing & BIST .q-1].q] /* row p and column q */ { Write 0 in cell[p.q]. For each cell[p. } 2. 1. Read 0 from cell[p. Write 0 in cell[p.q].q]. Read 0 from cell[p. Designed on the premise that DRAM cells are most susceptible to interference from their nearest neighbors (eliminates global sensitivity checks). Read 0 from cell[p.Classical Test Algorithms: SD Surround Disturb Algorithm Examine how the cells in a row are affected when complementary data are written into adjacent cells of neighboring rows.P. Repeat Step 1 with complementary data. Write 1 in cell[p+1. EE141 VLSI Test Principles and Architectures 1 0 0 1 0 25 Ch. Write 0 in cell[p.q+1].q+1].q]. 25 .q-1]. Write 1 in cell[p-1. 8 .

⇓ ( r1. w1). w0). w1).P. w 0)} 26 EE141 VLSI Test Principles and Architectures Ch.& AND-type AFs and SAFs The suggested test for unlinked SAFs {c ( w 0).c (r0)} MATS+ For both OR.c (r1)} AND-type address decoder fault {c (w1). 8 .Simple March Tests Zero-One (MSCAN) Modified Algorithmic Test Sequence (MATS) OR-type address decoder fault {c (w0).c (r1.c (r0. 26 .Memory Testing & BIST . ⇑ ( r 0.

27 . and TF (but only part of the CFs) It is a complete test. r1)} 27 EE141 VLSI Test Principles and Architectures Ch. with the data reversed For AF. ⇑ ( r 0. all faults that should be detected are covered It however is a redundant test. w0.e.Memory Testing & BIST . ⇓ ( r 0. then read and write back complement values (and read again to verify) for all cells (from cell 0 to n-1. and then from cell n-1 to 0). w1. 8 . r1). because only the first three march elements are necessary {⇑ ( w0). w1. w0. r 0). in 7N time Marching-0: follows exactly the same pattern.P. SAF. r 0).March Tests: Marching-1/0 Marching-1/0 Marching-1: begins by writing a background of 0s. ⇑ ( r1. ⇓ ( r1. i.. ⇑ ( w1).

but allow for the coverage of TFs The suggested test for unlinked SAFs & TFs {c ( w0). ⇓ (r1.P. 8 . w0.March Tests: MATS++ MATS++ Also for AF. ⇑ (r0.Memory Testing & BIST . 28 . SAF. r0)} 28 EE141 VLSI Test Principles and Architectures Ch. w1). and TF Optimized marching-1/0 scheme—complete and irredundant Similar to MATS+.

⇓ (r1. SAF.⇑ (r0.c (r0)} March C For AF.P. & all CFs. w0). TF. w0).⇑ (r0. but semi-optimal (redundant) {c ( w0).Memory Testing & BIST . 29 .c (r0)} 29 EE141 VLSI Test Principles and Architectures Ch.March Tests: March X/C March X Called March X because the test has been used without being published For AF. TF. w1). w1). & CFin {c (w0). w1). w0). ⇓ (r0. 8 .⇑ (r1. ⇓ (r1. c (r0). SAF.

w 1.P.c(r0)} Extended March CCovers SOF in addition to the above faults {c(w0).⇓(r1. w0). 30 . 8 . TF.⇑(r0.March Tests: March CMarch CRemove the redundancy in March C Also for AF. w0). w0). r1).⇓ (r0.c(r0)} 30 EE141 VLSI Test Principles and Architectures Ch.⇑(r1.⇑ (r1. & all CFs Optimal (irredundant) {c(w0).Memory Testing & BIST . SAF.⇓(r0.⇓ (r1.⇑ (r0. w 1). w 1). w0). w 1).

8 .Fault Detection Summary 31 EE141 VLSI Test Principles and Architectures Ch.P.Memory Testing & BIST . 31 .

32 . 8 .P.Memory Testing & BIST .Comparison of March Tests SAF TF AF SOF CFin CFid CFst MATS++ March X March Y March Cˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ 32 EE141 VLSI Test Principles and Architectures Ch.

Word-Oriented Memory A word-oriented memory has Read/Write operations that access the memory cell array by a word instead of a bit. 33 .Memory Testing & BIST .P. 8 . Word-oriented memories can be tested by applying a bit-oriented test algorithm repeatedly with a set of different data backgrounds: The repeating procedure multiplies the testing time 33 EE141 VLSI Test Principles and Architectures Ch.

01010101. so complexity is 4*6N/8=3N Note: b is the complement of a 34 EE141 VLSI Test Principles and Architectures Ch. 00110011. ra)} Conventional method is to use logm+1 different backgrounds for m-bit words Called standard backgrounds m=8: 00000000.P. 8 . ⇑ (ra. wb).Memory Testing & BIST . 34 . ⇓ (rb.Testing Word-Oriented RAM Background bit is replaced by background word MATS++: {c (wa). and 00001111 Apply the test algorithm logm+1=4 times. wa.

. Approaches: 1. 8 . 35 . 04/02 35 EE141 VLSI Test Principles and Architectures Ch.Cocktail-March Algorithms Motivation: Repeating the same algorithm for all logm+1 backgrounds is redundant so far as intra-word coupling faults are concerned Different algorithms target different faults.P.Memory Testing & BIST . Use multiple backgrounds in a single algorithm run 2. Merge and forge different algorithms and backgrounds into a single algorithm Good for word-oriented memories Ref: Wu et al. IEEE TCAD.

wa.Memory Testing & BIST .March-CW Algorithm: March C. as compared with extended March CImprovement increases as m increases Ref: Wu et al.for solid background (0000) Then a 5N March for each of other standard backgrounds (0101. 8 . rb.P. 04/02 36 EE141 VLSI Test Principles and Architectures Ch. wb. 0011): Results: {c (wa. where m is word length and N is word count Test time is reduced by 39% if m=4. IEEE TCAD.. ra)} Complexity is (10+5logm)N. 36 .

37 .Multi-Port Memory Fault Models Cell Faults: Single cell faults: SAF. 8 .P. TF. RDF Two-cell coupling faults – Inversion coupling fault (CFin) – State coupling fault (CFst) – Idempotent coupling fault (CFid) Port Faults: Stuck-open fault (SOF) Address decoder fault (AF) Multi-port fault (MPF) 37 EE141 VLSI Test Principles and Architectures Ch.Memory Testing & BIST .

P.Memory Testing & BIST . 8 . 38 .2-Port RAM Topology BLA WLA Interport WL short WLA BLA 3 1 2 BLA BLA WLB WLB Interport BL short WLA WLA β α γ WLB WLB BLB EE141 VLSI Test Principles and Architectures BLB BLB BLB 38 Ch.

P.Memory Testing & BIST .Inter-Port Word-Line Short Fault-Free Faulty Port A Address 1 Cell 1 Address 1 Cell 1 Address 2 Port B Address 2 Cell 2 Address 3 Cell 2 Cell 3 * Functional test complexity: O(N3) 39 EE141 VLSI Test Principles and Architectures Ch. 8 . 39 .

40 . 8 .P.Memory Testing & BIST .Inter-Port Bit-Line Short Fault-Free Address α Port A Address α Cell α Address β Cell β Faulty Cell α Address α Port B Address β Cell β Address β Cell α Cell β * Functional test complexity: O(N2) 40 EE141 VLSI Test Principles and Architectures Ch.

In addition to bit-oriented memories. wordoriented memories can be simulated easily even with multiple backgrounds. 8 . especially when the number of fault models is large.Memory Testing & BIST . Fault dictionary can be constructed for easy diagnosis.Why Memory Fault Simulation? Fault coverage evaluation can be done efficiently. 41 EE141 VLSI Test Principles and Architectures Ch.P. Test algorithm design and optimization can be done in a much easier way. Detection of a test algorithm on unexpected faults can be discovered. 41 .

42 . Report error output.Memory Testing & BIST . 8 . } 42 EE141 VLSI Test Principles and Architectures /* N**2 for 2-cell CF */ /* N for March */ Ch. For each test element { Apply test element.Sequential Memory Fault Simulation Complexity is N**3 for 2-cell CF For each fault Inject fault.P.

& Wu.P.Memory Testing & BIST . 8 . 43 .s/1> AGR := v0 SPT := * /* All other cells are suspects */ VTM := r0 RCV := w1 43 EE141 VLSI Test Principles and Architectures Ch. DFT99 & IEEE TCAD 4/02] Each fault model has a fault descriptor # S/1 AGR := w0 SPT := @ VTM := r0 RCV := w1 /* Single-cell fault */ # CFst <0. Huang.Parallel Fault Simulation RAMSES [Wu.

} 44 EE141 VLSI Test Principles and Architectures Ch. If op is RCV then release victim cells. 8 . 44 .RAMSES Complexity is N**2 For each test operation { If op is AGR then mark victim cells.P.Memory Testing & BIST . If op is VTM then report error.

45 .P.RAMSES Algorithm 45 EE141 VLSI Test Principles and Architectures Ch.Memory Testing & BIST . 8 .

8 . > 46 EE141 VLSI Test Principles and Architectures Ch. 46 .RAMSES Example for CFin< .Memory Testing & BIST .P.

75 1 1 1 .P.Memory Testing & BIST .625 1 ☞ Extended March C.5 1 .has 100% coverage of SOF 47 EE141 VLSI Test Principles and Architectures Ch.002 1 .625 .002 . 8 .375 .Coverage of March Tests SAF TF AF SOF CFin CFid CFst MA TS++ March X March Y March C1 1 1 1 1 1 1 1 1 1 1 1 1 .5 .5 . 47 .

Memory Testing & BIST . generate a test with 100% fault coverage Given a set of target fault models and a test length constraint. generate a test with the highest fault coverage Priority setting for fault models Test length/test time can be reduced Diagnostic test generation Need longer test to distinguish faults 48 EE141 VLSI Test Principles and Architectures Ch.Test Algorithm Generation Goals Given a set of target fault models.P. 48 . 8 .

P.r0) ↑(w) ↑(r.w). 8 .w1).r) (w)(rw)(rwr) 49 EE141 VLSI Test Principles and Architectures Ch.Test Algorithm Generation by Simulation (TAGS) March template abstraction: ↑(w0).w. ↓(r. ↑(r0. ↓(r1.w0. 49 .Memory Testing & BIST .

Template Set
Exhaustive generation: complexity is very high, e.g., 6.7 million templates when N = 9 Heuristics should be developed to select useful templates
T(1N) (w)

T(2N) T(3N)

(ww) (www) (wwr)

(w)(w)

(wr)

(w)(r)

(ww)(w) (wrw)

(w)(ww) (wr)(w) (w)(rw) ….
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Ch. 8 - Memory Testing & BIST - P. 50

TAGS Procedure
1. 2. 3. 4. 5. 6. 7.

Initialize test length as 1N, T(1N) = {(w)}; Increase test length by 1N: apply generation options; Apply filter options; Assign address orders and data backgrounds; Fault simulation using RAMSES; Drop ineffective tests; Repeat 2-6 using the new template set until constraints met;

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Template Generation/Filtering
Generation heuristics:
(r) insertion (…r), (r…) expansion (w) insertion (…w), (w…) expansion

Filtering heuristics:
Consecutive read: (…rr…) Repeated read: (r)(r) Tailing single write: …(w)

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Ch. 8 - Memory Testing & BIST - P. 52

TF. 53 . AF.Memory Testing & BIST .P. 8 . Cfin. Cfid. time constraints ∞: 53 EE141 VLSI Test Principles and Architectures Ch.TAGS Example (1/2) Target fault models (SAF. CFst). SOF.

TAGS Example (2/2)

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Ch. 8 - Memory Testing & BIST - P. 54

RAMSES Simulation Results

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Ch. 8 - Memory Testing & BIST - P. 55

FC Spectrum for 6N Tests

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Ch. 8 - Memory Testing & BIST - P. 56

Memory Testing & BIST . 3.P. Construct bit-oriented test algorithms Generate initial Cocktail-March: Assign each data background to the test in Step 1─a cascade of multiple March algorithms Optimize the Cocktail-March (!P1) /* non-solid backgrounds */ Optimize the Cocktail-March (P1) /* solid background */ 57 EE141 VLSI Test Principles and Architectures Ch. 4. 57 . 2. 8 .Word-Oriented TAGS 1.

58 EE141 VLSI Test Principles and Architectures Ch.Memory Testing & BIST . 58 . 8 . Cocktail March Optimization (!P1) For each non-solid data background P (P != P1) a) Generate a new Cocktail–March test by replacing the March algorithm having P as its background with a shorter one from the set of algorithms generated in Step 1.3. d) Store the test algorithm candidates used in the previous step.P. b) Run RAMSES for the new Cocktail–March. c) Repeat 3(a) and 3(b) until the FC drops and cannot be recovered by any other test algorithm of the same length.

P. 8 .4.Memory Testing & BIST . Cocktail March Optimization (P1) a) b) c) Generate a new Cocktail–March test by replacing the March algorithm having P1 as its background with a shorter one from the test set generated in Step 1. 59 EE141 VLSI Test Principles and Architectures Ch. Repeat 4(a) and 4(b) for all candidate test algorithms from 3(d) until the FC drops and cannot be recovered by any other test algorithm of the same length or by selecting other candidates. 59 . Repeat with every test candidate for other backgrounds. Run RAMSES for the new Cocktail–March.

.Memory Testing & BIST .Cocktail March Example (m=8) Ref: Wu et al.P. IEEE TCAD. 8 . 4/02 60 EE141 VLSI Test Principles and Architectures Ch. 60 .

P. Can it support fault location and redundancy repair? Can it support BI? Can it support on-chip redundancy analysis and repair? Does it allow characterization test as well as mass production test? Can it really replace ATE (and laser repair machine)? Programmability. shorts. parallelism. 61 . currents. 8 . etc. threshold range. voltages.What Can BIST do? What are the functional faults to be covered? Static and dynamic Operation modes What are the defects to be covered? Opens. speed. timing accuracy.Memory Testing & BIST . timing parameters. 61 EE141 VLSI Test Principles and Architectures Ch. etc.

P. 1149. hierarchical) Patterns (address sequence) March & March-like Pseudorandom Others 62 EE141 VLSI Test Principles and Architectures Ch. 8 . 62 .Typical RAM BIST Approaches Methodology Processor-based BIST – Programmable Hardwired BIST – Fast – Compact Hybrid Interface Serial (scan.Memory Testing & BIST .1) Parallel (embedded controller.

P.Memory Testing & BIST .Typical RAM BIST Architecture Controller Test Collar (MUX) Pattern Generator RAM Go/No-Go Comparator BIST Module RAM Controller 63 EE141 VLSI Test Principles and Architectures Ch. 8 . 63 .

EDO DRAM BIST Example 64 EE141 VLSI Test Principles and Architectures Ch.P.Memory Testing & BIST . 64 . 8 .

DRAM Page-Mode Read-Write Cycle 65 EE141 VLSI Test Principles and Architectures Ch. 8 .Memory Testing & BIST .P. 65 .

8 . 66 .P.BIST Architecture 66 EE141 VLSI Test Principles and Architectures Ch.Memory Testing & BIST .

P. 8 .Memory Testing & BIST .BIST External I/O MBS (Memory BIST Selection): controller test collar (normal/test mode selection) MBC (Memory BIST Control): Controller input MCK (Memory BIST Clock) MBR (Memory BIST Reset) MSI (Memory BIST Scan In): for test commands and scan test inputs MSO (Memory BIST Scan Out): for diagnostic data and scan test outputs MBO (Memory BIST Output): error indicator MRD (Memory BIST Output Ready): BIST completion flag 67 EE141 VLSI Test Principles and Architectures Ch. 67 .

P. 8 .Memory Testing & BIST . 68 .BIST I/O Summary 68 EE141 VLSI Test Principles and Architectures Ch.

P.1 TAP PLD Sequencer (Pattern Generator) Counter LFSR LUT PLD 69 EE141 VLSI Test Principles and Architectures Ch. 8 .Memory Testing & BIST . 69 .Controller and Sequencer Controller Microprogram Hardwired Shared CPU core IEEE 1149.

70 .Memory Testing & BIST . 8 .P.Controller 70 EE141 VLSI Test Principles and Architectures Ch.

8 .Memory Testing & BIST .Sequencer D Q Combination Logic #0 Combination Logic #1 Row Address Counter Column Address Counter Control Counter D Q D Q D Q BIST Controller D Q D Q eDRAM D Q D Q State Flags MCK Comparator eDRAM control signal MCK 71 EE141 VLSI Test Principles and Architectures Ch.P. 71 .

Sequencer States Disable BIST_EN=low SEQ_EN=low All outputs and flags are high-z Idle& Wait BIST_EN=high SEQ_EN=low All outputs and flags are in precharged state Reset/Initiate BIST_EN=high SEQ_EN=high All outputs and flags seted to known state CBR Refresh NON_EDO A WD NON_EDO B RDWD' EDO_ROW EDO_ROW EDO_ROW Self Refresh EDO_COL 0 WD EDO_COL 1 RDWD' EDO_COL 2 RDWD'RD' Done & Change Command 72 EE141 VLSI Test Principles and Architectures Ch. 72 .Memory Testing & BIST .P. 8 .

etc. 8 . 4. RAM-Diagnosis Mode RAM-BI Mode 73 EE141 VLSI Test Principles and Architectures Ch.P. Data retention faults 3.Memory Testing & BIST . Functional faults 2.BIST Test Modes 1. 2.) 3. rise/fall times. Timing faults (setup/hold times. Scan-Test Mode RAM-BIST Mode 1. 73 .

8 .Memory Testing & BIST . Bit 0 Addressing order Data type Operations 000: EOT (End of test) 1: ⇑ (increasing) 1: d = DB (READ Cycle) 0: ⇓ (decreasing) 0: d = ~DB 001: Rd 010: Wd (Early WRITE Cycle) 011: RdW~d (READ-WRITE) Cycle EDO-PAGE-MODE 100: Wd (Early WRITE Cycle 101: RdW~d (READ-WRITE) Cycle 110: RdW~dR~d (READ Early WRITE Cycle) 111: Refresh 74 EE141 VLSI Test Principles and Architectures Ch.P.BIST Controller Commands Bit 4 Bit 3 Bit 2. 74 . Bit 1.

Memory Testing & BIST .BIST Control Sequence 75 EE141 VLSI Test Principles and Architectures Ch.P. 75 . 8 .

flash RAM Multiple cores RAM BIST compiler is the trend BRAINS (BIST for RAM in Seconds) Proposed BIST Architecture Memory Modeling Command Sequence Generation Configuration of the Proposed BIST 76 EE141 VLSI Test Principles and Architectures Ch. 8 .P. DRAM.Memory Testing & BIST .RAM BIST Compiler Use of RAM cores is increasing SRAM. 76 .

8 .P. 77 .Memory Testing & BIST .BRAINS Output Specification Synthesizable BIST design At-speed testing Programmable March algorithms Optional diagnosis support – BISD Activation sequence Test bench Synthesis script 77 EE141 VLSI Test Principles and Architectures Ch.

78 .Memory Testing & BIST .BRAINS Inputs and Outputs 78 EE141 VLSI Test Principles and Architectures Ch. 8 .P.

Memory Testing & BIST .General RAM BIST Architecture Programmable Memory BIST MCK MBS MBC MBR MSI MSO MRD MBO Controller Sequencer TPG Controls Test Collar Comparator Address D Q Memory Normal Access 79 EE141 VLSI Test Principles and Architectures Ch. 8 . 79 .P.

Memory Testing & BIST .P. 80 . Address Generator Control Module Sequence Generator command go Error Handling Module error signature 80 EE141 VLSI Test Principles and Architectures address Ch. 8 .Sequencer Block Diagram March element en done go Command Generator error info.

P. 81 .Memory Testing & BIST . output.Function of the TPG BIST Controller Sequencer TPG RAM The test pattern generator (TPG) translates high-level memory commands to memory input signals. and in/out Width Latency: number of clock cycles the TPG generates the physical signal after it receives a command from the sequencer Packet_length: number of different signal values packed within a single clock cycle 81 EE141 VLSI Test Principles and Architectures Ch. Four parameters to model a memory’s I/Os: Type: input. 8 .

82 .P.Memory Testing & BIST . 8 .Architecture of the TPG 82 EE141 VLSI Test Principles and Architectures Ch.

Multiple RAM Cores Controller and sequencer can be shared Test pattern generator sequencer controller Test pattern generator Ram Core B Ram Core A sequencer Test pattern generator Ram Core C 83 EE141 VLSI Test Principles and Architectures Ch. 83 .Memory Testing & BIST . 8 .P.

84 .Sharing Controller & Sequencer 84 EE141 VLSI Test Principles and Architectures Ch. 8 .P.Memory Testing & BIST .

85 .Memory Testing & BIST . 8 .Grouping and Scheduling 85 EE141 VLSI Test Principles and Architectures Ch.P.

BRAINS BIST Architecture External Tester MBS MSI MBO MRD MSO MBC MBR MCK Controller Memory BIST Sequencer Sequencer Sequencer TPG TPG TPG TPG TPG TPG RAM RAM RAM RAM RAM RAM Source: ATS’01 86 EE141 VLSI Test Principles and Architectures Ch. 86 . 8 .Memory Testing & BIST .P.

BRAINS GUI 87 EE141 VLSI Test Principles and Architectures Ch. 87 . 8 .Memory Testing & BIST .P.

Supported Memories The Built-In Memory List DRAM – EDO DRAM – SDRAM – DDR SDRAM SRAM – Single-Port Synchronous SRAM – Single-Port Asynchronous SRAM – Two-Port Synchronous Register File – Dual-Port Synchronous SRAM – Micron ZBT SRAM BRAINS can support new memory architectures easily 88 EE141 VLSI Test Principles and Architectures Ch. 88 . 8 .Memory Testing & BIST .P.

8 .P. 89 .Memory Testing & BIST .Examples 89 EE141 VLSI Test Principles and Architectures Ch.

8 .P.Area Overhead 90 EE141 VLSI Test Principles and Architectures Ch. 90 .Memory Testing & BIST .

91 .Memory Testing & BIST . 8 .P.Concluding Remarks BIST is considered the best solution for testing embedded memories: Low cost Effective and efficient Further improvement can be expected to extend the scope of RAM BIST: Timing/delay faults and disturb faults BISD and BISR CAM BIST and flash BIST BIST/BISD/BISR compiler Wafer-level BI and test – Known good die 91 EE141 VLSI Test Principles and Architectures Ch.