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Recommended JTAG Circuitry for Debug with Intel® Xscale™ Microarchitecture

Application Note
June 2001

Document Number: 273538-001

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.................................................................................................... 8 5........................................5 Requirements ...........................................................................................................................................................0 Introduction ...............................................................0 2..............................................7 Example JTAG Signals at Debug Start-Up ............................................................................ 5 JTAG Signals / Header ................................ 7 Hardware Requirements ...........................Recommended JTAG Circuitry for Debug with Intel® Xscale™ Microarchitecture Contents Contents 1.................. 6 System Requirements .................................................................................... 8 ARM* Multi-ICE* .................................................................................................................. 8 References ................................................................. 6 Example JTAG Signals at Power-Up ..............................................................0 3...... 9 Figures 1 2 3 4 JTAG Header.....0 4...............................................2 6..............................................................0 Macraigor Raven* and Wind River Systems visionPROBE* / visionICE* .. 8 Tables Application Note 3 ..................................................1 5........................................................0 5..................................................................................................................................................................... 7 Example Power-Up Circuit for nTRST .....

Description 4 Application Note .Recommended JTAG Circuitry for Debug with Intel® Xscale™ Microarchitecture Contents Revision History Date June 2001 Revision 001 Initial release.

0 Introduction Certain restrictions exist in order to use JTAG based debuggers with the Intel® XScale™ microarchitecture (ARM* Architecture compliant).Recommended JTAG Circuitry for Debug with Intel® Xscale™ Microarchitecture Introduction 1. This is primarily due to the Tap Controller reset requirements of the Intel® 80200 processor with Intel® XScale™ microarchitecture and the reset requirements of specific JTAG debuggers. The following sections outline these requirements along with suggestions for circuitry to alleviate potential problems. This is to ensure a fully initialized boundary scan chain. like many others. This requirement stems from the fact that the debugger can only assert nTRST (drive low). 2. Application Note 5 . requires that nTRST (Tap Reset) is asserted low during power up for at least 32 core clock cycles. The ARM∗ Multi-ICE∗ JTAG debugger requires that nTRST is always weakly pulled high.0 Requirements The Intel® 80200 processor with Intel® XScale™ microarchitecture. Both reset signals coming from the Multi-ICE (nTRST and nSRST) are open collector and must be weakly pulled high in order to avoid unintentional resets (System or TAP). Failure to comply with this requirement may result in spurious behavior of the application.

6 Application Note .Recommended JTAG Circuitry for Debug with Intel® Xscale™ Microarchitecture JTAG Signals / Header 3. JTAG Header VTref nTRST TDI TMS TCK RTCK TD0 nSRST DBGRQ DGBACK 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20 Vsupply GND GND GND GND GND GND GND GND GND A8982-01 The ARM Multi-ICE debugger along with the Macraigor Raven* and Wind River Systems∗ visionPROBE* / visionICE* utilize this connector. ARM Multi-ICE is configured as open collector only. The main difference to be noted is the specific implementation of nTRST for each debugger. The Macraigor Raven implementation actively drives nTRST (high and low).0 JTAG Signals / Header Figure 1 is the pin definition (20-pin standard ARM connector) for JTAG (See specific Product Design Guide for part number information). The Wind River Systems visionPROBE / visionICE can configure nTRST active or open collector (only drive low). Figure 1.

0 System Requirements In order to successfully invoke a debug session. “Example JTAG Signals at Debug Start-Up. the JTAG debug unit must be able to control nTRST and nSRST independently. Example JTAG Signals at Debug Start-Up VCC nTRST nSRST TCK TMS TDI TD0 A8979-01 Application Note 7 . See Figure 2. The nSRST signal allows the debugger to control system/processor reset in order to download the debug handler via the JTAG interface. Example JTAG Signals at Power-Up Figure 2. The nTRST signal allows the debugger to get the TAP controller in a known state. Note: Figure 2 and Figure 3 are examples and do not reflect actual signal timings.Recommended JTAG Circuitry for Debug with Intel® Xscale™ Microarchitecture System Requirements 4. “Example JTAG Signals at Power-Up and Figure 3. VCC nTRST nSRST TCK TMS TDI TD0 A8978-01 Figure 3.

2 ARM* Multi-ICE* The ARM Multi-ICE debugger requires special power-up circuitry due to the open collector implementation of the nTRST signal.1 Macraigor Raven* and Wind River Systems visionPROBE* / visionICE* Both the Macraigor Raven and Wind River Systems visionPROBE / visionICE (when configured as active) do not require any special power-up circuitry. It is suggested that the value of the pull-down resistor is 10kΩ or greater. Simply. The value of this resistor should be confirmed with the JTAG debugger manufacturer to ensure optimal performance.01µF MAX811S A8980-01 8 Application Note .3 V 1 kΩ 3 MR# RESET# 2 nTRST 220Ω 4 VCC GND 1 0. and ARM Multi-ICE. Example Power-Up Circuit for nTRST nTRST-DGB 3. See Figure 4. This power-up circuit must ensure that nTRST is asserted (low) at power on and weakly pulled high thereafter. 5. Note: This section does not discuss circuitry needed for nSRST. This circuit is a universal solution and will work with other JTAG debug systems.3 V 3. 5.Recommended JTAG Circuitry for Debug with Intel® Xscale™ Microarchitecture Hardware Requirements 5. it is necessary to incorporate a circuit that can drive nTRST low at power up and weakly pull it high at all other times. This section details the circuits required for nTRST when using the Macraigor Raven.0 Hardware Requirements Due to the conflicting requirements of Multi-ICE and the Intel® 80200 processor. the requirement is that nTRST is weakly pulled down at the processor. Wind River Systems visionPROBE / visionICE. “Example Power-Up Circuit for nTRST. due to varying system level requirements. Figure 4.

Max811/812 Datasheet (http://www.htm) 3.intel.0 References 1.intel.com/design/iio/docs/iop310.com/) 2.htm) 4. Intel® 80310 I/O Processor Chipset with Intel® XScale™ Microarchitecture Design Guide (http://developer.maxim-ic. Intel® 80200 Processor Evaluation Platform Board Schematics (http://proto-cps.arm. Multi-ICE System Design Considerations Application Note 72 (http://www.jf.com/) Application Note 9 .com/design/iio/docs/iop310.Recommended JTAG Circuitry for Debug with Intel® Xscale™ Microarchitecture References 6.

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