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Crafting a Chip

A Practical Guide to the
UofU VLSI CAD Flow

Erik Brunvand
School of Computing
University of Utah

August 24, 2006

Draft August 24. 2006 2 .

. . 35 3. . . . . . . .2. . . . . . 75 4.1 Generating a Behavioral View .3 Schematics that use Transistors . . . . . . 15 2. . . . 79 4. . . . . . and Cell Naming Restrictions . 80 . . . . . . . . . . .1 Verilog-XL: Simulating a Schematic . . . Pin. . . . . . . . . . . . . . .2 4. . . . . .1. . . . . .1 Verilog-XL . 38 3. . . . . . . . .Contents 1 Introduction 1. . . . . . . .5 4 9 Modifying Postscript Plot Files . . . . . 48 4. . . . . . .1 Cadence Design Framework . . . . . . 24 3. . . . . . . . . . . . . .2 NC Verilog: Simulating a Schematic . . 10 Cadence ICFB 15 2. . . . . . . .1 Starting Cadence and Making a new Working Library . 17 Composer Schematic Capture 23 3. . . .2 Simulating a Behavioral View .1. . .1 3. . 43 Verilog Simulation 4. . 67 Behavioral Verilog Code in Composer . . . . . . . . . . .2 Creating a New Cell . . . . . 42 Variable. . . .1 4. .2 Starting Cadence . . . . . . . . .4. 78 Stand-Alone Verilog Simulation . . . .3 45 Verilog Simulation of Composer Schematics . . . . . . . . . . . . .4 Printing Schematics . .1 2 3 Cad Tool Flows .2. . . . . . . . . . 75 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3. . . . . 49 4. . . 25 3. . . . . .

. . . . . . . .1 Generating an analog-extracted view . . .. . . . 106 Virtuoso Layout Editor 113 5. . . . . . . . . . . . . . . . . . . . . 98 4. . .2 Behavioral Gate Timing . 98 4. . . 137 5. . . . . . . . . .4 Transistor Timing . . 167 6. . . 152 5. . . . . . . . . . . . 171 6. 86 4. . . .3 Printing Layouts .3 Mixed Analog/Digital Simulation . . . . . .4. . . . . . 132 5. . . . . . . . . . . . . . . . .2 Simulating with a Config View .2 Overall Cell Design Flow (so far. . . . . . . . . . . . . .3 Standard Delay Format (SDF) Timing . . . .4. 152 Standard Cell Template . . . . .1 165 Simulating a Schematic . . . . . . . . . . . . .2 NC Verilog . . . . . . 104 4. . . . .) . . . . .2 Standard Cell I/O Pin Placement .1. . . . . . . . . . . . .3. . .4 Final Words about Mixed Mode Simulation . . . 141 5. . . . . . . .3 vcs . . . . . 101 4. . . . . . . . . . . . 2006 5. . 116 5. .6. . . . . . . . . . . . . . . . 160 Spectre Analog Simulator 6. . . .1 An Inverter Schematic . . 195 4 . . . . . . 154 5. . . .4. . .4 Design Rule Checking . . . . . . . . . . . . 141 5. 159 5. . . .7. . . . . .1 DIVA Design Rule Checking . . .4. . . . . . . .. . . . . . . . . .3.4 5 4. . . . . 135 5. . . . . .3. .7. . . . . . . . . . . .6. . 135 5. . . . . . . . . 193 DC Simulation . . . . . . . 179 6. . . . . . . . . . . . . . . . . . . . . . .1 Behavioral versus Transistor Switch Simulation . . .5 Generating an Extracted View . . . . . . . . . . . . .6 Layout Versus Schematic Checking .CONTENTS 4. . . 91 Timing in Verilog Simulations .1 Simulation with the Spectre Analog Environment . . .7 6 Draft August 24. . . .1 Virtuoso Command Overview . 113 5. . . . . . . . . . . . 176 6. . . . . .3 Standard Cell Transistor Sizing .2 Layout for an Inverter . . . . . . . . . . . . .1 Standard Cell Geometry Specification .4. 152 5. . . . . . . . . . . . . . . . .7.1 6.2. . . .

205 8. . . . . . . . . . . . . . . . . . . . . . . . 213 5 . . . . . . . . . .3 Liberty (. . . . . . 205 8. . . . 211 11. . . . . . . .Draft August 24. . . . . . . . . . . .1 Synopsys Synthesis: dc shell . . . . . . . . . . . . . 203 Verilog Synthesis 205 8. . . .4. . . . . .4 MIPS: Final Assembly . . . . . . . . . . . . . . . .1 Importing the Design to DFII . . . . . . . . . .4 Cadence to Synopsys (CSI) Interface . . . 213 12. 197 Cell Characterization 203 7. . . . . . . . . 203 7. . . . . . . . . . . 211 11. . . . . .3 MIPS: Simulation . . . . . . .1 Characterization with Spectre .2 Synopsys Module Compiler . . . . . . . . . . . .1 7 8 9 CONTENTS Parametric Simulation . . . . . . .2 MIPS: Place and Route . . . . . .2 Characterization with SignalStorm . . . . . . . . . . . . . . 207 9. . . 205 8. . . . . . . . . . . . . . . . . . . . . . . . . . 206 Abstract Generation 207 9. . . . . . . . . . . . . 213 12. . . . . . 211 12 Design Example: TinyMIPS 213 12. . . . . . . . . . . . . . . .3 Pad Frames in CCAR . . . . .2 LEF File Generation . . . . . .lib) file format . .2 Encounter Scripting . . . . . . . . .3 Cadence BuildGates . . . . 213 12.4 Final GDS Generation . . . . . . . . . . . . .1 Encounter GUI . . 203 7.1 Abstract Tool . . . . . . . . . .2 Pad Frames in Encounter . 207 10 SOC Encounter Place and Route 209 10. . . . . . . . . . . . . . . . 2006 6. . . . . . . . . 211 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 11 Chip Assembly 211 11. . . . . . . . . . . . . . . .1 MIPS: Synthesis . . . . . . . . . . . . 209 10. . . . . . . . . . .

. . . . . . . . . .5. . . . . 218 B. . . . . . . . . . . . . . . . . . . . . 215 B Highlights of the Tools 217 B. .4. . 215 A. . . . . 219 C. 218 B. . . . . . . 218 C Tool and Setup Scripts 219 C. . .1 Cadence Setup Scripts . 218 B. . . . . . . . . . . . . . . . . . . . . . . .5 Synopsys Tool Scripts . . .9 Synopsys Synthesis . . . . . . . . . . .2 Installing the NCSU CDK . . . . . . . . . . . . . . . . . . . . 219 C. . . . 219 C. 218 B. . . . . . . .1 dc shell Synthesis . . . . . . 219 C. . . . . . . . . .2 Synopsys Setup Scripts . . . .5 Virtuoso Layout . . . . .4. . 219 C. .3 Installing Synopsys Tools . . . .8 SOC Encounter . . . . . . . .2 BuildGates Synthesis . . . . . . . . . .3 PrimeTime Timing Analysis . . . . . . . 218 B. . . . . . . . . . . . . . 2006 A Tool Administration 215 A. . . . . . . . . . . . . . . . 218 B. . . . . . . . . . . . . . .1 Installing Cadence Tools . . . . . . . . .1 SOC Encounter . . 218 B. . . . . . . . .5.CONTENTS Draft August 24. . .10 ICC Chip Assembly Router . . . . . . . . . . . . . . . . . . . . 218 B. . . . . . . . . . .6 Abstract Generation . . . . . . . . . . . . . . . . . . .3 TCL script basics . . . . 219 C.4 Cadence Tool Scripts . . . . . . . . . . . . . . . 219 C. .4 Spectre Analog Simulation . . . . . . . . . . . . .2 Module Compiler Synthesis . . . . . . . .5. . 219 C. . . . . . . . . . 218 B. . . . . . . . . . . . . . .7 SignalStorm Library Characterization . . . . . . 219 D MOSIS SCMOS rev8 Design Rules 6 221 . . . . . . . . . . . . . . . . . 219 C. . . . . . .3 Verilog Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 A. . . . . . . . . . . . . . . . . . . . . .1 ICFB . . . . . . . . . . . . . . . . . . . . . . . . . .2 Composer Schematics . .

. . . . .1 NCSU CDK . . . . . . . . . . . . .2. . . 223 E. . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 UofU Digital . . . . . . . . 223 E. . .Draft August 24. . . . . . . . . . . . . . . . . . 223 E. .1. . .2 UofU Async . .2.3 OSU Libraries . . . . . . . . . . .1 UofU Extensions . . . . . 223 E. . . . . . . 223 E. . .2. . . . . . . . . . . 223 Bibliography 224 Index 226 7 . . . . . .2 Standard Cell Libraries . . . . . 2006 E Technology and Cell Libraries CONTENTS 223 E. . . .

CONTENTS Draft August 24. 2006 8 .