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OM SATHI

ADHIPARASAKTHI COLLEGE OF ENGINEERING

6.1

Syllabus
DIGITAL LOGIC CIRCUITS 3 1 0 4

EE2255

1. BOOLEAN ALGEBRA AND COMBINATIONAL CIRCUITS 9 Boolean algebra: De-Morgans theorem, switching functions and simplification using Kmaps & Quine McClus e! method, Design of adder, subtractor, comparators, code con"erters, encoders, decoders, multiple#ers and demultiple#ers$ 2. S NC!RONOUS SE"UENTIAL CIRCUITS 9 %lip flops - &', D, (K and )$ *nal!sis of s!nchronous se+uential circuits, design of s!nchronous se+uential circuits - Counters, state diagram, state reduction, state assignment$ 3. AS NC!RONOUS SE"UENCTIAL CIRCUIT 9 *nal!sis of as!nchronous se+uential machines, state assignment, as!nchronous design problem$ 4. #ROGRAMMABLE LOGIC DE$ICES% MEMOR AND LOGIC &AMILIES Memories: '.M, /'.M, 0/'.M, /1*, /1D, %/2*, digital logic families: ))1, 0C1, CM.&$ 5. $!DL 9 ')1 Design - combinational logic - )!pes - .perators - /ac ages - &e+uential circuit &ub programs - )est benches$ 30#amples: adders, counters, flipflops, %&M, Multiple#ers 4 Demltiple#ers5$ L ' 45 T ' 15 T()al ' 60 TE*T BOO+S 6$ 'a7 Kamal, 8 Digital s!stems-/rinciples and Design, /earson education 9nd edition, 9$ M$ Morris Mano, 8Digital Design, /earson 0ducation, 9::<$ =$ (ohn M$>arbrough, 8Digital 1ogic, *pplication & Design, )homson, 9::9$ 9::; 9

RE&ERENCES 6$ Charles ?$'oth, 8%undamentals 1ogic Design, (aico /ublishing, @A edition, 9::9$ 9$ %lo!d and (ain, 8Digital %undamentals, Bth edition, /earson 0ducation, 9::=$ =$(ohn %$Ca erl!, 8Digital Design /rinciples and /ractice, =rd edition, /earson

EE2255 DIGITAL LOGIC CIRCUITS

OM SAKTHI

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

0ducation, 9::9$ D$ )occi, EDigital &!stems : /rinciples and aopplications, Bth 0ditionF /earson 0ducation$

6.2

#a,) A "u-s).(/s 0.)1 A/s0-,s 2 #a,) B "u-s).(/s


UNIT3I BOOLEAN ALGEBRA AND COMBINATIONAL CIRCUITS T4O MAR+S

15 41a) a,- bas.6 7,(7-,).-s (8 B((l-a/ al9-b,a: )he basic properties of Boolean algebra are commutati"e propert!, associati"e /ropert! and distributi"e propert!$ 25 S)a)- )1- ass(6.a).;- 7,(7-,)y (8 b((l-a/ al9-b,a. )he associati"e propert! of Boolean algebra states that the .' ing of se"eral "ariables results in the same regardless of the grouping of the "ariables$ )he associati"e propert! is stated as follows: *G 3BGC5 H 3*GB5 GC 35 S)a)- )1- 6(<<u)a).;- 7,(7-,)y (8 B((l-a/ al9-b,a$ )he commutati"e propert! states that the order in which the "ariables are .' ed ma es no difference$ )he commutati"e propert! is: *GBHBG* 45 S)a)- )1- =.s),.bu).;- 7,(7-,)y (8 B((l-a/ al9-b,a. )he distributi"e propert! states that *ID ing se"eral "ariables and .' ing the result Cith a single "ariable is e+ui"alent to .' ing the single "ariable with each of the the se"eral Aariables and then *ID ing the sums$ )he distributi"e propert! is: *GBCH 3*GB5 3*GC5 55 S)a)- )1- abs(,7).(/ la0 (8 B((l-a/ al9-b,a$ )he absorption law of Boolean algebra is gi"en b! JGJ>HJ, J3JG>5 HJ$ 65 S)a)- D- M(,9a/>s )1-(,-<$ De Morgan suggested two theorems that form important part of Boolean algebra$ )he! are, 65 )he complement of a product is e+ual to the sum of the complements$ 3*B5K H *K G BK 95 )he complement of a sum term is e+ual to the product of the complements$ 3* G B5K H *KBK

2nd YEAR/ 4th SEMESTER

OM SATHI

ADHIPARASAKTHI COLLEGE OF ENGINEERING

?5 R-=u6- A @A A B5 * 3* G B5 H ** G *B H * 36 G B5 L6 G B H 6M H *$ B5 R-=u6- A>B>C> A A>BC> A A>BC *KBKCK G *KBCK G *KBC H *KCK3BK G B5 G *KBKC H *KCK G *KBC L* G *K H 6M H *K3CK G BC5 H *K3CK G B5 L* G *KB H * G BM 95 R-=u6- AB A @AC5> A ABCC @AB A C5 *B G 3*C5K G *BC 3*B G C5 H *B G 3*C5K G **BKBC G *BKCC H *B G 3*C5K G *BKCC L*$*K H :M H *B G 3*C5K G *BKC L*$* H 6M H *B G *K G CK H*BKC L3*B5K H *K G BKM H *K G B G CK G *BKC L* G *BK H * G BM H *K G BKC G B G CK L* G *KB H * G BM H *K G B G CK G BKC H*K G B G CK G BK H*K G CK G 6 H 6 L* G 6 H6M 105 S.<7l.8y )1- 8(ll(0./9 -D7,-ss.(/ ' @A A B5 @A A CC5 @B> A CC5 > H 3* G B5 3* G C5 3BK G C5 H 3**K G *C G*KB GBC5 3BK G CK5 L*$*K H :M H 3*C G *KB G BC5 3BK G C5 H *BKC G *CCK G *KBBK G *KBCK G BBKC G BCCK H *BKC G *KBCK 115 S1(0 )1a) @* A > A * 5 @* A >5 @*> 5 ' 0 3J G >K G J>53J G >K53JK>5 H 3J G >K G J5 3J G >5 3JK G >5 L* G *KB H * G BM H 3J G >5 3J G >5 3JK>5 L* G * H 6M H 3J G >5 3JK>5 L*$* H 6M H J$JK G >K$JK$> H : L*$*K H :M 125 #,(;- )1a) ABC A ABC> A AB>C A A>BC ' AB A AC A BC *BC G *BCK G *BKC G *KBCH*B3C G CK5 G *BKC G *KBC H*B G *BKC G *KBC H*3B G BKC5 G *KBC H*3B G C5 G *KBC H*B G *C G *KBC

EE2255 DIGITAL LOGIC CIRCUITS

OM SAKTHI

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

HB3* G C5 G *C H*B G BC G *C H*B G *C GBC $$$/ro"ed 135 C(/;-,) )1- 9.;-/ -D7,-ss.(/ ./ 6a/(/.6al SO# 8(,< ' AC A AB A BC > H *C G *B G BC H*C 3B G B5 G *B 3C G C5 G 3* G *K5 BC H*BC G *BCK G *BKC G *BKCK G *BC G *BCK G *BC H*BC G *BCK G*BKC G *BKCK L* G * H6M 145 D-8./- =ual.)y 7,(7-,)y$ Dualit! propert! states that e"er! algebraic e#pression deducible from the postulates .f Boolean algebra remains "alid if the operators and identit! elements are interchanged$ @f the dual of an algebraic e#pression is desired, we simpl! interchange .' and *ID operators and replace 6Ks b! :Ks and :Ks b! 6Ks$ 155 &./= )1- 6(<7l-<-/) (8 )1- 8u/6).(/s &1 ' D>yE> A D>y>E a/= &2 ' D @y>E> A yE5. By a77ly./9 D-3M(,9a/>s )1-(,-<. %6K H 3#K!NK G #K!KN5K H 3#K!NK5K3#K!KN5K H 3# G !K G N53# G ! GNK5 %9K H L# 3!KNK G !N5MK H #K G 3!KNK G !N5K H #K G 3!KNK5K3!N5K H #K G 3! G N5 3!K G NK5 165 S.<7l.8y )1- 8(ll(0./9 -D7,-ss.(/ ' @A A B5 @A ' C5 @B A C5 H 3* * G * C G * B G B C5 3B G C5 H 3* C G * B G B C5 3B G C5 H*BCG*CCG*BBG*BCGBBCGBCC H*BC 1?5 41a) a,- )1- <-)1(=s a=(7)-= )( ,-=u6- B((l-a/ 8u/6).(/: i5 Karnaug map ii5 )abular method or Quine Mc-Clus e! method iii5 Aariable entered map techni+ue$ 1B5 S)a)- )1- l.<.)a).(/s (8 Fa,/au91 <a7. i5 2enerall! it is limited to si# "ariable map 3i$e5 more then si# "ariable in"ol"ing e#pression are not reduced$ ii5 )he map method is restricted in its capabilit! since the! are useful for simplif!ing onl! Boolean e#pression represented in standard form$ 195 41a) .s a Fa,/au91 <a7:

2nd YEAR/ 4th SEMESTER

OM SATHI

ADHIPARASAKTHI COLLEGE OF ENGINEERING

* arnaugh map or map is a pictorial form of truth table, in which the map diagram is made up of s+uares, with each s+uares representing one minterm of the function$DD5 %ind the minterms of the logical e#pression > H *KBKCK G *KBKC G *KBC G *BCK > H *KBKCK G *KBKC G *KBC G *BCK Hm: G m6 Gm= Gm< HOm 3:, 6, =, <5 205 4,.)- )1- <aD)-,<s 6(,,-s7(/=./9 )( )1- l(9.6al -D7,-ss.(/ ' @A A B A CC5 @A A B> A C>5 @A> A B> A C5 H 3* G B G C5 3* G BK G CK5 3*K G BK G C5 HM6$M=$M< H M 36, =, <5 215 41a) a,- 6all-= =(/C) 6a,- 6(/=.).(/s: @n some logic circuits certain input conditions ne"er occur, therefore the Corresponding output ne"er appears$ @n such cases the output le"el is not defined, it can be either high or low$ )hese output le"els are indicated b! 8J or8d in the truth tables and are called dont care conditions or incompletel! specified functions$ 225 41a) .s a 7,.<- .<7l.6a/): * prime implicant is a product term obtained b! combining the ma#imum possible number of ad7acent s+uares in the map$ 235 41a) .s a/ -ss-/).al .<7l.6a/): @f a min term is co"ered b! onl! one prime implicant, the prime implicant is said to be essential 245 D-8./- 6(<b./a).(/al l(9.6 Chen logic gates are connected together to produce a specified output for certain specified combinations of input "ariables, with no storage in"ol"ed, the resulting circuit is called combinational logic$ 265 ED7la./ )1- =-s.9/ 7,(6-=u,- 8(, 6(<b./a).(/al 6.,6u.)s )he problem definition Determine the number of a"ailable input "ariables & re+uired .4/ "ariables$ *ssigning letter s!mbols to @4. "ariables .btain simplified Boolean e#pression for each .4/$ .btain the logic diagram$ 2?5 D-8./- 1al8 a==-, a/= 8ull a==-,

EE2255 DIGITAL LOGIC CIRCUITS

OM SAKTHI

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

)he logic circuit that performs the addition of two bits is a half adder$ )he circuit that /erforms the addition of three bits is a full adder$ 2B5 D-8./- D-6(=-,: * decoder is a multiple - input multiple output logic circuit that con"erts coded inputs into coded outputs where the input and output codes are different$ 295 41a) .s b./a,y =-6(=-,: * decoder is a combinational circuit that con"erts binar! information from n input lines to a ma#imum of 9n out puts lines$ 305 D-8./- E/6(=-,: *n encoder has 9n input lines and n output lines$ @n encoder the output lines generate the binar! code corresponding to the input "alue$ 315 41a) .s 7,.(,.)y E/6(=-,: * priorit! encoder is an encoder circuit that includes the priorit! function$ @n priorit! encoder, if 9 or more inputs are e+ual to 6 at the same time, the input ha"ing the highest priorit! will ta e precedence$

325 D-8./- <ul).7l-D-,: Multiple#er is a digital switch$ @f allows digital information from se"eral sources to be routed onto a single output line$ 335 41a) =( y(u <-a/ by 6(<7a,a)(,: * comparator is a special combinational circuit designed primaril! to compare the relati"e magnitude of two binar! numbers$ 345 4,.)- =(0/ )1- s)-7s ./ .<7l-<-/)./9 a B((l-a/ 8u/6).(/ 0.)1 l-;-ls (8 NAND Ga)-s: &implif! the function and e#press it in sum of products$ Draw a I*ID gate for each product term of the e#pression that has at least two 1iterals$ )he inputs to each I*ID gate are the literals of the term$ )his constitutes a group of first le"el gates$ Draw a single gate using the *ID-in"ert or the in"ert- .' graphic s!mbol in the second le"el, with inputs coming from outputs of first le"el gates$ * term with a single literal re+uires an in"erter in the first le"el$ ?ow e"er if the single literal is complemented, it can be connected directl! to an input of the second le"el I*ID gate$ 355 G.;- )1- 9-/-,al 7,(6-=u,- 8(, 6(/;-,)./9 a B((l-a/ -D7,-ss.(/ ./ )( <ul).l-;-l NAND =.a9,a<:

2nd YEAR/ 4th SEMESTER

OM SATHI

ADHIPARASAKTHI COLLEGE OF ENGINEERING

Draw the *ID-.' diagram of the Boolean e#pression$ Con"ert all *ID gates to I*ID gates with *ID-in"ert graphic s!mbols$ Con"ert all .' gates to I*ID gates with in"ert-.' graphic s!mbols$ Chec all the bubbles in the same diagram$ %or e"er! bubble that is not compensated b! another circle along the same line, insert an in"erter or complement the input literal$ #ART B 15 S.<7l.8y )1- b((l-a/ 8u/6).(/ us./9 )abula).(/ <-)1(=. & ' G @0% 1% 2% B% 10% 11% 14% 155 1ist all the min terms *rrange them as per the number of ones based on binar! e+ui"alent Compare one group with another for difference in one and replace the bit with dash$ Continue this until no further grouping possible$ )he unchec ed terms represent the prime implicants$ % H CKJK>K G JKPK G C> 25 D-)-,<./- )1- 7,.<- .<7l.6a/)s (8 )1- 8u/6).(/ & @4%*% %H5 ' G @1%4%6%?%B%9%10%11%155 1ist all the min terms *rrange them as per the number of ones based on binar! e+ui"alent Compare one group with another for difference in one and replace the bit with dash$ Continue this until no further grouping possible$ )he unchec ed terms represent the prime implicants$ % H JK>KP G CKJPK G CKJ> G J>P G C>P G CJK Minimum &et of prime implicants % H JK>KP G CKJPK G J>P G CJK 35 S.<7l.8y )1- B((l-a/ 8u/6).(/ us./9 +3<a7. &@A%B%C%D%E5 ' @0%2%4%6%9%13%21%23%25%29%315 %i"e "ariables hence two "ariable maps one for * H : and the other for * H 6$ % H *KBK0K G BDK0 G *C0 45 Ob)a./ )1- 6a/(/.6al su< (8 7,(=u6)s (8 )1- 8u/6).(/ > H *B 3C G CK5 3D G DK5 G *CD 3B G BK5 > H *BCD G *BCDK G *BCKD G *BCKDK G *BKCD 55 S)a)- )1- 7(s)ula)-s a/= )1-(,-<s (8 B((l-a/ al9-b,a. JG:HJJQ6HJ J G JK H 6 J Q JK H : JGJHJJQJHJ ' AB A ACD

EE2255 DIGITAL LOGIC CIRCUITS

OM SAKTHI

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

JG6H6JQ:H: 3JK5K H J J G > H > G J J> H >J J G 3> G P5 H 3J G >5 G P J 3>P5 H 3J>5 P J3> G P5 H J> G JP J G >J H 3J G >5 3J G P5 3J G >5K H JK>K 3J>5K H JK G >K J G J> H J J3J G >5 H J 65 D-s.9/ a 43b.) b./a,y a==-,Isub),a6)(, 6.,6u.)$ Basic e+uations Comparison of e+uations Design using twos complement Circuit diagram ?5 D-s.9/ a l(9.6 6.,6u.) )( 6(/;-,) )1- BCD 6(=- )( ED6-ss J 3 6(=-s. )ruth )able for BCD to 0#cess - = con"ersions$ K-map simplification 1ogic circuit implementing the Boolean 0#pression B5 D-s.9/ a/= -D7la./ a 6(<7a,a)(, )( 6(<7a,- )0( .=-/).6al 0(,=s. )wo numbers represented b! * H *=*9*6*: & B H B=B9B6B: @f two numbers e+ual / H *i Bi .btain the logic 0#pression$ .btain the logic diagram$ 95 S)a)- 2 7,(;- )1- la0s ./ B((l-a/ al9-b,a. 105 S.<7l.8y )1- )1,-- ;a,.abl- -D7,-ss.(/ us./9 B((l-a/ al9-b,a'KM @3% 5% ?5 115 S.<7l.8y )1- 8(ll(0./9 B((l-a/ -D7,-ss.(/s us./9 +a,/au91 <a7$ 3i5>H*CGBCG*BCG*B 3@@5>H 3/GQG'5 3/GQG'5 3/GQG'5 125 S.<7l.8y )1- 8(ll(0./9 8u/6).(/s: 3i5%3*,B,C,D5HR3:,6,=,B,S,6=,6T5 3@@5 %3C,J,>,P5HR3:,=,D,;,S,69,6D5 135 Us- a +3<a7 )-61/.Lu- )( ,-=u6- )1- 9.;-/ -D7,-ss.(/ )( <./.<u< SO# 8(,<. 3i5>H*BCDG*BCDG*BCDG*BCD 145 I<7l-<-/) )1- B((l-a/ 8u/6).(/ 0.)1 a <uDM %3*,B,C,D5 H Rm3:,6,=,D,B,S,6T5 155 D-s.9/ a 43b.) 7,.(,.)y -/6(=-, 0.)1 ./7u) D0 1a;./9 l(0-s) 7,.(,.)y 2 D3 1a;./9 1.91-s) 7,.(,.)y$

2nd YEAR/ 4th SEMESTER

OM SATHI

ADHIPARASAKTHI COLLEGE OF ENGINEERING

165 I<7l-<-/) )1- B((l-a/ 8u/6).(/ 0.)1 BM1 <uD % 3*, B, C, D5 H *BDG*CDGBCDG*CD 1?5R-al.E- &@4C*C CH5 ' N@1%4%6%?%B%9%10%11%155. UNIT3II S NC!RONOUS SE"UENTIAL CIRCUITS T4O MAR+S 1. 41a) a,- )1- 6lass.8.6a).(/s (8 s-Lu-/).al 6.,6u.)s: )he se+uential circuits are classified on the basis of timing of their signals into two t!pes$ )he! are, 65 &!nchronous se+uential circuit$ 95 *s!nchronous se+uential circuit$ 2. D-8./- &l.7 8l(7. )he basic unit for storage is flip flop$ * flip-flop maintains its output state either at 6 or : until directed b! an input signal to change its state$ 3. 41a) a,- )1- =.88-,-/) )y7-s (8 8l.738l(7: )here are "arious t!pes of flip flops$ &ome of them are mentioned below the! are, '& flip-flop &' flip-flop D flip-flop (K flip-flop ) flip-flop 4. 41a) .s )1- (7-,a).(/ (8 RS 8l.738l(7: Chen ' input is low and & input is high the Q output of flip-flop is set$ Chen ' input is high and & input is low the Q output of flip-flop is reset$ Chen both the inputs ' and & are low the output does not change Chen both the inputs ' and & are high the output is unpredictable$ 5. 41a) .s )1- (7-,a).(/ (8 SR 8l.738l(7: UChen ' input is low and & input is high the Q output of flip-flop is set$ UChen ' input is high and & input is low the Q output of flip-flop is reset$ UChen both the inputs ' and & are low the output does not change$ UChen both the inputs ' and & are high the output is unpredictable$ 6. 41a) .s )1- (7-,a).(/ (8 D 8l.738l(7:

EE2255 DIGITAL LOGIC CIRCUITS

OM SAKTHI

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

@n D flip-flop during the occurrence of cloc pulse if DH6, the output Q is set and if DH:, the output is reset$ ?. 41a) .s )1- (7-,a).(/ (8 O+ 8l.738l(7: UChen K input is low and ( input is high the Q output of flip-flop is set$ UChen K input is high and ( input is low the Q output of flip-flop is reset$ UChen both the inputs K and ( are low the output does not change UChen both the inputs K and ( are high it is possible to set or reset the %lip-flop 3ie5 the output toggle on the ne#t positi"e cloc edge$ B. 41a) .s )1- (7-,a).(/ (8 T 8l.738l(7: ) flip-flop is also nown as )oggle flip-flop$ UChen )H: there is no change in the output$ UChen )H6 the output switch to the complement state 3ie5 the output toggles$ 9. D-8./- ,a6- a,(u/= 6(/=.).(/. @n (K flip-flop output is fed bac to the input$ )herefore change in the output results change in the input$ Due to this in the positi"e half of the cloc pulse if both ( and K are high then output toggles continuousl!$ )his condition is called race around condition$ 10. 41a) .s -=9-3),.99-,-= 8l.738l(7: )he problem of race around condition can sol"ed b! edge triggering flip flop$ )he term edge triggering means that the flip-flop changes state either at the positi"e edge or negati"e edge of the cloc pulse and it is sensiti"e to its inputs onl! at this transition of the cloc $ 11. 41a) .s a <as)-,3sla;- 8l.738l(7: * master-sla"e flip-flop consists of two flip-flops where one circuit ser"es as a master and the other as a sla"e$ 12. ED7la./ )1- 8l.738l(7 -D6.)a).(/ )abl-s 8(, RS &&. @n '& flip-flop there are four possible transitions from the present state to the ne#t state$ )he! are, O :O: transition: )his can happen either when 'H&H: or when 'H6 and &H:$ O :O6 transition: )his can happen onl! when &H6 and 'H:$ O 6O: transition: )his can happen onl! when &H: and 'H6$ O 6O6 transition: )his can happen either when &H6 and 'H: or &H: and 'H:$

13. ED7la./ )1- 8l.738l(7 -D6.)a).(/ )abl-s 8(, O+ 8l.738l(7 @n (K flip-flop also there are four possible transitions from present state to ne#t state$)he! are,

2nd YEAR/ 4th SEMESTER

OM SATHI

ADHIPARASAKTHI COLLEGE OF ENGINEERING

O :O: transition: )his can happen when (H: and KH6 or KH:$ O :O6 transition: )his can happen either when (H6 and KH: or when (HKH6$ O 6O: transition: )his can happen either when (H: and KH6 or when (HKH6$ O 6O6 transition: )his can happen when KH: and (H: or (H6$ 14. ED7la./ )1- 8l.738l(7 -D6.)a).(/ )abl-s 8(, D 8l.738l(7 @n D flip-flop the ne#t state is alwa!s e+ual to the D input and it is independent of the present state$ )herefore D must be : if QnG6 has to :, and if QnG6 has to be 6 regardless the "alue of Qn$ 15. ED7la./ )1- 8l.738l(7 -D6.)a).(/ )abl-s 8(, T 8l.738l(7 Chen input )H6 the state of the flip-flop is complemented, when )H:, the state of the %lip-flop remains unchanged$ )herefore, for :O: and 6O6 transitions ) must be : and for :O6 and 6O: transitions must be 6$ 16. D-8./- s-Lu-/).al 6.,6u.): @n se+uential circuits the output "ariables dependent not onl! on the present input "ariables but the! also depend up on the past histor! of these input "ariables$ 1?. G.;- )1- 6(<7a,.s(/ b-)0--/ 6(<b./a).(/al 6.,6u.)s a/= s-Lu-/).al 6.,6u.)s. Combinational circuits &e+uential circuits Memor! unit is not re+uired Memor! unit! is re+uired /arallel adder is a combinational circuit &erial adder is a se+uential circuit 1B. 41a) =( y(u <-a/ by 7,-s-/) s)a)-: )he information stored in the memor! elements at an! gi"en time define$s the present state of the se+uential circuit$ 19. 41a) =( y(u <-a/ by /-D) s)a)-: )he present state and the e#ternal inputs determine the outputs and the ne#t state of the se+uential circuit$ 20. S)a)- )1- )y7-s (8 s-Lu-/).al 6.,6u.)s: 6$ &!nchronous se+uential circuits 9$ *s!nchronous se+uential circuits

21. D-8./- sy/61,(/(us s-Lu-/).al 6.,6u.) @n s!nchronous se+uential circuits, signals can affect the memor! elements onl! at discrete instant of time$

EE2255 DIGITAL LOGIC CIRCUITS

OM SAKTHI

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

22. D-8./- Asy/61,(/(us s-Lu-/).al 6.,6u.): @n as!nchronous se+uential circuits change in input signals can affect memor! element at an! instant of time$ 23. G.;- )1- 6(<7a,.s(/ b-)0--/ sy/61,(/(us 2 Asy/61,(/(us s-Lu-/).al 6.,6u.)s: &!nchronous se+uential circuits *s!nchronous se+uential circuits$ Memor! elements are loc ed flip-flops Memor! elements are either unloc ed flip - flops or time dela! elements$ 24. 41a) .s ,a6- a,(u/= 6(/=.).(/: @n the (K latch, the output is feedbac to the input, and therefore changes in the output results change in the input$ Due to this in the positi"e half of the cloc pulse if ( and K are both high then output toggles continuousl!$ )his condition is nown as race around condition 25. G.;- )1- 6(<7a,.s(/ b-)0--/ sy/61,(/(us 2 Asy/61,(/(us 6(u/)-,s. *s!nchronous counters @n this t!pe of counter flip-flops are Connected in such a wa! that output of 6st %lip-flop dri"es the cloc for the ne#t flipflop *ll the flip-flops are not cloc ed &imultaneousl! &!nchronous counters @n this t!pe there is no connection between output of first flip-flop and cloc input of the ne#t flip - flop *ll the flip-flops are cloc ed simultaneousl!

#ART B 15 ED7la./ )1- 0(,F./9 (8 BCD R.77l- C(u/)-, 0.)1 )1- 1-l7 (8 s)a)- =.a9,a< a/= l(9.6 D.a9,a<. BCD 'ipple Counter Count se+uence )ruth )able &tate diagram representing the )ruth )able )ruth )able for the (-K %lip %lop 1ogic Diagram 25D-s.9/ a s-Lu-/).al =-)-6)(, 01.61 7,(=u6-s a/ (u)7u) 1 -;-,y ).<- )1- ./7u) s-Lu-/61011 .s =-)-6)-=. Construct state diagram .btain the flow table .btain the flow table & output table )ransition table &elect flip flop 0#citation table

2nd YEAR/ 4th SEMESTER

OM SATHI

ADHIPARASAKTHI COLLEGE OF ENGINEERING

1ogic diagram 35 ED7la./ ./ =-)a.l ab(u) s-,.al ./ s-,.al (u) s1.8) ,-9.s)-,$ Bloc diagram )heoretical e#planation 1ogic diagram Cor ing UNIT3III AS NC!RONOUS SE"UENTIAL CIRCUITS T4O MAR+S 1. 41a) a,- s-6(/=a,y ;a,.abl-s: -present state "ariables in as!nchronous se+uential circuits 2. 41a) a,- -D6.)a).(/ ;a,.abl-s: -ne#t state "ariables in as!nchronous se+uential circuits 3. 41a) .s 8u/=a<-/)al <(=- s-Lu-/).al 6.,6u.): -input "ariables changes if the circuit is stable -inputs are le"els, not pulses -onl! one input can change at a gi"en time 4. 41a) .s 7uls- <(=- 6.,6u.): -inputs are pulses -widths of pulses are long for circuit to respond to the input -pulse width must not be so long that it is still present after the new state is reached 5. 41a) a,- )1- s.9/.8.6a/6- (8 s)a)- ass.9/<-/): @n s!nchronous circuits-state assignments are made with the ob7ecti"e of circuit reduction *s!nchronous circuits-its ob7ecti"e is to a"oid critical races 6. 41-/ =(-s ,a6- 6(/=.).(/ (66u,: -)wo or more binar! state "ariables change their "alue in response to the change in i4p Aariable ?. 41a) .s /(/ 6,.).6al ,a6-:

EE2255 DIGITAL LOGIC CIRCUITS

OM SAKTHI

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

%inal stable state does not depend on the order in which the state "ariable changes race condition is not harmful B. 41a) .s 6,.).6al ,a6-: -final stable state depends on the order in which the state "ariable changes -race condition is harmful 9. 41-/ =(-s a 6y6l- (66u,: -as!nchronous circuit ma es a transition through a series of unstable state 10. 41a) a,- )1- =.88-,-/) )-61/.Lu-s us-= ./ s)a)- ass.9/<-/): -shared row state assignment -.ne hot state assignment 11. 41a) a,- )1- s)-7s 8(, )1- =-s.9/ (8 asy/61,(/(us s-Lu-/).al 6.,6u.): -construction of primiti"e flow table -reduction of flow table -state assignment is made -realiNation of primiti"e flow table 12. 41a) .s 1aEa,=: -unwanted switching transients 13. 41a) .s s)a).6 1 1aEa,=: -output goes momentaril! : when it should remain at 6 14. 41a) a,- s)a).6 0 1aEa,=s: -output goes momentaril! 6 when it should remain at : 15. 41a) .s =y/a<.6 1aEa,=: -output changes = or more times when it changes from 6 to : or : to 6 16. 41a) .s )1- 6aus- 8(, -ss-/).al 1aEa,=s: -une+ual dela!s along 9 or more path from same input 1?. 41a) .s 8l(0 )abl-: -state table of an s!nchronous se+uential networ 1B. 41a) .s SM 61a,): -describes the beha"ior of a state machine -used in hardware design of digital s!stems 19. 41a) a,- )1- a=;a/)a9-s (8 SM 61a,): -eas! to understand the operation

2nd YEAR/ 4th SEMESTER

OM SATHI

ADHIPARASAKTHI COLLEGE OF ENGINEERING

-east to con"ert to se"eral e+ui"alent forms 20. 41a) .s 7,.<.).;- 8l(0 61a,): -one stable state per row 21. 41a) .s s)a)- -Lu.;al-/6- )1-(,-<: )wo states &* and &B, are e+ui"alent if and onl! if for e"er! possible input J se+uence, the outputs are the same and the ne#t states are e+ui"alent i$e$, if &* 3t G 65 H &B 3t G 65 and P* H PB then &* H &B$ 22. 41a) =( y(u <-a/ by =.s)./9u.s1./9 s-Lu-/6-s: )wo states, &* and &B of se+uential machine are distinguishable if and onl! if their e#ists at least one finite input se+uence$ Chich, when applied to se+uential machine causes different output se+uences depending on whether &* or &B is the initial state$ 23. #,(;- )1a) )1- -Lu.;al-/6- 7a,).).(/ .s u/.LuConsider that there are two e+ui"alence partitions e#ist: /* and /B, and /*5 /B$ )his states that, there e#ist 9 states &i & &7 which are in the same bloc of one partition and not in the same bloc of the other$ @f &i & &7 are in different bloc s of sa! /B, there e#ists at least on input se+uence which distinguishes &i & &7 and therefore, the! cannot be in the same bloc of /*$ 24. D-8./- 6(<7a).b.l.)y. &tates &i and &7 said to be compatible states, if and onl! if for e"er! input se+uencethat affects the two states, the same output se+uence, occurs whene"er both outputs arespecified and regardless of whether &i on &7 is the initial state$ 25. D-8./- <-,9-, 9,a71. )he merger graph is defined as follows$ @t contains the same number of "ertices as the state table contains states$ * line drawn between the two state "ertices indicates each compatible state pair$ @t two states are incompatible no connecting line is drawn$ 26. D-8./- ./6(<7a).b.l.)y )he states are said to be incompatible if no line is drawn in between them$ @f implied states are incompatible, the! are crossed & the corresponding line is ignored $ 2?. ED7la./ )1- 7,(6-=u,- 8(, s)a)- <./.<.Ea).(/$ 6$ /artition the states into subsets such that all states in the same subsets are 6 -e+ui"alent$ 9$ /artition the states into subsets such that all states in the same subsets are 9 e+ui"alent$

EE2255 DIGITAL LOGIC CIRCUITS

OM SAKTHI

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

=$ /artition the states into subsets such that all states in the same subsets are = e+ui"alent$ 2B. D-8./- 6l(s-= 6(;-,./9. * &et of compatibles is said to be closed if, for e"er! compatible contained in the set, all its implied compatibles are also contained in the set$ * closed set of compatibles, which contains all the states of M, is called a closed co"ering$ 29. D-8./- <a61./- -Lu.;al-/6-. )wo machines, M6 and M9 are said to be e+ui"alent if and onl! if, for e"er! state in M6, there is a corresponding e+ui"alent state in M9 & "ice "ersa$ 30. D-8./- s)a)- )abl-$ %or the design of se+uential counters we ha"e to relate present states and ne#t states$ )he table, which represents the relationship between present states and ne#t states, is called state table$ 31. D-8./- )()al s)a)-. )he combination of le"el signals that appear at the inputs and the outputs of the dela!s define what is called the total state of the circuit$ 32. 41a) a,- )1- s)-7s 8(, )1- =-s.9/ (8 asy/61,(/(us s-Lu-/).al 6.,6u.): 6$ Construction of a primiti"e flow table from the problem statement$ 9$ /rimiti"e flow table is reduced b! eliminating redundant states using the state 'eduction =$ &tate assignment is made D$ )he primiti"e flow table is realiNed using appropriate logic elements$ 33. D-8./- 7,.<.).;- 8l(0 )abl-$ @t is defined as a flow table which has e#actl! one stable state for each row in the table$ )he design process begins with the construction of primiti"e flow table$ 34. 41a) a,- )1- )y7-s (8 asy/61,(/(us 6.,6u.)s: 6$ %undamental mode circuits 9$ /ulse mode circuits 35. G.;- )1- 6(<7a,.s(/ b-)0--/ s)a)- Ass.9/<-/) Sy/61,(/(us 6.,6u.) a/= s)a)ass.9/<-/) asy/61,(/(us 6.,6u.)$ @n s!nchronous circuit, the state assignments are made with the ob7ecti"e of circuit reduction$ @n as!nchronous circuits, the ob7ecti"e of state assignment is to a"oid critical races$

2nd YEAR/ 4th SEMESTER

OM SATHI

ADHIPARASAKTHI COLLEGE OF ENGINEERING

36. 41a) a,- ,a6-s: Chen 9 or more binar! state "ariables change their "alue in response to a change in an input "ariable, race condition occurs in an as!nchronous se+uential circuit$ @n case of une+ual dela!s, a race condition ma! cause the state "ariables to change in an unpredictable manner$ 3?. D-8./- /(/ 6,.).6al ,a6-. @f the final stable state that the circuit reaches does not depend on the order in which the state "ariable changes, the race condition is not harmful and it is called a non critical race$ 3B. D-8./- 6,.).6al ,a6-: @f the final stable state depends on the order in which the state "ariable changes, the race condition is harmful and it is called a critical race$ 39. 41a) .s a 6y6l-: * c!cle occurs when an as!nchronous circuit ma es a transition through a series of unstable states$ @f a c!cle does not contain a stable state, the circuit will go from one unstable to stable to another, until the inputs are changed$ 40. L.s) )1- =.88-,-/) )-61/.Lu-s us-= 8(, s)a)- ass.9/<-/)$ 6$ &hared row state assignment 9$ .ne hot state assignment$ 41. 4,.)- a s1(,) /()- (/ 8u/=a<-/)al <(=- asy/61,(/(us 6.,6u.). %undamental mode circuit assumes that$ )he input "ariables change onl! when the circuit is stable$ .nl! one input "ariable can change at a gi"en time and inputs are le"els and not pulses$ 42. 4,.)- a s1(,) /()- (/ 7uls- <(=- 6.,6u.)$ /ulse mode circuit assumes that the input "ariables are pulses instead of le"el$ )he width of the pulses is long enough for the circuit to respond to the input and the pulse width must not be so long that it is still present after the new state is reached$ 43. 4,.)- s1(,) /()- (/ s1a,-= ,(0 s)a)- ass.9/<-/)$ 'aces can be a"oided b! ma ing a proper binar! assignment to the state "ariables$ ?ere, the state "ariables are assigned with binar! numbers in such a wa! that onl! one state "ariable can change at an! one state "ariable can change at an! one time when a state transition occurs$ )o accomplish this, it is necessar! that states between which transitions occur be gi"en ad7acent assignments$ )wo binar! are said to be ad7acent if the! differ in onl! one "ariable$ 44. 4,.)- s1(,) /()- (/ (/- 1() s)a)- ass.9/<-/)$

EE2255 DIGITAL LOGIC CIRCUITS

OM SAKTHI

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

)he one hot state assignment is another method for finding a race free stateassignment$ @n this method, onl! one "ariable is acti"e or hot for each row in the original flow table, ie, it re+uires one state "ariable for each row of the flow table$ *dditional row are introduced to pro"ide single "ariable changes between internal state transitions$

#ART B 15 ED7la./ 0.)1 /-a) =.a9,a< )1- =.88-,-/) 1aEa,=s a/= )1- 0ay )( -l.<./a)- )1-<. Classification of haNards &tatic haNard & D!namic haNard definitions K map for selected functions Method of elimination 0ssential haNards 25 S)a)- 0.)1 a /-a) -Da<7l- )1- <-)1(= 8(, )1- <./.<.Ea).(/ (8 7,.<.).;- 8l(0 )abl-. Consider a state diagram .btain the flow table Vsing implication table reduce the flow table Vsing merger graph obtain ma#imal compatibles Aerif! closed & co"ered conditions /lot the reduced flow table 35 D-s.9/ a asy/61,(/(us s-Lu-/).al 6.,6u.) 0.)1 2 ./7u)s T a/= C. T1- (u)7u) a))a./s a ;alu- (8 1 01-/ T ' 1 2 6 <(;-s 8,(< 1 )( 0. O)1-,0.s- )1- (u)7u) .s 0. .btain the state diagram .btain the flow table Vsing implication table reduce the flow table Vsing merger graph obtain ma#imal compatibles Aerif! closed & co"ered conditions /lot the reduced flow table .btain transition table 0#citation table 1ogic diagram 45 ED7la./ ./ =-)a.l ab(u) Ra6-s. Basics of races /roblem created due to races Classification of races 'emed! for races C!cles

2nd YEAR/ 4th SEMESTER

OM SATHI

ADHIPARASAKTHI COLLEGE OF ENGINEERING

55 ED7la./ )1- =.88-,-/) <-)1(=s (8 s)a)- ass.9/<-/) )hree row state assignment &hared row state assignment %our row flow table Multiple row state assignment /re"ention of races$

UNIT3I$ #ROGRAMMABLE LOGIC DE$ICES% MEMOR AND LOGIC &AMILIES T4O MAR+S 1. ED7la./ ROM * read onl! memor! 3'.M5 is a de"ice that includes both the decoder and the .' gates within a single @C pac age$ @t consists of n input lines and m output lines$ 0ach bit Combination of the input "ariables is called an address$ 0ach bit combination that comes out of the output lines is called a word$ )he number of distinct addresses possible with n input "ariables is 9n$ 2. 41a) a,- )1- )y7-s (8 ROM: 6$ /'.M 9$ 0/'.M =$ 00/'.M 3. ED7la./ #ROM. /'.M 3/rogrammable 'ead .nl! Memor!5 it allows user to store data or program$ /'.Ms use the fuses with materialli e nichrome and pol!cr!stalline$ )he user can blow these fuses b! passingaround 9: to T: m* of current for the period T to 9:Ws$)he blowing of fuses is called programming of '.M$ )he /'.Ms are one time programmable$ .nce programmed, the information is stored permanent$ 4. ED7la./ E#ROM. 0/'.M 30rasable /rogrammable 'ead .nl! Memor!5 0/'.M use M.& circuitr!$ )he! store 6s and :s as a pac et of charge in a buried la!er of the @C chip$ Ce can erase the stored data in the 0/'.Ms b! e#posing the chip to ultra"iolet light "ia its +uartN window for 6T to 9: minutes$ @t is not possible to erase selecti"e information$ )he chip can be reprogrammed$ 5. ED7la./ EE#ROM$

EE2255 DIGITAL LOGIC CIRCUITS

OM SAKTHI

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

00/'.M 30lectricall! 0rasable /rogrammable 'ead .nl! Memor!5$ 00/'.M also use M.& circuitr!$ Data is stored as charge or no charge on an insulated la!er or an insulated floating gate in the de"ice$ 00/'.M allows selecti"e erasing at the register le"el rather than erasing all the information since the information can be changed b! using electrical signals$ <. D-8./- a==,-ss a/= 0(,=M @n a '.M, each bit combination of the input "ariable is called on address$ 0ach bit combination that comes out of the output lines is called a word$ ?. 41a) a,- )1- )y7-s (8 ROM.: 6$ Mas ed '.M$ 9$ /rogrammable 'ead onl! Memor! =$ 0rasable /rogrammable 'ead onl! memor!$ D$ 0lectricall! 0rasable /rogrammable 'ead onl! Memor!$ B. 41a) .s 7,(9,a<<abl- l(9.6 a,,ay: !(0 .) =.88-,s 8,(< ROM: @n some cases the number of dont care conditions is e#cessi"e, it is more economical to use a second t!pe of 1&@ component called a /1*$ * /1* is similar to a '.M in concept, howe"er it does not pro"ide full decoding of the "ariables and does not generates all the minterms as in the '.M$ 9. 41a) .s <asF 3 7,(9,a<<abl-: Cith a mas programmable /1*, the user must submit a /1* program table to the manufacturer$ 10. 41a) .s 8.-l= 7,(9,a<<abl- l(9.6 a,,ay: )he second t!pe of /1* is called a field programmable logic arra!$ )he user b! means of certain recommended procedures can program the 0/1*$ 11. L.s) )1- <aP(, =.88-,-/6-s b-)0--/ #LA a/= #AL /1*: Both *ID and .' arra!s are programmable and Comple# Costlier than /*1 /*1 *ID arra!s are programmable .' arra!s are fi#ed Cheaper and &impler 12. D-8./- #LD. /rogrammable 1ogic De"ices consist of a large arra! of *ID gates and .' gates that Can be programmed to achie"e specific logic functions$ 13. G.;- )1- 6lass.8.6a).(/ (8 #LDs.

2nd YEAR/ 4th SEMESTER

OM SATHI

ADHIPARASAKTHI COLLEGE OF ENGINEERING

/1Ds are classified as /'.M 3/rogrammable 'ead .nl! Memor!5, /rogrammable 1ogic *rra! 3/1*5, /rogrammable *rra! 1ogic 3/*15, and 2eneric *rra! 1ogic 32*15 14. D-8./- #ROM. /'.M is /rogrammable 'ead .nl! Memor!$ @t consists of a set of fi#ed *ID gates Connected to a decoder and a programmable .' arra!$ 15. D-8./- #LA. /1* is /rogrammable 1ogic *rra! 3/1*5$ )he /1* is a /1D that consists of a /rogrammable *ID arra! and a programmable .' arra!$ 16. D-8./- #AL. /*1 is /rogrammable *rra! 1ogic$ /*1 consists of a programmable *ID arra! and a fi#ed .' arra! with output logic$ 1?. 41y 0as #AL =-;-l(7-=: @t is a /1D that was de"eloped to o"ercome certain disad"antages of /1*, such as longer dela!s due to additional fusible lin s that result from using two programmable arra!s and more circuit comple#it!$ 1B. D-8./- GAL. 2*1 is 2eneric *rra! 1ogic$ 2*1 consists of a programmable *ID arra! and a fi#ed .' arra! with output logic$ 19. 41y )1- ./7u) ;a,.abl-s )( a #AL a,- bu88-,-= )he input "ariables to a /*1 are buffered to pre"ent loading b! the large number of *ID gate inputs to which a"ailable or its complement can be connected$ 20. 41a) =(-s #AL 10LB s7-6.8y: /*1 - /rogrammable 1ogic *rra! 6: - )en inputs 1 - *cti"e 1.C .uput B - 0ight .utputs 21. 41a) .s C#LD: C/1Ds are Comple# /rogrammable 1ogic De"ices$ )he! are larger "ersions of /1Ds with a centraliNed internal interconnect matri# used to connect the de"ice macro cells together$ 22. D-8./- b.)% by)- a/= 0(,=. )he smallest unit of binar! data is bit$ Data are handled in a B bit unit called b!te$ * complete unit of information is called a word which consists of one or more b!tes$

EE2255 DIGITAL LOGIC CIRCUITS

OM SAKTHI

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

23. !(0 <a/y 0(,=s 6a/ a 16DB <-<(,y 6a/ s)(,-: * 6<#B memor! can store 6<,=BD words of eight bits each 24. D-8./- a==,-ss (8 a <-<(,y. )he location of a unit of data in a memor! is called address$ 25. 41a) .s R-a= a/= 4,.)- (7-,a).(/: )he Crite operation stores data into a specified address into the memor! and the 'ead operation ta es data out of a specified address in the memor!$ 26. 41y RAMs a,- 6all-= as $(la).l-: '*Ms are called as Aolatile memories because '*Ms lose stored data when the power is turned .%%$ 2?. D-8./- ROM$ '.M is a t!pe of memor! in which data are stored permanentl! or semi permanentl!$ Data can be read from a '.M, but there is no write operation$ 2B. D-8./- RAM. '*M is 'andom *ccess Memor!$ @t is a random access read4write memor!$ )he data can be read or written into from an! selected address in an! se+uence$ 29. D-8./- S)a).6 RAM a/= =y/a<.6 RAM. &tatic '*M use flip flops as storage elements and therefore store data indefinitel! as long as dc power is applied$ D!namic '*Ms use capacitors as storage elements and cannot retain data "er! long without capacitors being recharged b! a process called refreshing$ 30. L.s) )1- )0( )y7-s (8 SRAM. *s!nchronous &'*Ms and &!nhronous Burst &'*Ms 31. L.s) )1- bas.6 )y7-s (8 DRAMs. %ast /age Mode D'*M,0#tended Data .ut D'*M30D. D'*M5,Burst 0D. D'*M and &!nchronous D'*M$ 32. D-8./- a bus. * bus is a set of conducti"e paths that ser"e to interconnect two or more functional components of a s!stem or se"eral di"erse s!stems$ 33. D-8./- Ca61- <-<(,y.

2nd YEAR/ 4th SEMESTER

OM SATHI

ADHIPARASAKTHI COLLEGE OF ENGINEERING

@t is a relati"el! small, high-speed memor! that can store the most recentl! used instructions or data from larger but slower main memor!$ 34. 41a) .s )1- )-61/.Lu- a=(7)-= by DRAMs. D'*Ms use a techni+ue called address multiple#ing to reduce the number of address lines$ 35.G.;- )1- 8-a)u,- (8 U$ E#ROM. VA 0/'.M is electricall! programmable b! the user, but the store data must be erased b! e#posure to ultra "iolet light o"er a period of se"eral minutes$ 36. G.;- )1- 8-a)u,- (8 8las1 <-<(,y$ )he ideal memor! has high storage capacit!, non-"olatilit!, in-s!stem read and write capabilit!, comparati"el! fast operation$ )he traditional memor! technologies such as '.M, /'.M, 00/'.M indi"iduall! e#hibits one of these characteristics, but no single technolog! has all of them e#cept the flash memor!$ 3?. 41a) a,- &las1 <-<(,.-s: )he! are high densit! read4write memories that are non-"olatile, which means data can be stored indefinitel! with out power$ 3B. L.s) )1- )1,-- <aP(, (7-,a).(/s ./ a 8las1 <-<(,y. /rogramming, 'ead and 0rase operation 39. 41a) .s a &I&O <-<(,y: )he term %@%. refers to the basic operation of this t!pe of memor! in which the first data bit written into the memor! is to first to be read out$ 40. L.s) bas.6 )y7-s (8 7,(9,a<<abl- l(9.6 =-;.6-s$ 6$ 'ead onl! memor! 9$ /rogrammable logic *rra! =$ /rogrammable *rra! 1ogic 41. D-8./- a==,-ss a/= 0(,=. @n a '.M, each bit combination of the input "ariable is called on address$ 0ach bit combination that comes out of the output lines is called a word$ 42. 41a) .s 7,(9,a<<abl- l(9.6 a,,ay: !(0 .) =.88-,s 8,(< ROM: @n some cases the number of dont care conditions is e#cessi"e, it is more economical to use a second t!pe of 1&@ component called a /1*$ * /1* is similar to a '.M in concept, howe"er it does not pro"ide full decoding of the "ariables and does not generates all the minterms as in the '.M$

EE2255 DIGITAL LOGIC CIRCUITS

OM SAKTHI

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

43. 41a) .s <asF 3 7,(9,a<<abl-: Cith a mas programmable /1*, the user must submit a /1* /1* program table to the manufacturer$ 44. G.;- )1- 6(<7a,.s(/ b-)0--/ #ROM a/= #LA. #ROM 6$ *nd arra! is fi#ed and .' arra! is programmable$ 9$ Cheaper and simple to use$

#LA Both *ID and .' arra!s are /rogrammable$ Costliest and comple# than /'.M&$

45. M-/).(/ )1- 6lass.8.6a).(/ (8 sa)u,a)-= b.7(la, l(9.6 8a<.l.-s. )he bipolar logic famil! is classified as follows: ')1- 'esistor )ransistor 1ogic D)1- Diode )ransistor logic @91- @ntegrated @n7ection 1ogic ))1- )ransistor )ransistor 1ogic 0C1- 0mitter Coupled 1ogic

46. M-/).(/ )1- .<7(,)a/) 61a,a6)-,.s).6s (8 =.9.)al ICCs: %an out /ower dissipation /ropagation Dela! Ioise Margin %an @n .perating temperature /ower suppl! re+uirements 4?. D-8./- &a/3(u): %an out specifies the number of standard loads that the output of the gate can dri"e Cith out impairmen&t of its normal operation$ 4B. D-8./- 7(0-, =.ss.7a).(/: /ower dissipation is measure of power consumed b! the gate when full! dri"en b! all its inputs$ 49. 41a) .s 7,(7a9a).(/ =-lay: /ropagation dela! is the a"erage transition dela! time for the signal to propagate from input to output when the signals change in "alue$ @t is e#pressed in ns$

2nd YEAR/ 4th SEMESTER

OM SATHI

ADHIPARASAKTHI COLLEGE OF ENGINEERING

50. D-8./- /(.s- <a,9./: @t is the ma#imum noise "oltage added to an input signal of a digital circuit that does not cause an undesirable change in the circuit output$ @t is e#pressed in "olts$ 51. D-8./- 8a/ ./: %an in is the number of inputs connected to the gate without an! degradation in the "oltage le"el$ 52. 41a) .s O7-,a)./9 )-<7-,a)u,-: *ll the gates or semiconductor de"ices are temperature sensiti"e in nature$ )he temperature in which the performance of the @C is effecti"e is called as operating temperature$ .perating temperature of the @C "ar! from :: C to ;:: c$ 53. 41a) .s !.91 T1,-s1(l= L(9.6: &ome digital circuits operate in en"ironments, which produce "er! high noise signals$ %or operation in such surroundings there is a"ailable a t!pe of D)1 gate which possesses a high threshold to noise immunit!$ )his t!pe of gate is called ?)1 logic or ?igh )hreshold 1ogic$ 54. 41a) a,- )1- )y7-s (8 TTL l(9.6: 6$ .pen collector output 9$ )otem-/ole .utput

=$ )ri-state output$

55. 41a) .s =-7l-).(/ <(=- (7-,a).(/ MOS: @f the channel is initiall! doped lightl! with p-t!pe impurit! a conducting channel e#ists at Nero gate "oltage and the de"ice is said to operate in depletion mode$ 56. 41a) .s -/1a/6-<-/) <(=- (7-,a).(/ (8 MOS: @f the region beneath the gate is left initiall! uncharged the gate field must induce a channel before current can flow$ )hus the gate "oltage enhances the channel current and such a de"ice is said to operate in the enhancement mode$

5?. M-/).(/ )1- 61a,a6)-,.s).6s (8 MOS ),a/s.s)(,: 6$ )he n- channel M.& conducts when its gate- to- source "oltage is positi"e$ 9$ )he p- channel M.& conducts when its gate- to- source "oltage is negati"e =$ 0ither t!pe of de"ice is turned of if its gate- to- source "oltage is Nero$ 5B. !(0 s61())Fy ),a/s.s)(,s a,- 8(,<-= a/= s)a)- .)s us-: * schott ! diode is formed b! the combination of metal and semiconductor$ )he presence of schott ! diode between the base and the collector pre"ents the transistor from going into saturation$ )he resulting transistor is called as schott ! transistor$ )he use of schott ! transistor in ))1 decreases the propagation dela! without a sacrifice of power dissipation$

EE2255 DIGITAL LOGIC CIRCUITS

OM SAKTHI

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

59. L.s) )1- =.88-,-/) ;-,s.(/s (8 TTL 6$ ))1 3&td$))15 9$1))1 31ow /ower ))15 =$ ?))1 3?igh &peed ))15 D$&))1 3&chott ! ))15 T$ 1&))1 31ow power &chott ! ))15 60. 41y )()-< 7(l- (u)7u)s 6a//() b- 6(//-6)-= )(9-)1-,. )otem pole outputs cannot be connected together because such a connection might produce e#cessi"e current and ma! result in damage to the de"ices$ 61. S)a)- a=;a/)a9-s a/= =.sa=;a/)a9-s (8 TTL A=;a/)a9-sM 0asil! compatible with other @Cs 1ow output impedance D.sa=;a/)a9-sM Cired output capabilit! is possible onl! with tristate and open collector t!pes &pecial circuits in Circuit la!out and s!stem design are re+uired$ 62. 41-/ =(-s )1- /(.s- <a,9./ all(0 =.9.)al 6.,6u.)s )( 8u/6).(/ 7,(7-,ly: Chen noise "oltages are within the limits of AI*3?igh &tate Ioise Margin5 and AIK for a particular logic famil!$ #ART B 15 ED7la./ ./ =-)a.l ab(u) #LA 0.)1 a s7-6.8.6 -Da<7l-$ 0#planation about '.M Classifications of '.M *rchitecture of '.M &pecification of /1* &pecific 0#ample 'elated Diagram 'elated )able$ 25 I<7l-<-/) )1- 8(ll(0./9 us./9 a <uD. &@a%b%6%=5 ' G@0%1%3%4%B%9%155 .btain the truth table %rom the truth table realiNe the e#pressions for the outputs and inputs 'ealiNe the logic diagram$ 35 ED7la./ 0.)1 /-a) =.a9,a<s RAM a,61.)-6)u,-$ Different Memories Classification of memories '*M architecture diagram )iming wa"eforms

2nd YEAR/ 4th SEMESTER

OM SATHI

ADHIPARASAKTHI COLLEGE OF ENGINEERING

Coincident Decoding 'ead write operations 45 ED7la./ ./ =-)a.l ab(u) #LA a/= #AL. Basic '.M Classification of /'.M 1ogic difference between /rom & /1* 1ogic diagram implementing a function 1ogic difference between /rom & /*1 1ogic diagram implementing a function 55 ED7la./ 0.)1 /-a) =.a9,a<s a ROM a,61.)-6)u,-$ Different Memories Classification of memories )iming wa"eforms Coincident Decoding UNIT3$ $!DL T4O MAR+S 1. 41a) .s $-,.l(9: Aerilog is a general purpose hardware descriptor language$ @t is similar in s!nta# to the C programming language$ @t can be used to model a digital s!stem at man! le"els of abstraction ranging from the algorithmic le"el to the switch le"el$ 2. 41a) a,- )1- ;a,.(us <(=-l./9 us-= ./ $-,.l(9: 6$ 2ate-le"el modeling 9$ Data-flow modeling =$ &witch-le"el modeling D$ Beha"ioral modeling 3. 41a) .s )1- s),u6)u,al 9a)-3l-;-l <(=-l./9: &tructural modeling describes a digital logic networ s in terms of the components that ma e up the s!stem$ 2ate-le"el modeling is based on using primiti"e logic gates and specif!ing how the! are wired together$ 4. 41a) .s S0.)613l-;-l <(=-l./9: Aerilog allows switch-le"el modeling that is based on the beha"ior of M.&%0)s$ Digital circuits at the M.&-transistor le"el are described using the M.&%0) switches$ 5. 41a) a,- .=-/).8.-,s: @dentifiers are names of modules, "ariables and other ob7ects that we can reference in the design$ @dentifiers consists of upper and lower case letters, digits : through S, the underscore character3O5 and the dollar sign3X5$ @t must be a single group of characters$

'.M architecture diagram 'ead write operation

EE2255 DIGITAL LOGIC CIRCUITS

OM SAKTHI

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

0#amples: *:6D, a, b, inOo, sOout 6. 41a) a,- )1- ;alu- s-)s ./ $-,.l(9: Aerilog supports four le"els for the "alues needed to describe hardware referred to as "alue sets$ $alu- l-;-ls C(/=.).(/ ./ 1a,=0a,- 6.,6u.)s : 1ogic Nero, false condition 6 1ogic one, true condition J Vn nown logic "alue P ?igh impedance, floating state ?. 41a) a,- )1- )y7-s (8 9a)- a,,ays ./ ASIC: 65 Channeled gate arra!s 95 Channel less gate arra!s B. G.;- )1- 6lass.8.6a).(/s (8 ).<./9 6(/),(l Methods of timing control: 6$ Dela!-based timing control 9$ 0"ent-based timing control =$ 1e"el-sensiti"e timing control )!pes of dela!-based timing control: 6$ 'egular dela! control 9$ @ntra-assignment dela! control =$ Pero dela! control )!pes of e"ent-based timing control: 6$ 'egular e"ent control 9$ Iamed e"ent control =$ 0"ent .' control D$ 1e"el-sensiti"e timing control 9 .G.;- )1- =.88-,-/) a,.)1<-).6 (7-,a)(,s: O7-,a)(, sy<b(l O7-,a).(/ 7-,8(,<-= Y Multipl! 4 Di"ide G *dd &ubtract Z Modulus YY /ower 3e#ponent5

=5 &tructured gate arra!s

Nu<b-, (8 (7-,a/=s )wo )wo )wo )wo )wo )wo

10. G.;- )1- =.88-,-/) b.)0.s- (7-,a)(,s. O7-,a)(, sy<b(l O7-,a).(/ 7-,8(,<-=

Nu<b-, (8 (7-,a/=s

2nd YEAR/ 4th SEMESTER

OM SATHI

ADHIPARASAKTHI COLLEGE OF ENGINEERING

[ & \ ] ][ or [] [& [\

Bitwise negation Bitwise and Bitwise or Bitwise #or Bitwise #nor Bitwise nand Bitwise nor

.ne )wo )wo )wo )wo )wo )wo

11. 41a) a,- 9a)- 7,.<.).;-s: Aerilog supports basic logic gates as predefined primiti"es$ /rimiti"e logic function e!word pro"ides the basics for structural modeling at gate le"el$ )hese primiti"es are instantiated li e modules e#cept that the! are predefined in "erilog and do not need a module definition$ )he important operations are and, nand, or, #or, #nor, and buf3non-in"erting dri"e buffer5$ 12. G.;- )1- )0( bl(6Fs ./ b-1a;.(,al <(=-l./9. 6$ *n initial bloc e#ecutes once in the simulation and is used to set up initial conditions and step-b!-step data flow$ 9$ *n alwa!s bloc e#ecutes in a loop and repeats during the simulation$ 13. 41a) a,- )1- )y7-s (8 6(/=.).(/al s)a)-<-/)s: 6$ Io else statement &!nta#: if 3Le#pressionM5 true - statement, 9$ .ne else statement &!nta#: if 3Le#pressionM5 true - statement, else false-statement, =$ Iested if-else-if &!nta# : if 3 Le#pression6M 5 true statement 6, else if 3 Le#pression9M 5 true-statement 9, else if 3 Le#pression=M 5 true-statement =, else default-statement, )he Le#pressionM is e"aluated$ @f it is true 36 or a non-Nero "alue5 true-statement is e#ecuted$ @f it is false 3Nero5 or ambiguous 3#5, the false-statement is e#ecuted$ 14. Na<- )1- )y7-s (8 7(,)s ./ $-,.l(9 Ty7-s (8 7(,) +-y0(,= @nput port @nput .utput port .utput Bidirectional port inout 15. 41a) a,- )1- )y7-s (8 7,(6-=u,al ass.9/<-/)s: 6$ Bloc ing assignment

EE2255 DIGITAL LOGIC CIRCUITS

OM SAKTHI

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

9$ Ion-bloc ing assignment #ART B 15 Construct a full subtractor circuit and Crite a ?D1 program module for the same$ 3i5 Compare s!nchronous with *s!nchronous counters$ 3ii5 0#plain the beha"ioral Model with suitable e#ample$ 95 * positi"e edge triggered flip-flop has two inputs Dr and DN and a control input that chooses between the two$ Crite an ?D1 beha"ioral description of this flip-flop$ =5$ Crite an ?D1 beha"ioral description of ripple counter D5 Crite a ?D1 program module for full adder circuit$ T5 Crite a ?D1 program for four bit ripple carr! adder$

2nd YEAR/ 4th SEMESTER