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International Journal of Advanced Computer Science, Vol. 2, No. 6, Pp. 211-216, Jun., 2012.

An Ultra-Low power Current-Mode Amplitude Shift Keying Demodulator Dedicated for Implantable Electronic Devices in 0.35m CMOS Technology
Khalil Monfaredi, Yashar Hasimi
Manuscript
Received: 15,Aug., 2011 Revised: 20,Nov.,2011 Accepted: 18,Apr.,2012 Published: 29,Aug.,2012

Keywords
amplitude shift-keying demodulator, Current-Mode, Implantable electronic device, Ultra Low power

Abstract In this paper a novel ultra-low power CMOS integrated amplitude shift-keying (ASK) demodulator is presented which is dedicated for implantable electronic devices (IED). The proposed ASK demodulator (ASKD) has a simple structure, is optimized in order to consume the minimum possible power and is used to extract digital data from two-level ASK modulated current signal. The ASKD makes detection of current levels with very small modulation depth which is defined as the difference between the two allowable ASK amplitude levels, feasible. The circuit performance is validated by HSPICS software using 0.35mCMOS technology and power supply of 3V. The simulation results are proved for both conventional and proposed circuits by applying an input signal of 250 KHz at current amplitude varying between 4 and 4.5A which shows four times less power consumption comparing the conventional circuit. Another merit of the proposed ASKD circuit is its less complexity compared to the conventional ones which guarantees its robust operation against process tolerances. Favorably eliminating PMOS current mirror and reducing the number of NMOS current mirrors assures less mismatch error and higher linearity.

1. Introduction
Implantable electronic devices (IEDs), sensors and neurostimulators, are becoming more and more popular and widely accessible. These devices are used to stimulate nerves and muscles or to measure and sense different physiological signals such as blood pressure, temperature and strain from inside the bodies of human or animals [1, 2]. The popularity of these devices is due to the benefit of available smart medical devices and the technological research progresses in the different domains related to the fabrication process of IEDs.
Khalil Monfaredi is with Electrical and Electronics Engineering Faculty, Azarbaijan Shahid Madani University, Tabriz 5375171379, Islamic Republic of Iran. (Corresponding Author Email: khalilmonfaredi@gmail.com).

A typical IED is composed of two units: an external controller unit and an internal implanted unit. The internal part is implanted underneath the body skin and is intended to operate for long time interval. This unit is not directly accessible from the external world and hence has to be charged with a remote power transfer system such as magnetic or optic systems [3-6]. Moreover, to reduce the complexity of the IED, the same power transfer system is commonly used to carry out data transmission between the external controller and the implanted unit. To realize data transmission from internal part to the external system the signal carrying the data is modulated at the transmitter side, i.e. the implanted unit, and then it is demodulated and used at the receiver side, i.e. external controller unit. Similarly for data transmission from the external unit to the internal one the signal carrying the data is modulated at the transmitter side, i.e. the external controller unit, and then it is demodulated and used at the receiver side, i.e. implanted unit. Although there are several modulation techniques in the area of the IEDs data transmission [7] but the most popular and common one is the amplitude-shift keying (ASK) modulation. The previously reported works realizing ASKD, often suffer from high complexity, more non linearity, larger occupied chip area due to the multiple usage of current mirror circuits more especially PMOS ones in their structure. In this paper we propose a new ASKD with ultra low power capability and less chip area compared to the conventional circuits. Unlike the conventional ASKDs, in the proposed one the PMOS current mirrors are elaborately eliminated and the number of NMOS current mirrors are reduced which provides it with such outstanding properties as lower power consumption, less chip area, high linearity and robustness against mismatches. The proposed ASKD, based on current-mode technique, accepts ASK modulated input current and generates a demodulated digital output voltage. This ASKD is an improved version of the one described in [7]. The design is not complex, and it is less sensitive to process variation compared to other previous existing ASKD where transistor sizing is used to determine the threshold and trip voltages of their basic blocks such as comparators [8, 9]. In the next section, the ASK demodulator overview are presented in section 3 where we present the main building blocks of the novel ASK demodulator. Finally, section 4 and 5 contain preliminary results and conclusion respectively.

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International Journal of Advanced Computer Science, Vol. 2, No. 6, Pp. 211-216, Jun., 2012.

2. Description of the Proposed ASKD


The block diagram of the ASKD is shown in Fig. 1. It is composed of a current edge-detector, two current comparators and an output stage. The role of the edge-detector circuit is to detect the instants which the ASK modulated input current (Iin) changes its amplitude between the allowable ASK levels (Imin and Imax). The circuit generates a sink current-pulse (Isink) each time Iin changes from Imin to Imax (a positive transition); similarly, the circuit generates a source current-pulse (Isource) each time Iin changes from Imax to Imin (a negative transition). The generated current pulses are then converted to voltage pulses by means of two current-mode comparators. The extracted voltage pulses are used to control the output stage of the ASKD which comprises a triggered set/reset (SR) Latch.

processing stage. Using the delay circuit, the current IA is then delayed by a fixed delay (1) in order to generate an output current (IDy ) which is equal to IA but with a delay 1.

A. Current edge detector The schematic of the current edge-detector circuit is presented in Fig. 2, and its timing diagram is shown in Fig. 3. The edge- detector circuit comprises a gain and level-shifting (GALS) input stage, a current-delay circuit and two current subtractors. The circuit uses wide-swing cascoded current mirrors, which can be easily replaced by simple current mirrors for very low voltage applications. The role of the GALS input stage is to amplify the ASKD input current IIn and to shift the resulting current (IA) such that it remains within the operating range of the next

Fig. 1. Simplified block diagram of the proposed ASKD.

By comparing IA and IDy, the two subtractors generate the required output current-pulses (ISource and ISink), which correspond to the positive and negative input current transitions (Fig. 3). In the case where there are no changes in the amplitude of the input current, the output current of each sub-tractor remains continually equal to zero. 1) Gain and Level Shifting Circuit The role of the GALS input stage is to amplify the difference (I) between the two allowable levels (I min and Imax) of the ASK modulated-input current. The reason behind this

Subtractor 1

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Fig. 2. Schematic of the ASKD current edge detector.

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Monfaredi et al.: An Ultra-Low power Current-Mode Amplitude Shift Keying Demodulator Dedicated for Implantable Electronic Devices in 0.35m CMOS Technology.

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amplification is to provide the circuit with the ability to demodulate ASK modulated-input currents having very small modulation depths ( I). The schematic of the proposed GALS circuit is shown in Fig. 4a and its timing diagram is depicted in Fig. 4b. This circuit amplifies the ASK modulated input current IIn, then the amplified current (I X) is level-shifted such that its amplitude (IA) remains within the operating range of the next processing circuit. The required current amplification is realized using the current mirror composed of the transistors M 3 and M4 where the gain amplification is determined by the aspect ratio of M3-M4. To generate the output current (IA), the amplified current (IX) is shifted down by subtracting the fixed reference input current (IS) from IX using the three current mirror stages (M1-M2), (M5-M6) and (M7-M8). As shown in Fig. 4b, the output current IA has exactly the same variations as the input current IIn but with increased levels which fall in allowable ASKD range. Improved version of Gain and level shifting block is presented at Fig. 4c. In this version four transistors namely M3, M4, M5, and M6 which are functioning as gain providers and since are relatively large with more power consumption and with more transfer error were eliminated and instead the M8 provides the current gain. Eliminating PMOS transistors is considered another advantage because of its degraded frequency response. The occupied area becomes small and this is an important factor for implantable devices which small chip size is a crucial parameter. Favorably current subtraction at first stage allows the reduction of the number and also current amplitude needed for current sources which effectively reduces the total power consumption of the circuit.

Fig. 4b. Timing diagram of the gain and level shifting input stage.

Iin IS Iin-IS IS
M1 M2 M7 M8

IA

Fig. 4c. Improved version of Fig. 4a.

Fig. 3. Timing diagram of the ASKD current-edge detector.

2) Current-delay circuit As shown in Fig. 2, the current delay circuit is implemented using the current mirror (M 1_1-M1_4) and the low-pass filter composed of the resistor R and the capacitor C. In order to keep the overall area of the circuit small, the resistor R of the low-pass filter is implemented using a PMOS transistor biased in its linear region (triode). The filter is inserted between the transistors of the current mirror (M1_1-M1_4) such that the gate voltage Vp2 of M1_1 is delayed and applied to the gate of M1_3. It follows that, if the size of M1_3 is equal to that of M1_1, the current IDy of M1_3 will be equal to the current IA but with the delay which is determined by the low-pass filter time constant (RC). 3) Current-Subtractors The role of the two current subtractors of the edge-detector circuit is to generate the sink and source current pulses (ISink and ISource) which correspond respectively to the

IX IS Iin

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Fig. 4a. The gain and level shifting input stage of the edge-detector.

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positive and the negative transitions of the input current IA. As shown in the timing diagram of Fig. 3, these current pulses can be generated by computing the differences (I AIDy) and (IDyIA) respectively. To generate the source current I Source the subtractor 1 which comprises the transistor M 1_7-M1_14 of the edge detector circuit (Fig. 2) is used to compute the difference (IDyIA). Since the output current of this circuit (I Source) is a source current, it can be active only when I Dy is greater than IA; in the other cases when I Dy is equal or less than I A, ISource will be simply equal to zero. Similarly, to generate the sink current ISink the subtractor 2 which comprises the transistor M1_15-M1_22 of the edge detector circuit (Fig. 2) is used to compute the difference (I AIDy). Since the output current of this circuit (ISink) is a sink current, it can be active only when IA is greater than IDy.

The speed of this comparator is determined by the change rate of the input current I In and the difference between I In and IRef. Therefore if IIn changes slowly or the difference between the two currents is too small, the comparator speed would be very low and consequently it can limit the demodulator performances. To alleviate this problem, we modified the conventional comparator version to the proposed one.

C. Output Stage
In order to recover the demodulated data, the outputs of the two comparators are used to control the ASK output stage which is based on a simple triggered Set/Rest (SR) Latch. The schematic of this stage is presented in Fig. 6. It comprises an SR latch and two positive (rising) edge detectors. The SR latch is a simple digital circuit using two cross-coupled NOR gates while each edge detector is composed of one AND gate and one delay-element with an intrinsic delay equal to . The delay element is simply implemented using cascaded inverters. The aim of the two positive edge detectors is to generate the required latch Set (S) and Reset (R) control signals from the current comparators of the ASKD. The improved comparator version is obtained by adding the transistors (M2_9-M2_10 and M3_9-M3_10) of the shadowed area to the basic comparator architecture (Fig. 5). In this new configuration, the input current I In is not only applied to the PMOS current mirror but it is also applied to the NMOS current mirror. To do so, a copy of the input current IIn is injected in the node Y of the NMOS current-mirror. In such conditions, when the input current rises and becomes greater than the reference current, the current of transistors M 2_4 and M3_4will be entirely drawn from the extra transistors (M2_9-M2_10 and M3_9-M3_10) and not from M2_3 and M3_3 as it is the case in the basic architecture.

B. Current comparators
The purpose of the current comparators is to convert the current pulses (ISource and ISink) generated by the subtractors of the edge detector circuit to equivalent digital voltage pulses. These comparators are based on a current-mode circuit which is composed of an input current stage and a voltage output stage (voltage inverter). Such basic architecture is shown in Fig. 5 where the transistors located in the shadowed area are excluded. The input current stage comprises two complementary current mirrors, an NMOS one (M 2_1-M2_4 and M3_1-M3_4) and a PMOS one (M2_5-M2_8 and M3_5-M3_8). This stage compares the input current (I In) to a reference current (IRef) and the resulting current is used to drive the output stage. The current IRef is used to bias the input stage and determine the comparator threshold transition point. In the absence of any current pulse, when the input current is equal to zero, I Ref will force the output of the inverter to be equal to V dd (the logic 1). When an input current pulse changes and once I In becomes greater than I Ref, the inverter changes its output state from Vdd to 0V (the logic 0). In the same way, when I In returns to zero, the inverter changes its output state and returns to V dd.

Therefore, the current of the transistors M 2_3 and M3_3 will be equal to zero and the comparator output inverter will be

M2_6

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Fig. 5. Schematic of the comparator used to convert input current pulses to digital voltage pulses.

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driven by the current of M 2_7 and M3_7 and M2_8 and M3_8 which is equal to I In. Since in this case, the input capacitor of the output inverter is charged by I In instead of the difference between IIn and IRef, the switching time of this inverter becomes very small. Therefore the speed of the comparator is improved. Using the same strategy, the basic comparator of Fig. 5 can be modified accordingly to convert source current pulses instead of sink current pulses. To do so, it is necessary to interchange the input and the reference currents (I In, IRef) such that IIn is applied to the NMOS current mirror and I Ref is applied to the PMOS current mirror. Moreover, the two extra PMOS transistors (M2_9-M2_10 and M3_9-M3_10) should be replaced by two NMOS transistors which carry a current equal to IIn that is injected in the node Z instead of the node Y.

operation of the proposed circuit with additional advantages of less power consumption and less occupied chip area.

Fig. 7b. Simulation result for Fig. 4c.

Fig. 6. Output stage of the ASKD

3. Preliminary Results
The proposed circuit of the Fig. 4c, the conventional circuit of Fig. 4a, and the modified comparator of Fig. 5 are simulated with HSPICE using 0.35 m CMOS technology. An input current with frequency of 250 KHz and amplitude which varies between two distinct levels of 4A and 4.5 A are used for evaluations. It worth noting that gain of the Gain and Level Shifting Stage are set to four. Figure 7a and 7b show the simulation results of the conventional and the proposed gain and level shifting stages of the edge detector respectively.

Fig. 8a. Post-layout simulation results of the proposed ASKD.

Fig. 8b. Simulation result for Fig 5 (without shadowed area).

Fig. 7a. Simulation result for Fig 4a.

These results prove the effectiveness of the proposed approach while preserving the low power consumption. The simulation results of the comparator used to convert input current pulses to digital voltage both conventional (without shadowed area) and proposed (with shadowed area) (Fig. 4) are shown in figures 8a-8c. The results proved the correct
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Fig. 8c. Simulation result for Fig 5 (without shadowed area).

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International Journal of Advanced Computer Science, Vol. 2, No. 6, Pp. 211-216, Jun., 2012. [4] Djemouai, M. Sawan & M. Slamani, "An Efficient RF Power Transfer and Bidirectional Data Transmission to Implantable Electronic Devices," (1999) ISCAS99, pp. II-259-262. [5] Djemouai, M. Sawan & M. Slamani, "Improved Biotelemetry System with an Integrated Automatic Control and On-Chip Reference Frequency," (1999) IFESS1999. [6] K. Goto, T. Nakagawa, O. Nakamura & S. Kawata, "An Implantable Power Supply with an Optically Rechargeable Lithium Battery," (2001) IEEE Transactions on BME, Vol. 48, No. 7, p. 830 - 833. [7] Djemouai & M. Sawan, "Integrated ASK Demodulator Dedicated to Implantable Electronic Devices," (2003) The 46th IEEE Midwest Symposium on Circuits and systems. [8] Gunnar Gudnason, "A low-power ASK demodulator for inductively coupled implantable electronics," (2000) Proc. 26th European Solid-State Circuits Conference (ESSCIRC), pp. 404-407, Stockholm, Sweden. [9] R. Harjani, O. Birkenes & J. Kim, "An IF Stage Design for an ASK-Based Wireless Telemetry System," (2000) ISCAS2000, I52-55. [10] Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001, chapter 5. [11] Djemouai & M. Sawan, "New CMOS Current-Mode Amplitude Shift Keying Demodulator (ASKD) Dedicated for Implantable Electronic Devices," (2004) IEEE, ISCAS.

Fig. 8d. Simulation result using Fig. 4c and Fig 5 (without shadowed area).

Fig. 8e. Simulation result using Fig. 4c and Fig 5 (without shadowed area).

4. Conclusions
A new CMOS integrated current-mode ASK demodulator dedicated for implantable electronic devices was presented. The circuit was based on current mode techniques, it accepted modulated analog current signal at the input and generated demodulated digital voltage signal at the output. The demodulator could process modulated input current, which could have a very small difference between the two levels defining its amplitude. Improved version of Gain and level shifting block was presented in which one PMOS and one NMOS current mirrors which were functioning as gain providers with relatively large aspect ratios were eliminated. Eliminating PMOS transistors improved the frequency response of the proposed circuit. The circuit was simulated with HSPICE software using 0.35m, 3V CMOS technology. Preliminary post-layout simulation results were also provided.

References
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