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ECE/CS Final Exam

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Last (family) name: ____SOLUTION__________

First (given) name: _________________________

Student I.D. #: _____________________________

Circle section: Saluja Ramanathan

Department of Electrical and Computer Engineering
University of Wisconsin - Madison

ECE/CS 352 Digital System Fundamentals

Final Examination
Tuesday, December 16, 2003, 12:25 2:25 PM

Instructions:
1. Closed book examination.
2. No calculator, hand-held computer or portable computer allowed.
3. You must show your complete work. Points will be awarded only based on what appears in
4. Five points penalty if you fail to enter name, ID#, or instructor selection.
5. No one shall leave the room during the last 5 minutes of the examination.
6. Upon announcement of the end of the exam, stop writing on the exam paper immediately.
Pass the exam to aisles to be picked up by a TA. The instructor will announce when to leave
the room.
7. Failure to follow instructions may result in forfeiture of your exam and will be handled
according to UWS 14 Academic misconduct procedures.

Problem Points Score
1 18
2 15
3 13
4 15
5 15
6 8
7 8
8 8
Total 100

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1. (18 points) Truth table, canonical forms, minimization
(a) (5 points) Represent function realized by the logic circuit given below in Sum of
Minterms canonical form.

A
B
C
D
g

D B A C B A F
D C A B B A A B A F
+ =
+ + + + + = ) ( )] ( ) [(

(b) (4 points) Draw a realization of the function below in two level NAND/NAND form.
Assume that inputs are available only in uncomplimented forms.

D C B C B A F + + + =

g(A,B,C,.D) = ( 8, 10, 11 )
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(c) (4 points) Represent F(A,B,C,D) in the equation above (Problem 1b) in Product of
Maxterm canonical form.

(d) (5 points) A combinational circuit F depends on three inputs A, B, and C. The input-
output behavior of the circuit is shown in the following waveforms. Write the function F
in minimum two level SOP form. You must show all your work. No points will be
awarded for just writing the final answer.
A
B
C
F

C B A F + =

F(A,B,C,.D) = ( 3, 5 )
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2. (15 points) Minimization Quine-McClusky method (Tabular method) Prime implicant
generation
Let: G(w,x,y,z) = m(0, 4, 5, 6, 7, 9, 10, 12, 13, 15)
Execute the Quine-McCloskey algorithm to find all the Prime Implicants of the function
The algorithm has been started for you below (minterms are listed in increasing 1s count
order). Complete the algorithm and CIRCLE the PRIME IMPLICANTS. You will be
penalized severely if any of the implicant or prime implicant generated by is not an
implicant or prime implicant.

m
i
Index Order 1-Cubes 2-Cubes
0 0000 0 0 - 0 0 1 - -
4 0100

0 1 0 -

- 1 0 -
5 0101

0 1 - 0

-1 - 1
6 0110

- 1 0 0

9 1001

0 1 1

10 1010

- 1 0 1

12 1100

0 1 - 1

7 0111

1 0 1

13 1101

1 1 0 -

15 1111

- 1 1 1

1 1 - 1

Answer: The prime implicants are:

1 0 1 0 0 0 0 1 0 1

0 1 - - - 1 0 - - 1 - 1
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3. (13 points) Finite state machine Excitation map
(a) (12 points) A single input six state (Sa, Sb, Sc, Sd, Se, Sf) finite state machine is realized
using 3 flip-flops. A D type FF is used to realize the variable Q1, a T FF is used to realize
the variable Q2, and a JK type FF is used to realize the variable Q3. Partially completed
exitation map and the next states are listed in the table below. Complete all entries in the
table. Note that two combinations of state encodings are not used and these are Q1 Q2 Q3 =
010 and 111.

State Code
Present State Input Next State Output Flip-Flop inputs

State
Q1 Q2 Q3 I Q1(t+1) Q2(t+1) Q3(t+1) Y D1 T2 J3 K3
Sa 0 0 0 0 0 0 1 1 0 0 1 X
0 0 0 1 0 0 0 1 0 0 0 X
Sb 0 0 1 0 1 0 0 0 1 0 X 1
0 0 1 1 0 1 1 0 0 1 X 0
- 0 1 0 0 X X X X X X X X
0 1 0 1 X X X X X X X X
Sc 0 1 1 0 1 0 0 0 1 1 X 1
0 1 1 1 1 0 1 0 1 1 X 0
Sd 1 0 0 0 1 1 0 0 1 1 0 X
1 0 0 1 1 0 1 0 1 0 1 X
Se 1 0 1 0 1 1 0 0 1 1 X 1
1 0 1 1 0 0 0 1 0 0 X 1
Sf 1 1 0 0 1 1 0 0 1 0 0 X
1 1 0 1 0 0 0 1 0 1 0 X
- 1 1 1 0 X X X X X X X X
1 1 1 1 X X X X X X X X

(b) (1 points) Is the above machine a Mealy or a Moore machine?
Answer: Mealy, because when the machine is in state 101 it produces outputs
based on the input value.

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4. (15 points) Sequential circuit design: Problem description to FSM
!n this problem, you are to draw a state diagram of a pattern recognizer. The pattern recognizer has one
input X and one output Z. The output Z goes high if it sees a pattern 11 on the input except when 11 is
immediately preceded by the pattern 10. For example, input pattern 0011 should have a output 1 at the
+th bit but the input pattern 1011 should not produce a 1 at the +th bit. Also, assume that there is no
sharing of 1s in the pattern detection. Thus, input pattern of 00111 should produce a output 1 at the +th
bit and a 0 at the 5th bit. Also, an input pattern 11011 should produce a 1 at the 2nd and the 5th bit
positions. After power up, assume the recognizer starts at the state called !N!T. Draw a state diagram of
a Nealy type FSN for this pattern recognizer.

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5. (15 Points) Datapath
(a) (11 points) The simple datapath studied in Chapter 7 is used for this question. The
detailed description of the micro-operations and control bits is attached to the end of this
exam. Use it to help answer the following questions. FILL in the table below with the
appropriate missing entries. If the field is unused, denote it by placing a dash " -- " in the
field. All microinstruction values are BINARY.

Operation DA AA BA MB FS MD RW Data in Constant in
R0 R1 + R2 000 001 010 0 00010 0 1
R3 (57)
16
011 - - - - 1 1 0101 0111
or 011 - - 1 10000 0 1 - 0101 0111
R3 sr R3 011 -- 011 0 1 0 1 0 0 0 1 -- --
R0 R5^(F5)
16
000 101 - 1 01000 0 1 - 1111 0101
R2 2R3 010 011 011 0 00010 0
1

or 010 - 011 0 11000 0 1 - -
= multiply (you may have think about this a little)

(b) (4 points) Registers R1 and R2 have the values shown in the table below. Fill in the
VALUE of Register R0 AFTER the instruction executes. Also fill in the C, Z, N, and V
bits that change based on the operations. NOTE: all representations are in 2s
complement format and arithmetic operations take place using 2s complement
arithmetic.

Operation R0(t+1) R1(t) R2(t) C V Z N
R0 R1 + R2 0 0 0 0 0 0 0 0 11111111 00000001 1 0 1 0
R0 R1 R2 1 1 1 1 1 1 1 0 11111111 00000001 1 0 0 1

11111111
+ 00000000
1 00000000

11111111
+ 11111111
1 11111110
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6. (8 points) ASM realization
Consider the ASM given below. Implement this using one flip-flop per state approach. Some of
the components needed for the implementation are drawn below. You may require additional
gates to implement the logic. Use as few gates as possible. Excessive use of additional gates will
be penalized.

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7. (8 points) RAM
Design and all the relevant information for a memory module is given in the figure below.
M3
CS
M2
CS
M1
CS
M4
CS
0
1
2
3
1
1
1
1
1
data bus
CS
16
14
14
14
14
14
R / W

(a) (1 points) What is the size of module M1: Where K = 2
10

(b)(1 points) What is the size of this memory: Where K = 2
10

(c) (2 points) If an address (54A3)
16
and a read command is issued which memory module will
place date on the data bus.
Module M2

(d) (2 points) What is the maximum address of any bit in M2. Write your answer in Hex.

(e) (2 points) What is the minimum address of any bit in M3. Write your answer in Hex.

16 Kb
64 Kb
7FFF
8000
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8. (8 points) ROM and PLDs
(a) (4 points) An 8X2 bit ROM given below is to be used to realize a full adder. Program this
ROM.

A B C S C
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

(b) (4 points) Realize the three variable function
C B A F =
using the PLD
(attahced figure if a PAL) provided. Note that I have already marked the inputs to the PAL as
well as the pin at which the function F should be produced.

ABC C B A C B A C B A C B A + + + =

0
1
2
3
4
5
6
7
A
i
B
i
C
i
S
i
C
i+1
ABC C B A C B C B A + + + = ) (
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Basic Identities of Boolean Algebra

1. X + 0 = X 2. X 1 = X
Existence of 0 and 1
3. X + 1 = 1 4. X 0 = 0
Existence of 0 and 1
5. X + X = X 6. X X = X
Idempotence
7. X + X =1 8. X X = 0
Complement
9. X =X

Involution
10. X + Y = Y + X 11. X Y = Y X
Commutative Law
12. X + (Y + Z) = (X + Y) + Z 13. X (YZ) = (XY) Z
Associative Law
14. X(Y + Z) = XY + XZ 15. X + YZ = (X + Y)(X + Z)
Distributive Law
16. X Y X Y + = 17. X Y X Y = +
DeMorgans Law

Useful Boolean Identities

X + XY = X X XY X Y + = +
XY XY X + =
XY XZ YZ XY XZ + + = +
( )( ) X Y X Y X Y X Y + + = + ( )( ) X Y X Y X + + =

Flip-Flop Characteristics Tables

JK Flip Flop
SR Flip-Flop
J K Q(t+1) S R Q(t+1)
0 0 Q(t) 0 0 Q(t)
0 1 0 0 1 0
1 0 1 1 0 1
1 1
) (t Q
1 1 Indetminate

D Flip-Flop
T Flip-Flop
D Q(t+1) T Q(t+1)
0 0 0 Q(t)
1 1 1
) (t Q