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260

ELECTRON IEEE

DEVICE LETTERS, VOL. EDL-8, NO. 6, JUNE 1987

Complementary GaAs MESFET Logic Gates
STEVEN M. BAIER, MEMBER, IEEE, GI-YOUNG LEE, M E M B E R ,
IEEE,

H. K. CHUNG, B. J. FURE,

AND

R. MACTAGGART

Abstract-Operation of the first complementary GaAs MESFET (CMES) logic gates is reported. Direct-coupled inverters utilizing p- and n-channel ion-implanted MESFET’s demonstrate good transfer characteristics with less than 5-pW power dissipation per gate.Propagation delays as small as 54 ps are attained in 13-stage ring oscillators at room temperature with speed-power products as small as 6 fJ.

I. INTRODUCTION aAs MESFET’s have attracted considerable attention as components of ultra-high-performance integrated circuits. Although n-channel GaAs DCFL circuits have demonstrated impressive speed results [I], a complementary p- and n-channel GaAs logic similar to silicon CMOS is preferable for higher integration levels because of the larger noise margin and much reduced power dissipation. Complementary GaAs logic is currently being explored with HIGFET [2] and MODFET [3] technologies. However, heterostructure devices are complicated to fabricate and generally require cryogenic cooling to achieve high performance. An ion-implanted complementary MESFET approach would offer switching speeds superior to silicon at very low power levels without the requirements of epitaxial growth and cryogenic circuit operation. Complementary GaAs MESFET logic has been inhibited by poor p-FET transconductance and voltage swing [4]. However, by utilizing a Schottky barrier tailoring technique and self-aligned source-drain implants, we have recently fabricated ion-implanted p-channel GaAs MESFET’s with extrinsic transconductances as large as 22 mS/mm at room temperature and gate turn-on voltages in excess of 1.2 V [ 5 ] . Basedon these devices, a complementary GaAs MESFET (CMES) technology has been developed and we report here characteristics of the first operational logic circuits.

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We have found that the key to a successful ion-implanted complementary GaAs technology is the use of barrier-height tailoring to improve p-FET characteristics. Without this technique, gate leakage in both forward and reverse biases severely limits voltage swing, current drive, and transconductance of the p-channel device. With the tailored-barrier-height (TBH) implant, p-channel FET gate turn-on voltages routinely exceed - 1.2 V. (We define gate turn-on voltage as the forward gate bias at which gate current equals 5 pAlpm2 of gate area.) Extrinsic peak transconductance of 1.0-pm gate length p-MESFET’s averages 15 mSlmm with a threshold voltage of - 0.25 V. Without the TBH implant, transconductances as high as 33 mS/mm have been measured. R-MESFET V,uniformity is in the range 130-190 mV across 3-in wafers with the TBH implant; this will improve as the process matures. The extrinsic transconductance of 1.0-pm n-channel MESFET’s averages 200 mS/ mm at gate turn-on voltages of 0.68V, with a threshold voltage of +0.15 V. The family of drain characteristics for typical n- and p-channel devices is illustrated in Fig. 1. 111. CIRCUIT RESULTS Based on these devices, complementary GaAs MESFET inverter and ring-oscillator circuits have been fabricated. The voltage transfer curve of a typical CMES inverter is shown in Fig. 2. This inverter is direct coupled (see Fig. 3), utilizing a 1 X 10-pm n-FET and 1 X 20-pm p-FET, and unloaded. With v d d = 1.O V, the inverter exhibits’ stable high and low logic states of 0.98 and 0.23V, respectively. As expected in a complementary gate, supply current I d d is very small in the stable logic regions (1.1 and 100 nA, respectively). During switching, the power dissipation reaches a peak of 2.3 gW. This is a factor of 10-20 lower than for unloaded DCFL inverters. To access noise margin, CMES inverters with several fanouts were fabricated. Using the “largest square” definition [6] we found noise margins in the range of 150-200 mV for CMES gates with fan-outs of 1 and 2 (see Fig. 4). ‘This is comparable to the performance of n-channel DCFL’s. Also, we found CMES and DCFL noise margins are limited by the same factor, namely, diode clamping of the n-channel FET in the next stage. With fan-outs of 1 and 2, CMES power dissipation was still lower than DCFL by a factor of 5-10. The inverters were functional over the temperature range - 60 to + 140°C. In addition, CMES switching characteristics were found to be less temperature-sensitive than comparable DCFL gates in terms of noise margin and switching levels. The mechanism for this temperature stability is not clear at this time. It may be related to the fact that n- and p-channel FET

11. FABRICATION PROCESS The CMES IC process is completely ion implanted and planar, using 29Si and 24Mg for the nand p-channels, respectively. Both n- and p-FET’s are self-aligned to WSi, gates. The p-FET has an additional 29Si implant beneath the gate for barrier-height enhancement. Rapid optical anneal is used for implant activation. Complete fabrication details have been published previously [5].
Manuscript received January 27, 1987;revised March 16, 1987. This work was supported in part by the Avionics Laboratory, Wright-Patterson AFB, OH, under Contract F33615-85-C-1704. S. M.Baier,H. K. Chung, B. J. Fure, and R.Mactaggartare with the Honeywell Physical Sciences Center, Bloomington, MN 55420. G . - Y .Lee was with the Honeywell Physical Sciences Center, Bloomington, MN 55420. He is now with Gould, Inc., Rolling Meadows, IL. IEEE Log Number 8714950.

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Concomitant power dissipation was 1. 0. In a more complex circuit with significant interconnect capacitance. + threshold voltages have opposite temperature coefficients. .2010 at 02:19:01 EDT from IEEE Xplore.1 Vistep. Downloaded on April 03. Authorized licensed use limited to: Alcatel Space Industries.8 mVl0 C. (a) n-FET is1 X 10 Frn with top curve at V .45 0. -2.2 mwlstage. the inverter transition region is not shifted monotonically to lower input voltages as in DCFL. FET sizes are 1 X 10 pm for n-FET and 1 X 20 pm for p-FET.1. CONCLUSION dd i Fig.0 V.75 Input Voltage [VI Fig.O.60 0. Unusually small gate turn-on voltage degrades output high logic level but a high gain is maintained with increasing fan-out.0 0.and p-channel GaAs MESFET's fabricated on the same wafer.15 0.30 0.3.and p-FETS's at: V d d = 2. Z P B 0.. . a larger p:n FET width ratio would be desirable to improve rise time since the increased gate capacitance would be less significant.7 V. 7 V.0 V.0 Drain6ource Voltage [VI 0 Input Voltage [VI Fig. : COMPLEMENTARY GaAs MESFET LOGIC GATES 26 I 500 5 3 400 I E t 300 .o 2. (b) p-FET is 1 X 20 pm with top curve at V. Switching delays as low as 54.8 ' 1.3 fJ (700 ps at 9 pW). Vdd = + 0. -0. This occurs because propagation in a 13-stage ring oscillator is limited by total gate capacitance. A barrier tailoring technique is utilized to improve p-FET characteristics.5 and + 1. Ids-Vdf family of curves for typical n.45 F. Schematic diagram of direct-coupled complementary inverters used in this work. 200 3 0 P 100 0 0 1. Voltage transfer and supply currentcurvesfora typical directcoupled CMES inverter at room temperature with v d d = 1.respectively.1. 1. Characteristics are more with respect to temperature. = 2 Complementary GaAs circuits have been successfully fabricated by ion implantation. 3.0 . = f 0 .0 (b) Fig.Source Voltage[VI 3. As temperature rises.200 .b z 2 -50 c 3 E B e . 5 for a variety of p:n FET width ratios. Direct-coupled 13-stage CMES ring oscillators were also fabricated. Speed-power curves are reported in Fig.- a -100 8 -150 . The best speed-power product we have observed for CMES to date is 6. Restrictions apply.6 0 0.0 0. Voltage transfer curves for CMES inverters with variety of fan-out conditions. 4. Direct-coupled complementary GaAs MESFET inverters demonstrate switching characteristics to DCFL but with 5-20 times lower power dissipation. The best room-temperature speed results (54. = .4 ' d . 2.1.0 (a) 0 ' 0:2 ' d. 6 Input Voltage [VI ' b. not interconnects.4.0 Drain.BAIER et al.6 ps) were obtained with 1 X 10-pm gate dimensions for both n. RO propagation delay is seen to increase with p:n FET width ratio.15 0.2 Vistep. IV.

Santa Barbara. SC-18. Fure. Wiegmann. ps were obtained from 13-stage complementary ring oscillators. Shur. Lee. Cirillo. JUNE 1987 \ \ ACKNOWLEDGMENT KEY 0 4 1 P’N ratio A 2 5 1P . Stuelke in device and circuit.” IEEE J.VOL. Y. no. Chung. 1984. K. and preparation of the manuscript by R. H. Vold. and N.’’ presented at the 42nd Annual Device Res. Dec. A. “High speed and ultra-low power GaAs MESFET 5 X 5 multiplier. Oct. 5 .E. “Ion-implanted GaAs p-channel MESFET using Schottky barrier height tailoring. 6. and K. the work of D.Seevink. CMES is thus an attractive technology for ultra-highspeed radiation-hard logic and memory applications. P. June 24. and W. Tan. Conf. Abrokwah. J. 1986. V rati. L.EDL-8. Authorized licensed use limited to: Alcatel Space Industries.“Worst-case static noise margin criteria for logic circuits and their mathematical equivalence. CA.2010 at 02:19:01 EDT from IEEE Xplore. Gossard. June 18-20. Baier. Santa Barbara.NO.. C. pp. Speed-power performance of direct-coupled 13-stage complementary GaAs MESFET ring oscillators at room temperature. Jr. 803-807. Amherst. Los Angeles. Grenelefe. Baek. 0. G.Stormer. offering much reduced power consumption without the requirements of epitaxial growth or cryogenic circuit operation.” presented at the 42nd Annual Device Res. FL. K. . S. Solid-state Circuits. P:N FET width ratio is 1:l. Chung. P.C. Nakayama et al.. H..A. and J . and M.characterization. Lee. R. Y . 1983. “Modulation doped field effect transistors and logic gates based on two-dimensional hole gas. Restrictions apply. vol. MA. “GaAs self-aligned p-channel MESFET for highspeed complementary circuit.”presented at the 1986 IEDM. deGroot. June 18-20.” presented at the 1986 Device Research Conf. Tufte. McPherson.IEEEELECTRONDEVICELETTERS. R. Daniels. 0 1 1 P’N ratio \d \ The authors wish to acknowledge useful discussions with B . J. K.. Jenkins. CA. REFERENCES Power DissipationPer Stage (mW) Fig. Betz.Kiehl. B. Downloaded on April 03. Grung. H. 28! 1986. Lostroch. Conf.. G. 6. “Heterostructure insulated-gate FET’sfor VSLI applications. CA.” presented at the IEEE GaAs IC Symp. Baldwin. J. J.. 1984.