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Code: 9A04306

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DIGITAL LOGIC DESIGN
(Computer Science and Engineering)

B.Tech II Year I Semester (R09) Regular & Supplementary Examinations December/January 2013/14

Time: 3 hours Answer any FIVE questions All questions carry equal marks *****
1 (a) Convert the following numbers: (i) (41. 6875)10 to hexadecimal number. (ii) (11001101. 0101)2 to base -8 and base 4. (iii) (4567)8 to base 10. Add and multiply the following numbers without converting them to decimal: (i) Binary numbers 1011 and 101. (ii) Hexadecimal numbers 2E and 34. Simply the following Boolean expressions to minimum number of literals: � 𝐶𝐶̅ + 𝐴𝐴𝐴𝐴𝐴𝐴 + 𝐴𝐴 𝐶𝐶̅ . 𝐴𝐴 (𝐴𝐴̅ + 𝐶𝐶 )(𝐴𝐴̅ + 𝐶𝐶̅ )(𝐴𝐴 + 𝐵𝐵 + 𝐶𝐶̅ 𝐷𝐷). 𝐴𝐴𝐴𝐴𝐴𝐴 + 𝐴𝐴̅ 𝐵𝐵 + 𝐴𝐴𝐴𝐴𝐶𝐶̅ . �) (𝐵𝐵𝐶𝐶̅ + 𝐴𝐴̅𝐷𝐷)(𝐴𝐴 � 𝐵𝐵 + 𝐶𝐶𝐷𝐷 ��������� ��������� ̅ �) (𝐴𝐴 + 𝐵𝐵 ) (𝐴𝐴 + 𝐵𝐵

Max Marks: 70

(b)

2 (a) (b) (c) (d) (e) 3 (a) (b) 4 (a) (b)

Simplify and implement the following SOP using NOR gates f(A, B, C, D) = ∑𝑚𝑚 (0, 1, 4, 5, 10, 11, 14, 15). Reduce the following function using K-map technique f (A, B, C, D) = 𝜋𝜋𝑚𝑚 (0, 2, 3, 8, 9, 12, 13, 15).

5 (a) (b) 6 (a) (b) 7 (a) (b)

Implement BCD to 7-segment decoder for common anode using 4:16 decoder. � 𝐵𝐵𝐷𝐷 � + 𝐴𝐴𝐴𝐴𝐴𝐴 + 𝐵𝐵 � 𝐶𝐶𝐶𝐶 + Implement the following Boolean function using 8:1 multiplexers F(A, B, C, D) = 𝐴𝐴 � ̅ 𝐴𝐴 𝐶𝐶 𝐷𝐷.

Draw the circuit diagram of clocked D-flip flop with NAND gates and explain its operation using truth table. Give its timing diagram. Draw the logic diagram of a JK – flip flop and explain. Explain synchronous and ripple counters. Compare their merits and demerits. Design Mod-10 counter using T-Flip flop. Give the comparison between PROM, PLA and PAL. A combinational circuit is defined by the functions 𝐹𝐹1 (𝐴𝐴, 𝐵𝐵 , 𝐶𝐶 ) = ∑(3, 5, 6,7) 𝐹𝐹2 (𝐴𝐴, 𝐵𝐵 , 𝐶𝐶 ) = ∑(0, 2, 4, 7) Implement the circuit with a PLA having three inputs, four product terms and two outputs. Explain the salient features of ASM chart. Draw the ASM chart for weighing machine and explain.

8 (a) (b)

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𝑦𝑦. 0 2. Implement the following using PLA: 𝐴𝐴(𝑥𝑥 . (ii) (𝐴𝐴̅ + 𝐶𝐶 ) (𝐴𝐴̅ + 𝐶𝐶̅ ) (A+B+𝐶𝐶̅ 𝐷𝐷). (ii) (26153. 1 4 7. 4. 0 1. (iv) 𝑥𝑥𝑥𝑥 + 𝑥𝑥 (𝑤𝑤𝑤𝑤 − 𝑤𝑤𝑧𝑧̅). 0 5 4. 𝑧𝑧) = ∑𝑚𝑚 (2. 𝐵𝐵(𝑥𝑥 . 011)2 to decimal. If 𝑛𝑛 = 1 generate a conditional operation and go from 𝑇𝑇1 𝑡𝑡𝑡𝑡 𝑇𝑇2 . 𝑦𝑦. 2. 𝑧𝑧) = 𝑥𝑥𝑦𝑦 �𝑧𝑧 + 𝑥𝑥̅ 𝑦𝑦 �𝑧𝑧 + 𝑤𝑤 �𝑥𝑥𝑥𝑥 + 𝑤𝑤𝑥𝑥̅ 𝑦𝑦 + 𝑤𝑤𝑤𝑤𝑤𝑤. Obtain the 15-bit hamming code word for the 11-bit data word 11001001010. 1. 𝑧𝑧) =∑(0. 𝑥𝑥 . Simplify the Boolean function using K-map. 6). Implement the full adder with a decoder and two OR-gates. 𝐹𝐹 (𝐴𝐴. 1 6. 7406)8 to binary (iii) (1001001. 13. Use D-flip flops. Design a converter with the following repeated binary sequence: 0. PS NS Z J1 J2 1 2. F2)16 to octal. 1. 1 1 oo 1 o o 6 (a) (b) 7 (a) (b) 8 (a) (b) o 1 Design a 4-bit binary synchronous counter with D-flip flop. 5. 𝐶𝐶 (𝑥𝑥 . 𝐵𝐵 . 1 7 4. 𝑦𝑦. 0 1. 1 6 5. 1 4. 6. Simplify the following Boolean expressions to minimum number of literals: � + 𝐴𝐴𝐴𝐴𝐴𝐴 + 𝐴𝐴 𝐶𝐶̅ . 𝐶𝐶 . 0 4.Code: 9A04306 B. Max Marks: 70 2 (a) (b) 3 (a) (b) 4 (a) (b) Reduce the following function using K-map in SOP form 𝐹𝐹 (𝑤𝑤 . control goes from state 𝑇𝑇1 to state 𝑇𝑇2 . 4. 14). 2. 1 Design a sequential circuit specified by the state diagram in figure using JK-flip flop. 𝑥𝑥 . 1 2 7. (iii) (������� (i) 𝐴𝐴̅ 𝐵𝐵 𝑥𝑥 + 𝑦𝑦) (𝑥𝑥̅ + 𝑦𝑦 �). Convert the following numbers: (i) (2 C6B.7). 5 (a) (b) Determine a minimal state table equivalent to the state table given below. 6). Obtain the ASM chart for the following state transactions if 𝑥𝑥 = 0. 0 3 4. 𝐷𝐷) = 𝐴𝐴̅ 𝐵𝐵 Design and implement a 4-bit combinational circuit of binary to gray code. 4. 𝑦𝑦. 1. 𝑧𝑧) = ∑𝑚𝑚(1. 9. 𝑧𝑧) = ∑𝑚𝑚 (0. How do you indicate moore outputs and Melay outputs in an ASM? ***** . � 𝐶𝐶̅ + 𝐵𝐵 � 𝐶𝐶𝐷𝐷 � + 𝐴𝐴̅ 𝐵𝐵 𝐶𝐶 𝐷𝐷 � + 𝐴𝐴𝐵𝐵 � 𝐶𝐶̅ Implement with NAND gates. 𝑦𝑦. 0 1. 8.Tech II Year I Semester (R09) Regular & Supplementary Examinations December/January 2013/14 2 DIGITAL LOGIC DESIGN (Computer Science and Engineering) Time: 3 hours Answer any FIVE questions All questions carry equal marks ***** 1 (a) (b) Subtract (111001)2 from (101011) using i’s complement. 6. Simplify the following Boolean function in SOP form 𝐹𝐹 (𝑤𝑤 . 12. 2.

6). A sequential circuit with two D-flip flops. 𝑌𝑌 = 𝐴𝐴̅ 𝐵𝐵 Construct a 5 – to – 32 line decoder with four 3-to-8 line decoders with enable and a 2 – to -4 line decoder. 𝑦𝑦. Show that a BCD ripple counter can be constructed using a 4-bit binary ripple converter with asynchronous clear and a NAND gate that detects the occurrence of count 1010. M = 0 down counting: The circuit should generate an output ‘1’ whenever count becomes minimum or maximum. Draw the corresponding state diagram. 𝑧𝑧) = 𝜋𝜋 (4. 5. 𝑧𝑧) = ∑(0. z) = ∑(1. Design a serial 2’s complementor with a shift register and a flip –flop. Tabulate the PLA programming table for the four Boolean functions listed in above problem. 6. 𝑦𝑦. 6. 𝑧𝑧) = ∑(1. 4. 8. C. 4. 7). 3. 2. 8. 12. 0101)2 (ii) (16. A and B. 5. State and prove the following theorems: (i) Demorgan’s theorem. 9. Perform (15)10. two inputs 𝑥𝑥 𝑎𝑎𝑎𝑎𝑎𝑎 𝑦𝑦. 4. 7. 𝑧𝑧) = ∑(2. 6. (ii) Conserver theorem. Find the 16’s complements of AF3B and convert AF3B to binary. 3 (a) (b) 4 (a) (b) 5 (a) (b) (c) 6 (a) (b) 7 (a) (b) 8 (a) (b) ***** . B. Draw the ASM chart for weighing machine and explain. Reduce the following function using K-map in SOP form. 6). 6. 5)16 (iii) (26. 3.(28)10 in complement representation. 5. M= 1: up counting . Considering now the ROM as a memory. 14). y. (iii) Shanon’s expansion and reduction theorem. 11. 3. 𝑥𝑥. y.Tech II Year I Semester (R09) Regular & Supplementary Examinations December/January 2013/14 Time: 3 hours Answer any FIVE questions All questions carry equal marks ***** 1 (a) (b) (c) 2 (a) (b) Convert the following numbers in decimal: (i) (10110. 𝑦𝑦. 12) + 𝑑𝑑 (1. 9. Draw the logic diagram of the circuit. 𝐷𝐷 (𝑥𝑥. 14) implement with NOR gates. List the state table for the sequential circuit. 2. specify the memory contents at addresses 1 and 4. The binary number is shifted out from one side and its 2’s complement shifted in to the other side of the shift register. 𝑧𝑧) = ∑(1. Simplify the following Boolean function for minimal POS form using K-map: 𝐹𝐹 (𝑤𝑤. 3. 7). 1. Use block diagrams for the components.Code: 9A04306 3 DIGITAL LOGIC DESIGN (Computer Science and Engineering) B. 2. F(w. 7) (ii) F (A. Realize the following Boolean expression using a 8 × 1 multiplexer: � 𝐶𝐶 + 𝐴𝐴̅ 𝐵𝐵 𝐶𝐶̅ + 𝐴𝐴 𝐵𝐵 � 𝐶𝐶 + 𝐴𝐴𝐴𝐴𝐴𝐴 . 2. 13. Max Marks: 70 Convert the following to the other canonical form: (i) F(x. 2. 𝑦𝑦. D) = 𝜋𝜋(0. x. 1.12). 𝐵𝐵(𝑥𝑥 . Tabulate the truth table for an 8 × 4 ROM that implements the Boolean functions: 𝐴𝐴 (𝑥𝑥. 1. 𝐶𝐶 (𝑥𝑥. and one output z. 𝑦𝑦. Draw an ASM chart and stage table for a 2-bit up-down can be having mode control input. 24)8. is specified by the following next state and output equations: 𝐴𝐴 (𝑡𝑡 + 1) = 𝑥𝑥1 𝑦𝑦 + 𝑥𝑥𝑥𝑥 𝐵𝐵(𝑡𝑡 + 1) = 𝑥𝑥1 𝐵𝐵 + 𝑥𝑥𝑥𝑥 𝑧𝑧 = 𝐵𝐵. z) = ∑(0.

Tech II Year I Semester (R09) Regular & Supplementary Examinations December/January 2013/14 Time: 3 hours Answer any FIVE questions All questions carry equal marks ***** 1 (a) Max Marks: 70 (b) The state of a 12-bit register is 100010010111. ***** . 7. (iii) Three decimal digits in the 8421 code. 𝐶𝐶 . A sequential circuit has two JK flip-flops A and B two inputs 𝑥𝑥 𝑎𝑎𝑎𝑎𝑎𝑎 𝑦𝑦. 𝐵𝐵 . B. Derive the state equations for A and B. C. What is its content if it represents: (i) Three decimal digits in BCD. Obtain ASM chart for the following state transitions if 𝑥𝑥 = 0. Control goes from state 𝑇𝑇1 to state 𝑇𝑇2 . Use JK-flip flops. 6. 15) + ∑d (0. 4). 3. 3. Convert decimal 9126 to both BCD and ASCII codes. Tabulate the state table. 1. Draw the logic diagram of the circuit. The flip flops input equations and circuit output equation are 𝐽𝐽𝐴𝐴 = 𝐵𝐵𝐵𝐵 +𝐵𝐵1 𝑌𝑌1 𝐾𝐾𝐴𝐴 = 𝐵𝐵1 𝑥𝑥 𝑌𝑌1 1 𝐽𝐽𝐵𝐵 = 𝐴𝐴 𝑥𝑥 𝐾𝐾𝐵𝐵 = 𝐴𝐴 + 𝑥𝑥𝑌𝑌1 . 2. 4). Design and implement a 4-bit combinational circuit of binary to gray code. 4. 11. 5. (ii) Three decimal digits in the excess -3 code. The circuit accepts a 3. What is the difference between serial and parallel transfer? Explain how to converter serial data to parallel and parallel data to serial. What type of register is needed? Design a combinational circuit using a ROM. 7.bit number and generates an output binary number equal to the square of the input number. (a) (b) (c) 6 (a) (b) 7 (a) (b) 8 (a) (b) Explain how the ASM chart differs from a conventional flow chart. Implement the full adder with a decoder and two OR-gates. � 𝐶𝐶 + 𝐴𝐴𝐵𝐵 � 𝐷𝐷 + 𝐴𝐴 � (ii) 𝐴𝐴 � 𝐶𝐶̅ + 𝐴𝐴𝐴𝐴𝐶𝐶̅ + 𝐴𝐴 � 𝐶𝐶 (i) A𝐵𝐵 2 (a) (b) 3 (a) (b) 4 (a) (b) 5 Simplify the following Boolean function by using a Quline-McCluskey method: 𝐹𝐹 (𝐴𝐴. 𝐶𝐶 ) = ∑(0. 1. Implement the following two Boolean functions with a PLA: 𝐹𝐹1 (𝐴𝐴. 5. 12. 𝐵𝐵 . 2. 8. if 𝑛𝑛 = 1 generate a conditional operation and go from 𝑇𝑇1 𝑡𝑡𝑡𝑡 𝑇𝑇2 . 3. 𝐵𝐵 . Show the difference in interpretation using one example. Find the reduced SOP form of the following function F (A. Given the Boolean function 𝐹𝐹 = 𝑥𝑥𝑥𝑥 + 𝑥𝑥 1 𝑦𝑦1 + 𝑦𝑦1 𝑧𝑧: (i) Implement it with AND. 7). D) = ∑m (1.Code: 9A04306 4 DIGITAL LOGIC DESIGN (Computer Science and Engineering) B. an add parity bit is to be appended at the left. Design a counter with the following repeated binary sequence: 0. 𝐹𝐹2 (𝐴𝐴. For ASCII. 𝐷𝐷) = ∑𝑚𝑚 (0. 6. 𝐶𝐶 ) = ∑(0. Obtain the dual of the following Boolean expressions: � 𝐵𝐵 � 𝐵𝐵 � 𝐵𝐵 � 𝐷𝐷 . 13). OR and inverter gates. (iv) A binary number. (iii) Implement it with AND and inverter gates. (ii) Implement it with OR and inverter gates. and one output ‘2’. 10. 6. 2. 2.