Digital Integrated Circuits

A Design Perspective
Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic

Arithmetic Circuits
January, 2003
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EE141 Integrated Circuits2nd © Digital

Arithmetic Circuits

A Generic Digital Processor

MEM ORY INPUT-OUTPUT

CONTROL

DATAPATH

EE141 Integrated Circuits2nd © Digital

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Arithmetic Circuits

Building Blocks for Digital Architectures
Arithmetic unit - Bit-sliced datapath (adder, multiplier, shifter, comparator, etc.) Memory - RAM, ROM, Buffers, Shift registers Control - Finite state machine (PLA, random logic.) - Counters Interconnect - Switches - Arbiters - Bus
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Arithmetic Circuits

An Intel Microprocessor 9-1 Mux 5-1 Mux a CARRYGEN SUMSEL g64 ck1 REG node1 sum sumb to Cache 9-1 Mux 2-1 Mux b SUMGEN + LU LU : Logical Unit s0 s1 1000um Itanium has 6 integer execution units like this EE141 Integrated Circuits2nd © Digital 4 Arithmetic Circuits .

Bit-Sliced Design Control Bit 3 Multiplexer Data-In Register Adder Bit 2 Bit 1 Bit 0 Shifter Data-Out 5 Tile identical processing elements EE141 Integrated Circuits2nd © Digital Arithmetic Circuits .

Bit-Sliced Datapath From register files / Cache / Bypass Multiplexers Shifter Adder stage 1 Wiring Adder stage 2 Wiring Loopback Bus Loopback Bus Loopback Bus EE141 Integrated Circuits2nd © Digital Bit slice 63 Bit slice 2 Bit slice 0 Bit slice 1 Adder stage 3 Sum Select To register files / Cache 6 Arithmetic Circuits .

Orton.Itanium Integer Datapath EE141 Integrated Circuits © Digital Fetzer. ISSCC’02 2nd 7 Arithmetic Circuits .

Adders EE141 Integrated Circuits2nd © Digital 8 Arithmetic Circuits .

Full-Adder A Cin B Cout Full adder Sum EE141 Integrated Circuits2nd © Digital 9 Arithmetic Circuits .

The Binary Adder A Cin B Cout Full adder Sum S = A ⊕ B ⊕ Ci = ABC i + ABC i + ABCi + ABCi C o = AB + BCi + ACi EE141 Integrated Circuits2nd © Digital 10 Arithmetic Circuits .

Express Sum and Carry as a function of P. G. B Generate (G) = AB Propagate (P) = A ⊕ B Delete = A B Can also derive expressions for S and Co based on D and P Note that we will be sometimes using an alternate definition for Propagate (P) = A + B EE141 Integrated Circuits2nd © Digital 11 Arithmetic Circuits . D Define 3 new variable which ONLY depend on A.

Complimentary Static CMOS Full Adder VDD VDD A B A B Ci A X A Ci A B B VDD A Co B Ci A B VDD Ci A B Ci S Ci B 28 Transistors EE141 Integrated Circuits2nd © Digital 12 Arithmetic Circuits .

A Better Structure: The Mirror Adder VDD VDD A "0"-Propagate Ci "1"-Propagate A B A Generate B A B Ci A B B B Kill A Co Ci S Ci A B VDD Ci A B 24 transistors EE141 Integrated Circuits2nd © Digital 13 Arithmetic Circuits .

Mirror Adder Stick Diagram VDD A B Ci Co B A Ci Co Ci A B S GND EE141 Integrated Circuits2nd © Digital 14 Arithmetic Circuits .

• When laying out the cell. two internal gate capacitances. the most critical issue is the minimization of the capacitance at node Co. • Only the transistors in the carry stage have to be optimized for optimal speed. and six gate capacitances in the connecting adder cell . The reduction of the diffusion capacitances is particularly important. All transistors in the sum stage can be minimal size. EE141 Integrated Circuits2nd © Digital 15 Arithmetic Circuits . • The capacitance at node Co is composed of four diffusion capacitances. A maximum of two series transistors can be observed in the carrygeneration circuitry.The Mirror Adder • The NMOS and PMOS chains are completely symmetrical. • The transistors connected to Ci are placed closest to the output.

Transmission Gate Full Adder P VDD A A B VDD Ci Ci A Setup A P A P B Ci P Ci P A P Ci P Co Carry Generation VDD S Sum Generation VDD EE141 Integrated Circuits2nd © Digital 16 Arithmetic Circuits .

One-phase dynamic CMOS adder EE141 Integrated Circuits2nd © Digital 17 Arithmetic Circuits .

One-phase dynamic CMOS adder EE141 Integrated Circuits2nd © Digital 18 Arithmetic Circuits .

One-phase dynamic CMOS adder EE141 Integrated Circuits2nd © Digital 19 Arithmetic Circuits .

3 S0 S1 S2 S3 Worst case delay linear with the number of bits td = O(N) tadder = (N-1)tcarry + tsum Goal: Make the fastest possible carry path circuit EE141 Integrated Circuits2nd © Digital 20 Arithmetic Circuits .0 FA B0 Co.1) FA A1 B1 Co.The Ripple-Carry Adder A0 Ci.1 FA A2 B2 Co.0 (= Ci.2 FA A3 B3 Co.

Inversion Property A B A B Ci FA Co Ci FA Co S S EE141 Integrated Circuits2nd © Digital 21 Arithmetic Circuits .

0 FA B0 Co.3 S0 S1 S2 S3 Exploit Inversion Property EE141 Integrated Circuits2nd © Digital 22 Arithmetic Circuits .Minimize Critical Path by Reducing Inverting Stages Even cell A0 Ci.1 FA A2 B2 Co.2 FA Odd cell A3 B3 Co.0 FA A1 B1 Co.

Carry Look-Ahead Adders EE141 Integrated Circuits2nd © Digital 23 Arithmetic Circuits .

Carry-Lookahead Adders EE141 Integrated Circuits2nd © Digital 24 Arithmetic Circuits .

Carry-Lookahead Adders EE141 Integrated Circuits2nd © Digital 25 Arithmetic Circuits .

k = Gk + Pk (Gk – 1 + Pk – 1 Co .3 P0 P1 P2 P3 EE141 Integrated Circuits2nd © Digital 26 Arithmetic Circuits . 0 ) ) ) Ci. k = Gk + Pk ( Gk – 1 + P k – 1( … + P1 ( G0 + P0 Ci . k – 2 ) VDD G3 G2 All the way: C o.Look-Ahead: Topology Expanding Lookahead equations: C o.0 G1 G0 Co.

Manchester Carry Chain VDD VDD Pi Gi Ci Di Pi Co Ci Pi φ Co Gi φ EE141 Integrated Circuits2nd © Digital 27 Arithmetic Circuits .

Manchester Carry Chain VDD φ P0 P1 P2 P3 C3 Ci.0 G0 φ G1 G2 G3 C0 C1 C2 C3 EE141 Integrated Circuits2nd © Digital 28 Arithmetic Circuits .

Manchester Carry Chain Stick Diagram Propagate/Generate Row VDD Pi Ci .1 GND Inverter/Sum Row Gi φ Ci Pi + 1 Gi + 1 φ Ci + 1 EE141 Integrated Circuits2nd © Digital 29 Arithmetic Circuits .

1 P2 G2 Co. else “kill” or “generate”.0 C o.2 P3 G3 Co.Carry-Bypass Adder P0 Ci.0 G1 C o.2 P3 G3 BP=P oP1 P2 P3 Multiplexer FA FA FA FA Co.0 P0 G1 C o. 30 EE141 Integrated Circuits2nd © Digital Arithmetic Circuits .1 P2 G2 C o.0 P0 G1 Co.3 Also called Carry-Skip FA FA FA FA P0 G1 Ci.3 Idea: If (P0 and P1 and P2 and P3 = 1) then Co3 = C0.

Carry-Bypass Adder (cont.) Bit 0–3 Setup tsetup Bit 4–7 Setup tbypass Bit 8–11 Setup Bit 12–15 Setup Carry propagation Carry propagation Carry propagation Carry propagation Sum M bits Sum Sum tsum Sum tadder = tsetup + Mtcarry + (N/M –1)tbypass + (M – 1)tcarry + tsum EE141 Integrated Circuits2nd © Digital 31 Arithmetic Circuits .

Carry Ripple versus Carry Bypass tp ripple adder bypass adder 4.8 N 32 EE141 Integrated Circuits2nd © Digital Arithmetic Circuits ..

Carry-Select Adder Setup P.k-1 Multiplexer Carry Vector C o.k+ 3 Sum Generation EE141 Integrated Circuits2nd © Digital 33 Arithmetic Circuits .G "0" "0" Carry Propagation "1" "1" Carry Propagation Co.

Carry Select Adder: Critical Path Bit 0–3 Setup Bit 4–7 Setup Bit 8–11 Setup Bit 12–15 Setup 0 0-Carry 0 0-Carry 0 0-Carry 0 0-Carry 1 1-Carry 1 1-Carry 1 1-Carry 1 1-Carry Ci.15 Sum Generation S0–3 Sum Generation S4–7 Sum Generation S8–11 Sum Generation S12–15 EE141 Integrated Circuits2nd © Digital 34 Arithmetic Circuits .11 Multiplexer Co.7 Multiplexer Co.3 Multiplexer Co.0 Multiplexer Co.

Linear Carry Select Bit 0-3 Bit 4-7 Bit 8-11 Bit 12-15 Setup (1) "0" (1) "1" Carry "1" (5) (5) (6) Multiplexer Ci.0 Sum Generation S0-3 Sum Generation S 4 -7 Sum Generation S8-11 Multiplexer "1" (5) (7) Multiplexer "1" Carry "1" (5) (8) Multiplexer (9) Sum Generation S 1 2-15 (10) "1" Carry "1" (5) "1" Carry "0" Carry "0" "0" Carry "0" "0" Carry "0" "0" Carry Setup Setup Setup EE141 Integrated Circuits2nd © Digital 35 Arithmetic Circuits .

0 Sum Generation S0-1 Sum Generation S2-4 Sum Generation S5-8 Sum Generation S9-13 Sum S14-19 (9) Multiplexer "1" Carry "1" (4) (5) Multiplexer "1" (5) (6) Multiplexer "1" Carry "1" (6) (7) Mux (8) (7) "1" Carry "0" Carry "0" "0" Carry "0" "0" Carry "0" "0" Carry Setup Setup Setup EE141 Integrated Circuits2nd © Digital 36 Arithmetic Circuits .Square Root Carry Select Bit 0-1 Bit 2-4 Bit 5-8 Bit 9-13 Bit 14-19 Setup (1) "0" (1) "1" (3) "1" Carry (3) (4) Multiplexer Ci.

Comparison 50 40 tp (in unit delays) Ripple adder 30 Linear select 20 10 0 Square root select 0 20 N 40 60 EE141 Integrated Circuits2nd © Digital 37 Arithmetic Circuits .Adder Delays .

“O” Operator Definizione EE141 Integrated Circuits2nd © Digital 38 Arithmetic Circuits .

Properties of the “O” operator EE141 Integrated Circuits2nd © Digital 39 Arithmetic Circuits .

Properties of the “O” operator EE141 Integrated Circuits2nd © Digital 40 Arithmetic Circuits .

Group Generate and Propagate EE141 Integrated Circuits2nd © Digital 41 Arithmetic Circuits .

Group Generate and Propagate EE141 Integrated Circuits2nd © Digital 42 Arithmetic Circuits .

Group Generate and Propagate EE141 Integrated Circuits2nd © Digital 43 Arithmetic Circuits .

k – 1 ) = Gk + P k Co .Basic Idea A0. BN-1 Ci. k = f (A k.Look-Ahead .1 P1 Ci. B0 A1. B k. B1 ••• AN-1.0 P0 Ci. N-1 ••• PN-1 S0 S1 SN-1 C o. k – 1 44 EE141 Integrated Circuits2nd © Digital Arithmetic Circuits . Co .

Logarithmic Look-Ahead Adder A0 A1 A2 A0 A1 A2 A3 F A4 A5 A6 A7 A3 A4 A5 A6 A7 F tp∼ N tp∼ log2(N) EE141 Integrated Circuits2nd © Digital 45 Arithmetic Circuits .

Brent-Kung BLC adder EE141 Integrated Circuits2nd © Digital 46 Arithmetic Circuits .

Folding of the inverse tree EE141 Integrated Circuits2nd © Digital 47 Arithmetic Circuits .

Folding the inverse tree EE141 Integrated Circuits2nd © Digital 48 Arithmetic Circuits .

Dense tree with minimum fan-out EE141 Integrated Circuits2nd © Digital 49 Arithmetic Circuits .

Dense tree with simple connections EE141 Integrated Circuits2nd © Digital 50 Arithmetic Circuits .

0 ) = G 2:1 + P2:1 C o. 0 = G0 + P0 Ci . 0 C o. 0 = ( G 2 + P2 G1) + ( P2 P1 ) ( G 0 + P0 Ci . EE141 Integrated Circuits2nd © Digital 51 Arithmetic Circuits . 2 = G2 + P2 G 1 + P2 P1 G0 + P2 P1 P0 C i. 1 = G1 + P1 G 0 + P1 P0 Ci. 0 Can continue building the tree hierarchically.Carry Lookahead Trees Co . 0 C o.

B5) (A6. B7) (A8. B13) (A14. B8) EE141 Integrated Circuits2nd © Digital Tree Adders 16-bit radix-2 Kogge-Stone tree 52 Arithmetic Circuits . B4) (A5. B6) (A7. B1) (A2. B10) (A11. B14) (A15. B3) (A4. B12) (A13. B2) (A3. B9) (A10. B0) S0 S1 S2 S3 S4 S5 S6 S7 S8 (A9.(A0. B11) (A12. B15) S9 S10 S11 S12 S13 S14 S15 (A1.

b 15) S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S 10 S 11 S 12 S 13 S 14 S 15 EE141 Integrated Circuits2nd © Digital Tree Adders 16-bit radix-4 Kogge-Stone Tree 53 Arithmetic Circuits . b 11) (a 12. b 13) (a 14. b 6) (a 7. b 4) (a 5. b 1) (a 2. b 14) (a 15. b 2) (a 3. b 0) (a 1. b 3) (a 4. b 10) (a 11. b 7) (a 8. b 9) (a 10. b 12) (a 13. b 8) (a 9.(a 0. b 5) (a 6.

b 9) (a 10. b 12) (a 13. b 14) (a 15. b 5) (a 6. b 11) (a 12. b 8) EE141 Integrated Circuits2nd © Digital S 10 S 11 S 12 S 13 S 14 S 15 Sparse Trees 16-bit radix-2 sparse tree with sparseness of 2 54 Arithmetic Circuits . b 15) S9 (a 1. b 3) (a 4. b 6) (a 7.(a 0. b 4) (a 5. b 1) (a 2. b 10) (a 11. b 0) S0 S1 S2 S3 S4 S5 S6 S7 S8 (a 9. b 2) (a 3. b 13) (a 14. b 7) (a 8.

B2) (A3. B11) (A12.(A0. B7) (A8. B0) (A1. B5) (A6. B4) (A5. B13) (A14. B1) (A2. B6) (A7. B9) (A10. B3) (A4. B8) (A9. B14) (A15. B12) (A13. B15) S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 EE141 Integrated Circuits2nd © Digital Tree Adders Brent-Kung Tree 55 Arithmetic Circuits . B10) (A11.

Example: Domino Adder VDD VDD Clk Gi = aibi Clk P i = a i + bi ai ai bi bi Clk Clk Propagate Generate EE141 Integrated Circuits2nd © Digital 56 Arithmetic Circuits .

Example: Domino Adder VDD VDD Clkk Clkk Pi:i-2k+1 Gi:i-2k+1 Pi:i-k+1 Pi:i-k+1 Gi:i-k+1 Pi-k:i-2k+1 Gi-k:i-2k+1 Propagate Generate EE141 Integrated Circuits2nd © Digital 57 Arithmetic Circuits .

Example: Domino Sum VDD Clk Clkd Sum Gi:0 VDD Keeper Clk Si0 Clkd Clk Gi:0 Si1 Clk EE141 Integrated Circuits2nd © Digital 58 Arithmetic Circuits .

Adders – Summary EE141 Integrated Circuits2nd © Digital 59 Arithmetic Circuits .

Multipliers EE141 Integrated Circuits2nd © Digital 60 Arithmetic Circuits .

The Binary Multiplication EE141 Integrated Circuits2nd © Digital 61 Arithmetic Circuits .

The Binary Multiplication EE141 Integrated Circuits2nd © Digital 62 Arithmetic Circuits .

The Binary Multiplication 1 0 1 0 1 0 x 1 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 + 1 0 1 0 1 0 1 1 1 0 0 1 1 1 0 Result 63 Multiplicand Multiplier Partial products EE141 Integrated Circuits2nd © Digital Arithmetic Circuits .

The Array Multiplier X3 X3 HA X3 FA X3 FA Z7 Z6 X2 FA Z5 X2 FA X1 FA Z4 X2 FA X1 FA X0 HA Z3 Y3 X2 X1 FA X0 HA Z2 Y2 X1 X0 HA Z1 X0 Y1 Z0 Y0 EE141 Integrated Circuits2nd © Digital 64 Arithmetic Circuits .

The MxN Array Multiplier — Critical Path HA FA FA HA FA FA FA HA Critical Path 1 Critical Path 2 FA FA FA HA Critical Path 1 & 2 EE141 Integrated Circuits2nd © Digital 65 Arithmetic Circuits .

Carry-Save Multiplier HA HA HA HA HA FA FA FA HA FA FA FA HA FA FA HA Vector Merging Adder EE141 Integrated Circuits2nd © Digital 66 Arithmetic Circuits .

( ) C S C S C S C S Z7 Z6 Z5 Z4 Z3 EE141 Integrated Circuits2nd © Digital 67 Arithmetic Circuits .Multiplier Floorplan X3 X2 X1 X0 Y0 Y1 HA Multiplier Cell C S C S C S C S Z0 FA Multiplier Cell Y2 C S C S C S C S Z1 Vector Merging Cell Y3 C S C S C S C S Z2 X and Y signals are broadcasted through the complete array.

Wallace-Tree Multiplier Partial products 6 5 4 3 2 1 0 First stage 6 5 4 3 2 1 0 Bit position (a) Second stage 6 5 4 3 2 1 0 (b) Final adder 6 5 4 3 2 1 0 FA (c) HA (d) EE141 Integrated Circuits2nd © Digital 68 Arithmetic Circuits .

Wallace-Tree Multiplier Partial products x3y3 x3y2 x2y3 x2y2 x3y1 x1y2 x3y0 x1y1 x2y0 x0y1 x1y3 x0y3 x2y1 x0y2 x1y0 x0y0 First stage HA HA Second stage FA FA FA FA Final adder z7 z6 z5 z4 z3 z2 z1 z0 EE141 Integrated Circuits2nd © Digital 69 Arithmetic Circuits .

Wallace-Tree Multiplier y0 y1 y2 Ci-1 y3 Ci FA y4 FA Ci FA y5 Ci FA C C S S FA Ci-1 Ci Ci-1 Ci-1 Ci Ci y 0 y 1 y2 y3 y4 y5 FA FA FA Ci-1 Ci-1 EE141 Integrated Circuits2nd © Digital 70 Arithmetic Circuits .

Performance EE141 Integrated Circuits2nd © Digital 71 Arithmetic Circuits .Wallace Tree Mult.

Wallace Tree Multiplier Complexity EE141 Integrated Circuits2nd © Digital 72 Arithmetic Circuits .

4:2 Adder EE141 Integrated Circuits2nd © Digital 73 Arithmetic Circuits .

Eight-input Tree EE141 Integrated Circuits2nd © Digital 74 Arithmetic Circuits .

Architectural comparison of multiplier solutions EE141 Integrated Circuits2nd © Digital 75 Arithmetic Circuits .

SPIM Architecture EE141 Integrated Circuits2nd © Digital 76 Arithmetic Circuits .

SPIM Pipe Timing EE141 Integrated Circuits2nd © Digital 77 Arithmetic Circuits .

SPIM Microphotograph EE141 Integrated Circuits2nd © Digital 78 Arithmetic Circuits .

SPIM clock generator circuit EE141 Integrated Circuits2nd © Digital 79 Arithmetic Circuits .

Binary Tree Multiplier Performance

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Binary Tree Multiplier Complexity

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Multipliers – Summary
• Optimization Goals Different Vs Binary Adder • Once Again: Identify Critical Path • Other possible techniques - Logarithmic versus Linear (Wallace Tree Mult) - Data encoding (Booth) - Pipelining FIRST GLIMPSE AT SYSTEM LEVEL OPTIMIZATION
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EE141 Integrated Circuits2nd © Digital

Arithmetic Circuits

Multipliers – Summary EE141 Integrated Circuits2nd © Digital 83 Arithmetic Circuits .

Booth encoding EE141 Integrated Circuits2nd © Digital 84 Arithmetic Circuits .

Booth encoding EE141 Integrated Circuits2nd © Digital 85 Arithmetic Circuits .

Tree Multiplier with Booth Encoding EE141 Integrated Circuits2nd © Digital 86 Arithmetic Circuits .

p. addition algorithm Exponent comparison and swap (if needed) Mantissas’ aligment Addition Normalization of result Rounding of result EE141 Integrated Circuits2nd © Digital 87 Arithmetic Circuits .The f.

multiplication algorithm Mantissas’ multiplication Exponent addition Mantissa normalization and exponent adjusting (if needed) Rounding of result EE141 Integrated Circuits2nd © Digital 88 Arithmetic Circuits .The f.p.

Dividers EE141 Integrated Circuits2nd © Digital 89 Arithmetic Circuits .

Iterative Division (Newton-Raphson) EE141 Integrated Circuits2nd © Digital 90 Arithmetic Circuits .

Iterative Division (Newton-Raphson) EE141 Integrated Circuits2nd © Digital 91 Arithmetic Circuits .

Quadratic Convergence of the Newton Method EE141 Integrated Circuits2nd © Digital 92 Arithmetic Circuits .

Properties of the Newton Method Asymptotically quadratic convergence Correction of round-off errors Final multiplication by a generates a round-off problem incompatible with the Standard IEEE-754 EE141 Integrated Circuits2nd © Digital 93 Arithmetic Circuits .

Iterative Division (Goldschmidt) EE141 Integrated Circuits2nd © Digital 94 Arithmetic Circuits .

Iterative division (Goldschmidt) EE141 Integrated Circuits2nd © Digital 95 Arithmetic Circuits .

Iterative Division (Goldschmidt) The sequence of xn tends to a/b The convergence is quadratic In its present form. this method is affected by roud-off errors EE141 Integrated Circuits2nd © Digital 96 Arithmetic Circuits .

Modified Goldschmidt Algorithm (correction of round-off errors) EE141 Integrated Circuits2nd © Digital 97 Arithmetic Circuits .

The Link between the Newton-Raphson and Goldschmidt Methods

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The Link between the Newton-Raphson and Goldschmidt Methods

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Arithmetic Circuits

Comparison between Newton and Goldschmidt methods
The

Newton and Goldschmidt methods are essentially equivalent; Both methods exhibit an asymptotically quadratic convergence; Both methods are able to correct roundoff errors; The Goldschmidt methods directly computes the a/b ratio.
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Shifters EE141 Integrated Circuits2nd © Digital 101 Arithmetic Circuits .

The Binary Shifter Right nop Left Ai Bi Ai-1 Bi-1 Bit-Slice i . EE141 Integrated Circuits2nd © Digital 102 Arithmetic Circuits ...

The Barrel Shifter A3 B3 Sh1 A2 B2 Sh2 A1 B1 Sh3 A0 B0 : Data Wire : Control Wire Sh0 Sh1 Sh2 Sh3 Area Dominated by Wiring EE141 Integrated Circuits2nd © Digital 103 Arithmetic Circuits .

4x4 barrel shifter A3 A2 A1 A0 Sh0 Sh 1 S h2 Sh3 B uffer Widthbarrel ~ 2 pm M EE141 Integrated Circuits2nd © Digital 104 Arithmetic Circuits .

Logarithmic Shifter Sh1 Sh1 Sh2 Sh2 Sh4 Sh4 A3 B3 A2 B2 A1 B1 A0 B0 EE141 Integrated Circuits2nd © Digital 105 Arithmetic Circuits .

0-7 bit Logarithmic Shifter A 3 Out3 A 2 Out2 A 1 Out1 A 0 Out0 EE141 Integrated Circuits2nd © Digital 106 Arithmetic Circuits .

ALUs EE141 Integrated Circuits2nd © Digital 107 Arithmetic Circuits .

Two-bit MUX EE141 Integrated Circuits2nd © Digital 108 Arithmetic Circuits .

Two-bit MUX Truth Table EE141 Integrated Circuits2nd © Digital 109 Arithmetic Circuits .

Two-bit Selector Truth Table EE141 Integrated Circuits2nd © Digital 110 Arithmetic Circuits .

Carry-chain Truth Table EE141 Integrated Circuits2nd © Digital 111 Arithmetic Circuits .

ALU block diagram (Mead-Conway) EE141 Integrated Circuits2nd © Digital 112 Arithmetic Circuits .

ALU Operations EE141 Integrated Circuits2nd © Digital 113 Arithmetic Circuits .

ALU Operations EE141 Integrated Circuits2nd © Digital 114 Arithmetic Circuits .

ALU Operations EE141 Integrated Circuits2nd © Digital 115 Arithmetic Circuits .

ALU Operations EE141 Integrated Circuits2nd © Digital 116 Arithmetic Circuits .

ALU Operations EE141 Integrated Circuits2nd © Digital 117 Arithmetic Circuits .

MIPS-X Instruction Format EE141 Integrated Circuits2nd © Digital 118 Arithmetic Circuits .

Pipeline dependencies in MIPS-X

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Die Photo of MIPS-X

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MIPS-X Architecture

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MIPS-X Instruction Cache-miss timing EE141 Integrated Circuits2nd © Digital 122 Arithmetic Circuits .

MIPS-X Tag Memory EE141 Integrated Circuits2nd © Digital 123 Arithmetic Circuits .

MIPS-X Valid Store Array EE141 Integrated Circuits2nd © Digital 124 Arithmetic Circuits .

RAM Sense Amplifier EE141 Integrated Circuits2nd © Digital 125 Arithmetic Circuits .

CMOS Dual-port Register Cell EE141 Integrated Circuits2nd © Digital 126 Arithmetic Circuits .

Self-timed bit-line write circuit EE141 Integrated Circuits2nd © Digital 127 Arithmetic Circuits .

Register bypass logic EE141 Integrated Circuits2nd © Digital 128 Arithmetic Circuits .

Schematic of comparator circuit EE141 Integrated Circuits2nd © Digital 129 Arithmetic Circuits .

Squash FSM EE141 Integrated Circuits2nd © Digital 130 Arithmetic Circuits .

Cache-miss FSM EE141 Integrated Circuits2nd © Digital 131 Arithmetic Circuits .

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