Processing VLSI Signal Laboratory

KECE 463 VLSI Design and Experiment

Lecture 1
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Course Format
Lecturer : Prof. Jongsun Park
Email : jongsun@korea.ac.kr Office : Innovation Building () 716 B Phone : (02) 3290-4827

Teaching Assistant
Ju-seong Lee ( juseong_lee@korea.ac.kr) Office : Engineering Building Annex () 501 Phone : (02)3290-3669
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Course Format

Lecture
Time: Wednesday 2:00 ~ 6:00 PM Place: Convergence Building 109 LAB: Engineering Building II 313

English Class !
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Course Format
Text Book : Verilog HDL: A Guide to Digital Design
and Synthesis, 2nd Edition 2003 By Samir Palnitkar
Publisher: Prentice Hall PTR, ISBN: 0-13-044911-3

Grading : Have to do the HW and projects.

Homework : 35 % - must attend the class and LAB. Exam : 20 % Project 1 : 20 % Project 2 : 25 %
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Course Objectives
For the students to get to know

Current Digital VLSI Design Flow

For the students to get familiar with

Industry Grade Design Tools

For the students to have the concepts of

Delay, Area, Power of Digital Design

Prerequisite Course : Digital System
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Course Format
Lecture goes First Experiment will follow
LAB : Embedded system design LAB Engineering Building 313
CAD tools are available. (15 copies)

Homework and Projects are very important !

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What is the course about ? Why ?

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Electronic World

Courtesy of ISSCC 2013 Plenary KEEE 463

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Electronic World
What are the REAL basics ? Transistors, ICs (Integrated Circuits) Those are what this Electronic Circuit course is about.

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HISTORY : Transistor Size Scaling

From Electronics to Micro-electronics to Nano-electronics ... to ?
Electronics systems used vacuum tubes Electronics systems used Transistors 1940s Microelectronics systems 1960s

Nano 10-9

10-6

BJT

CMOS

vacuum tube

First Transistor, Bell Labs 1948

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The Integrated Circuit (IC)

An IC consists of interconnected electronic components in a single piece (chip) of semiconductor material.
In 1958, Jack S. Kilby (Texas Instruments) showed that it was possible to fabricate a simple IC in germanium. In 1959, Robert Noyce (Fairchild Semiconductor) demonstrated an IC made in silicon using SiO2 as the insulator and Al for the metallic interconnects.

The first planar IC (actual size: 0.06 in. diameter)

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Central Processing Units (CPU)

First Single Chip Processor with 2250 Transistors
Intel 8080 (1975, 4500 tr) 5 Mhz

Intel 8086 (1978, 29,000 tr) 10 Mhz

Intel 4004 (1971)

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From a Few, to Billions

The degree of integration has increased at an exponential pace over the past 40 years. IC performs very complex tasks. The number of devices on a chip doubles every ~18 months, for the same price.
1 Gb
1,000,000,000 100,000,000

Intel Pentium4 Processor

256M 64M 16M 4M 1M 256K 64K 16K 80286 8086 1K 4K 4044 8080 80386 Pentium III & IV PentiumII Pentium 80486

10,000,000 1,000,000 100,000 10,000 1,000

300mm Si wafer
Intel CPU DRAM

19 71 19 73 19 75 19 77 19 79 19 81 19 83 19 85 19 87 19 89 19 91 19 93 19 95 19 97 19 99 20 01 20 03

Moores Law still holds today.

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From a Few, to Billions

45nm 6-Core Xeon CPU

Courtesy of Intel

45nm processor (Nehalem)

8-Core Enterprise Xeon CPU

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Semiconductor Impacts

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Application Processor
PC era Smart Device

Courtesy of Samsung KEEE 463

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Application Processor Trend

Courtesy of ISSCC 2013 Plenary KEEE 463

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From ASIC, to SoC

ASIC SoC

Single Chip Digital & Analog Components

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Transistor Size Scaling

From Electronics to Micro-electronics to Nano-electronics ... to ?
Electronics systems used vacuum tubes Electronics systems used Transistors 1940s Microelectronics systems 1960s

Nano 10-9

10-6

BJT

CMOS

vacuum tube

First Transistor, Bell Labs 1948

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Process Technologies

< from ISSCC 2012 plenary >

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Process Technologies

< from ISSCC 2012 plenary >

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Tri-gate Advantages

[ on-current ]

[ off-current ]

< from ISSCC 2012 plenary >

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How can we design those chips ? Why HDL ?

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VLSI Design Methodology

Full Custom Design Method
Analog System Specification

C or Matlab

in1

in2 o

Schematic Optimization

High performance Digital Datapath Memory Register files

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Layout

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VLSI Design Methodology

Semi Custom Design Method
System Specification C or Matlab

HDL Description Most of Digital circuits

Verilog

Synthesis

Design Compiler P&R tool

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Place & Routing

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Semi-Custom Design !
VIT VIT VITRD ROM SBD DIRS CABLE
TPS CE
DTL

CE

DIRS

Digital TV Baseband Processor

SBD DIRS

CFE

DTL DTL

SPD PE
SPD

DTL

MDT
CFE MDT

SFT FFT ROM

SIF MD
DAC TEST

Memory Wrapper

PAL FFT Memory

Uanalog

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KEEE 485:VLSI Design & Experiment

Learn about Semi-Custom Design Methodology
verilog
System Specification
For each K loop if ( Ni is the smallest) Decrease Ni by end if Restore Ni End For

HDL Description

Synthesis

Place & Routing

always @ (posedge clk ) begin b <= a; c <= b; end

D
Q

No Timing No Clock

Clock Latency

Area Power Consumption

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What is Gooood Design?

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Design Issue
Chip Area = > Money $$
Fabrication cost / chip Smaller System

300mm Si wafer
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Trend - Frequency in Microprocessor

10000 1000 Frequency (Mhz) 100

Doubles every 2 years

P6 Pentium proc

486
10 1

8085

8086 286

386

Courtesy, Intel 0.1 1970

8080 8008 4004

1980 Year 1990 2000 2010

Lead Microprocessors frequency doubles every 2 years

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Design Issue
Power Consumption
Battery Life
Power density (W/cm2)

System Reliability (System down ?)

Year

Source : Intel
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Design Issue
To reduce Power Consumption

Thermal gradient Simulation

Low Power VLSI Design is required

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VLSI Design Why ? : Summary

Transistor size, Integrated Circuit
Transistor size scale down Micro > Nano Integration Density increases Billions of Transistors

Design Methodology ?
Full Custom, Semi-Custom Most of Chip area Semi Custom Design Flow (need to learn before graduations)

VLSI Design Issues Area , Power Consumption

SoC trends
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Prerequisites ?
Digital Systems (KEEE 207)
in1 o in2

Digital systems gates

D
Q

delay area power

D Q
clk

Not a prerequisites but helpful

Electronic Circuits I
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BJT CMOS
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Things to remember for Verilog Design

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Basic Gates
Prerequisites
in1 o in2

D Q
clk

NAND NOR INV MUX XOR DFF FADD HADD AND OR

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KEEE 485:VLSI Design & Experiment

Learn about Semi-Custom Design Methodology
verilog
System Specification
For each K loop if ( Ni is the smallest) Decrease Ni by end if Restore Ni End For

HDL Description

Synthesis

Place & Routing

always @ (posedge clk ) begin b <= a; c <= b; end

D
Q

No Timing No Clock

Clock Latency

Area Power Consumption

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RULE # 1
When you design Verilog, ALWAYS think about what is the HARDWARE is going to be ? <verilog example 1> always @( ) begin if (s == 1) out = a ; else out = b; end

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Example 2
ALWAYS Think about HARDWARE !
<verilog example 2> always @( ) begin if (s == 1) out = a ; else out = 0; end

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Example 3
ALWAYS Think about HARDWARE !
<verilog example 3> always @(posedge clk) begin b <= a; c <= d; end

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Example 4
ALWAYS Think about HARDWARE !
<verilog example 4> always @(posedge clk) begin if (s == 1) out <= in; else out <= out; end

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RULE # 2
When you design Verilog, ALWAYS draw Timing Diagram
<verilog example 1> always @(posedge clk ) begin count <= count + 1 ; end <verilog example 2> always @(negedge clk ) begin count <= count + 1 ; end

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Example 5
<verilog example 3> always @(posedge clk ) begin count <= count + 1 ; end always @( .. ) begin if (count == 3) c = a + b ; else c = 0; end
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Verilog Coding Tips : Summary

When you design Verilog,

1. ALWAYS Think about the HARDWARE ! 2. Draw the Timing Diagram
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