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# Sequential Circuits

Logic circuits can be divided into types i) Combinational logic circuit ii) Sequential logic circuit As we know the combinational logic circuit operates on its inputs to produce various outputs, but in sequential logic circuit the outputs of the memory elements are given to the inputs of combinational logic circuit as shown in below fig. Inputs Combinational circuit Memory Element outputs

Feedback path

(Sequential Circuit) Difference between Combinational logic circuit and Sequential logic circuit S.No Parameters Combinational logic circuit 1. Definition A circuit whose output is dependent only on the inputs at that instant or the circuit that does not contain any memory element. 2. Speed faster speed because all inputs are applied simultaneously. 3. Design Sequential logic circuit A circuit whose output depends not only on the present input but also on the past history of the I/Ps or a circuit that contains at least one memory element. slower because it has secondary I/Ps which are applied after a delay. Easy to design because large Harder to design but require less number of hardware equipments hardware. and large circuits are used. No need of memory element Memory element is needed.

4. 5.

Memory elements Flexibility Designer has less flexibility since more flexible because output the output depends only on the depends on both present input present inputs. and past output. Cost Behavior More expensive The behavior is defined by the set of output function only. Cheaper circuit The behavior is defined by the Set of input function and next state function.

6. 7.

The binary external inputs and present state (past output) of memory elements determine the binary value of the output circuit. They also determine the condition for changing the state in the memory elements. Thus the next state of the memory elements is a function of the external inputs and the present state. The sequential circuit is defined by two ways 1) Synchronous sequential circuit 2) Asynchronous sequential circuit Difference between Synchronous sequential circuit and Asynchronous sequential circuit S.N. Parameters Synchronous sequential circuit Asynchronous sequential circuit 1. Definition In which, circuit can effect the In which, circuit depends upon memory element only at discrete the order in which the inputs instant of time and these are also change and the state of the circuit called as clocked sequential can be affected at any instant of circuit. The input signals can time. affect the memory elements with the activation of clock. 2. Speed The maximum speed depends on Because of absence of clock, it the time delays involved can operate faster than synchronous circuit. 3. Design Easier to design but require less Harder to design because large hardware. number of hardware equipments and large circuits are used. 4. Memory Here the memory elements are Here the gates are used elements clocked flip-flops. 5. Flexibility Designer has more flexibility Designer has less flexibility because small circuit because of large circuit. 6. Cost Cheaper circuit More expensive 7. Synchroniz- synchronization is employed by No synchronization, hence it is a ation the help of clock pulse. combinational circuit with feedback. 8. example any memory element with clock any feedback circuit without clock signal, like clocked S-R flip-flop like latch. 9. security highly secure because without less secure because if by fault using clock pulse nobody can input is changed at any instant of change the state of the circuit. time, output will be changed immediately. 10. power less power consumption because high power consumption. consumption flip-flops are operated at the half of clock pulse pulse The devices, combinations of logic gates, can store or delay certain bits, which provide a memory function, is called sequential circuits. In each stage sequential circuit depends on the present inputs as well as results of the previous stage (or past

outputs) for its own inputs. Sequential circuits are classified in two main categories which are synchronous and asynchronous sequential circuits and both depend on timing of their signals. From the above differences commonly used example of sequential synchronous circuit is Flip-Flop. Flip-Flops The simplest kind of sequential circuit is a memory cell that has only two states either 1 or 0. Such two state sequential circuits are called flip-flop because they flip from one state to another and then flop back. Thus a flip-flop is also known as bistable multivibrator. Flip-Flip is also known as one bit memory cell because it has two stable states which are 1 state and 0 state. General Block Diagraminput lines . . . Q Flip-Flop ck Q Normal output

Inverted output

Fig.(1) 1. It has one or more inputs and two outputs Q and Q. The two outputs are complementary to each other. 2. If Q = 1 and Q = 0 it means set state and If Q=0 and Q = 1 it means reset state. 3. When the flip-flop output Q = 1 and Q = 0, it will remain in that stable state until one or more of the inputs are excited to effect a change in the output. Since the flip-flop output will remain set or reset state until the trigger pulse is given to change the state, thus it can be regarded as a memory device to store one binary digit. Latch- Flip-Flop is also known as Latch why? The name flip-flop and latch are sometimes used interchangeably. The main difference is that the term flip-flop is more appropriately associated with devices that change state only on a clock edge or pulse, whereas latches change state without being clocked. We can say flip-flop is clocked and latches are not but both are bistable (two stable states) and both are used to store binary data. If in a flip-flop no clock is present to gate (e.g. NAND or NOR) for excitation inputs then it is known as latch. The latches are said to be asynchronous because no synchronizing clock is present. The simplest binary storage circuit is the latch and a latch can be constructed by cross connecting the outputs of a multiple input inverting gate (e.g. NAND or NOR) back to an input. We can say flip-flop or latch can be obtained by using NAND or NOR gates and symbol of latch is

## NAND configuration Symbolo

NOR configuration

S R

Q Latch Q

S
R

Q
Q

## Logic circuitS (set) G1 Q=1

o

Q G3

R (reset) G2 Fig.(2a)

Q=0

G4 Fig.(2b)

Operation- Above logic circuits are also called cross-coupled inverters or memory elements. In the circuit two inverters G1 and G2 NAND gates are used as inverters the output of G1 is connected to the input of G2 and output of G2 is connected to the input of G1. Let output of G1 to be Q=1, which is also the input of NAND gate G2. Therefore output of G2 will be Q=0. It means if Q=1 then Q=0 and if Q=0 then Q=1 Since above circuit may store one bit of information (either 1 or 0), thus t is a 1-bit memory unit or 1-bit memory cell. Because of the information is locked or latched in this circuit and hence the circuit flip-flop is also known as latch.

Draw back- 1. In the latch there is no way of entering the desired digital information to be stored in it. 2. When the power is switched ON, the circuit switches to one of the stable states (Q=1 or 0) and it is not possible to predict the state earlier. Solution- above draw backs are the main reason for invention of S-R latch. In above circuit if we replace the inverter G1 and G2 with two input NAND gates then the other input terminals of the NAND gates G1 and G2 can be used to enter the desired digital information by using other two NAND gates G3 and G4. the desired circuit is shown below
Sn (set) 1 (let) G3 0 1 0 Rn (reset) G4 Fig.(3) o 1 G2 o Qn+1= 0 o 0
o

Qn+1 =1 G1

In above circuit two additional inverter G3 and G4 have been added to the above memory element diagram Fig.(2a) by which we get S-R Flip-Flop without clock input. Operation1. If Sn=1 and Rn= 0:- The output of G3 =0 and the output of G4 = 1 Since one input of G1 is 0, thus output Qn+1 equals to 1 (e.g. Qn+1 = 1) Similarly since both the inputs of G2 is 1, thus output Qn+1= 0 From this step Qn+1 = 1 and Qn+1 = 0 which implies Set State. 2. If Sn=0 and Rn= 1:- The output of G3 = 1 and the output of G4 = 0 Since one input of G2 is 0, thus output Qn+1 equals to 1 (e.g. Qn+1 = 1) Similarly since both the inputs of G1 is 1, thus output Qn+1 = 0 From this step Qn+1 = 0 and Qn+1 = 1 which implies Reset or Clear State. 3. If Sn=0 and Rn= 0- The output of G3 = 1 and the output of G4 = 1 Now the operation depends upon previous output If previous output is Sn=1 and Rn =0 (set state), it implies the one input of NAND gate G1 is 0, thus output Qn+1 =1 and now both the inputs of G2 is 1, thus output Qn+1= 0. From this step Qn+1 = 1 and Qn+1 = 0 which implies Set State or the previous state is unaltered. Similarly if previous output is Sn=0 and Rn =1 (Reset state), it implies the one input of NAND gate G2 is 0, thus output Qn+1 =1 and now both the inputs of G1 is 1, thus output Qn+1 = 0. From this step Qn+1 = 1 and Qn+1 = 0 which implies Reset State or the previous state is unaltered. 4. If Sn=1 and Rn=1- The output of G3 = 0 and the output of G4 = 0, then both output Qn+1 and Qn+1 will try to become 1, which is not allowed and

## therefore the input condition is prohibited. Thus the truth table is

inputs outputs Sn Rn Qn+1 Q'n+1 0 0 Qn Qn 0 1 0 1 1 0 1 0 1 1 ? ? mode of operation Hold Reset Set Prohibited

where, Sn and Rn denote the inputs and Qn is the output during the bit time n. while Qn+1 denotes the output after the pulse passes in the bit time n+1.

Characteristic equation for S-R latch- For characteristic equation we draw a truth
table for all possible previous outputs and their present outputs respectively.

## Input Sn 0 0 0 0 1 1 1 1 K-Map for Qn+1 Qn SnRn 00

0

Rn 0 0 1 1 0 0 1 1

01
2

11 x x
6

10 Sn 1 1
4

0 1 1

RnQn

## Characteristic equation for S-R latch is Qn+1 = Sn + RnQn

For avoiding the draw-back of Latches we use clock pulses which causes transition between two states and by which the flip-flop is categorized in different types as given below 1. Clocked S-R flip-flop 2. J-K flip-flop 3. D flip-flop 4. T flip-flop 5. M-S flip-flop

Asynchronous or direct inputs- For the flip-flop discuss so far the S-R, D, T and J-K; the inputs are called synchronous input because data on these inputs are transferred to the flip-flops output only on the triggering edge of the clock pulse or the data are transferred synchronously with the clock. flip-flops available in IC packages sometimes provide special inputs for setting (preset) or clearing (clear) the flip-flop, asynchronously. These inputs are called asynchronous or direct inputs. These inputs are connected directly into the latch portion of the flip-flop so that they override the effect of the synchronous inputs J, K and the clock.

## The clocked S-R Flip-Flops

In the S-R latch the output changes occurs immediately after the input changes occur. It means the latch is sensitive to its S (set) and R (reset) inputs at all times. It is often required to set or reset the S-R latch or memory cell in synchronism with a train of pulses known as clock (ck). Such a circuit is referred to as a clocked S-R flip-flops. Q is comes from Latin language "quiscens" or "the present particle" or "what is present available" or "present output". Similar is the word quiescence. A lot of words in physics come from Latin and Greek languages. Logic circuitUsing NAND gates only Using NOR and AND gates
Sn (set) 1 (let) G3 ck 1 0 Rn (reset) G4 o G2 o Qn+1= 0 Rn (reset)
o o

0 G1 0
o

Qn+1 =1 Sn (set)
o

Qn+1

ck

Qn+1

Fig.(4) Operation- * If any input of NAND gate is equal to 0 then output of this NAND gate = 1 and if both the input is =1 then output is 0. * The circuit behaves like a S-R latch when ck=1 and retains its previous state when ck=0. But if clock pulse is not present the gates G3 and G4 are inhibited (stop). Now the some steps of operation1. if Sn = Rn =0 and ck=1, implies Hold condition the output at the end of the clock pulse is same as the output before the clock pulse it means Qn+1 = Qn and Qn+1 = Qn 2. if Sn = 0, Rn =1 and ck=1, it implies Reset condition then output of G3 NAND gate = 1 and output of G4 NAND gate = 0, therefore the out put of G2 NAND gate =Qn+1 = 1 which is also an input of gate G1. Thus both the input of G1 are = 1 and the output of G1 NAND gate = Qn+1 = 0. 3. if Sn = 1, Rn = 0 and ck=1; it implies Set condition then output of G4 NAND gate = 1 and output of G3 NAND gate = 0, therefore the out put of G1 NAND gate =Qn+1 = 1 which is also an input of gate G2. Thus both the input of G2 are = 1 and the output of G2 NAND gate = Qn+1 = 0.

4. if Sn = 1, Rn = 1 and ck=1; it implies Prohibited condition The output of gates G3 and G4 are both 0, making one of the input of G1 and G2 gates become 0. Consequently Qn+1 and Qn+1 both will attain logic 1, which is not full-fill our assumption. This means that state of the circuit is undefined, indeterminate or ambiguous. Thus condition Sn = 1, Rn = 1 and ck=1 is forbidden and it must not be allowed to occur. Logic symbol-

## NAND configuration SymbolS Q clocked

S-R flip-flop R Q Thus the truth table is inputs outputs ck Sn Rn Qn Qn+1 Q'n+1 0 x x 0 0 1 1 0 0 1 1 0 1 0 1 0 0 1 1 0 1 1 0 1 1 1 0 0 1 0 1 1 0 1 1 0 1 1 1 0 ? ? 1 1 1 1 ? ?

ck

mode of operation Hold Hold Reset Reset Set Set Prohibited Prohibited

where, Sn and Rn denote the inputs and Qn is the output during the bit time n. while Qn+1 denotes the output after the pulse passes in the
bit time n+1.

Characteristic equation for clocked S-R flip-flop- from the above truth table K-Map for Qn+1 SnRn Qn 00 0 1 1
0

01
2

11 x x
6

10 Sn 1 1
4

## Delay flip-flop or D flip-flop

It has only one input called delay input, because the data (a binary 0 or 1) at the input is delayed from getting to output Q, and two outputs Q and Q. It can be constructed from an S-R flip-flop by inserting an inverter (NOT gate) between S and R inputs. The single input is assigned by D at the S input. D flip-flop is either used as a delay device or as a latch to store 1-bit of binary information. If the inverter is added in S-R latch, we will get D latch and if the inverter is added in clocked S-R flip-flop, we will get D flip-flop as shown in below diagram.
S G3 o ck
o

Q G1
o

D S
o
o

Q
o

ck o R G4 G2 o Q R
o o

D latch

D flip-flop

The NOT gate is used to provide the complemented inputs. According to the above diagram, D input goes directly to the S input and its complement is applied to the R input through NOT gate. Therefore only two input conditions exists i) either S=0 and R=1 ii) either S=1 and R=0 In these two input conditions we dont find ambiguous or prohibited states. Logical Symbol:For D latch For D flip-flop D
o

D
o ck

## Truth-Table Truth Table using D latch

I/P D 0 0 1 1 Prev. O/P Pres.O/P Qn Qn+1 0 0 1 0 0 1 1 1

## Truth Table using D flip-flop

I/P Prev.O/P Pres.O/P State ck D Qn Qn+1 1 0 x 0 Reset 1 1 x 1 Set 0 x x Qn No change

In both truth tables we have to find that present output is same as data input (D), therefore it is also known as Transparent latch or flip-flop. Characteristics Equation :Characteristic equation using D latch Characteristic equation using D flip-flop For Qn+1 :DQn
Qn D 0 1 1 00
0

ck 01
1

00 0 x
0

01 x 0
1

11 x 1
3

10 x 1
2

Qn+1 = D

Qn+1 = D

## Thus the characteristics equation for D latch or D flip-flop is Qn+1 = D

JK Flip-Flop
The J-K flip-flop is considered to be the universal flip-flop as it has the features of all other types of flip-flops. The uncertainty in the state of an S-R flip-flop when S= R=1 can be eliminated by converting it into a J-K flip-flop. The set and reset inputs were given the symbols J and K after one of the engineers that helped design the J-K flip-flop who was the Texas Instruments engineer that invented the integrated circuit in 1958. Jack St. Clair Kilby shared the Nobel Prize in 2000 with a German and a Russian in Physics. Logic circuit of J-K Flip-Flop using NAND gates:Logic circuit of J-K Flip-Flop using NAND gates:J G3 ck
o

Qn+1 G1
o

J inputs ck o K G4 G2 o Qn+1 K

## Qn+1 outputs Qn+1

Operation- The circuit using NAND gates as shown above, the output is fed back to the input, and therefore change in the output results in a change in the input. The following steps of its working are available. 1. When both J=K=0 and ck=1 The output of NAND gate G3 = 1 and the output of NAND gate G4=1. It means the out put Qn+1 depends over previous state of outputs. If states are (i) reset (Qn = 0 and Qn = 1) (ii) set (Qn = 1 and Qn = 0) Inputs of NAND gate G1 are Inputs of NAND gate G1 are Qn = 1, o/p of G3=1 and Pr=1 Qn = 0, o/p of G3=1 and Pr=1 Then o/p of = G1 = Qn+1 =0. The Qn+1 = 0 Then o/p of = G1 = Qn+1 =1. The is fed back as input of G2 and by which Qn+1 = 1 is fed back as i/p of G2 and the output of G2 = Qn+1 = 1. by which the all inputs of G2 =1. Thus we find the hold condition, it means The o/p of G2 = Qn+1 = 0 Next State o/p = previous state o/p Next State o/p = previous state o/p 2. when J=0, K=1 and ck=1, the previous state of flip-flop is (i) reset (Qn = 0 and Qn = 1) (ii) set (Qn = 1 and Qn = 0) Then o/p of G3 =1 & o/p of G4 =1 Then o/p of G3 =1 & o/p of G4 =0 The i/p of G2 are- Qn = 0, o/p of G4 =1 it means o/p of G2 is Qn+1 = 1. Thus the o/p of G2 =1 & by which the now since all inputs of G1=1 and all inputs of G1=1 and the o/p of G1 =0 the o/p of G1 =0 It means reset state is found. It means reset state is found.

3. when J=1, K=0 and ck=1, the previous state of flip-flop is (i) reset (Qn = 0 and Qn = 1) (ii) set (Qn = 1 and Qn = 0) Then o/p of G3 =0 & o/p of G4 =1 Then o/p of G3 =1 & o/p of G4 =1 it means o/p of G1 is Qn+1 = 1. The i/p of G1 are- Qn =0, o/p of now since all inputs of G2=1 and the o/p G3 =1. Thus the o/p of G1=Qn+1=1. of G2 =Qn+1 =0 Since all inputs of G2 =1 and the It means set state is found. o/p of G2 =Qn+1 =0. It means set state is found. Finally set condition of flip-flop is found. 4. when J=1, K=1 and the previous state of flip-flop is (i) reset (Qn = 0 and Qn = 1) (ii) set (Qn = 1 and Qn = 0) Then o/p of G4 =1 & o/p of G3 =0 Then o/p of G3 =1 & o/p of G4 =1 Thus the o/p of G1 =Qn+1=1, which is the now o/p Qn+1depends on previous i/p of G2. Since all the inputs of G2 =1, o/p. since Qn = 0, it means o/p of therefore Qn+1 =0. G1 = 1. All inputs of G2 are equal It means set state is found. to 1 therefore o/p of G2 =0 Flip-flop will be in set state and it Flip-flop will be in reset state and will toggle to the reset state in short it will toggle to the set state in short time period compared to time duration time period compared to time duration of clock pulse and hence state is of clock pulse and hence state is changed again and again until the changed again and again until the clock pulse goes back to 0. clock pulse goes back to 0. Truth table of JK flip-flop for all possible combinationsInputs prev. o/p I/P to S-R FF present O/P mode of ck Jn Kn Qn Qn Sn Rn Qn+1 operation 0 1 1 1 1 1 1 1 1 x 0 0 0 0 1 1 1 1 x 0 1 0 0 1 0 1 0 1 0 1 1 1 0 0 0 1 0 1 0 1 0 1 1 1 0 x 0 0 0 0 1 0 1 0 x 0 0 0 1 0 0 0 1 Qn 0 1 0 0 1 1 1 0 Hold Hold Hold Reset Reset Set Set Toggle Toggle

Characteristic equation for J-K flip-flop- from the above truth table K-Map for Qn+1
JnKn Qn 00 0 1 1
0

01
2

11 1
6

10 Jn Qn 1 1
4

## Characteristic equation for J-K flip-flop is KnQn Qn+1 = Jn Qn + KnQn

Draw back of JK flip-flop:- If J=1, K=1 and clock pulse is applied (ck=1), both J and K will cause output to complement again and again until the clock pulse goes back to 0. We can see in a positive clock pulse, output of a flip-flop toggles (switch to the opposite state). It is called Race-around condition or Racing problem. To avoid this undesirable operation, the clock pulse must have a time duration (t p) of a clock pulse that is shorter than the propagation delay time (t) of the flip -flop.

## T or trigger or toggle flip-flop

By using race around condition we make a T or trigger or toggle flip-flop (is obtained from a J-k flip-flop by connecting its J and K inputs together and has only a single data input, a clock input and two outputs Q & Q.) which is used in many cases for binary counters and sequential counting networks. When a clock pulse is applied, the output changes state once every input cycle, thus inherent divide by 2 capability condition is found. Thus repeating one cycle for every two input cycles and this action is required in many cases. T flip-flop is shown below
T input J G3 ck ck o K G4 G2 o Qn+1 K Qn+1 outputs Qn+1
o

G1

T input

Qn+1

T flip-flop is a single input form of the J-K flip-flop and it is obtained if both J and K inputs are tied together. Operation- 1.When input T is low or 0 (i.e. both J and K inputs of J-K flip-flop are 0) and device is clocked, the output Qn+1 repeat its previous output Qn. When T = 0, Qn = 0 and ck = 1, it implies Qn+1 = Qn = 0. Similarly, if T = 0, Qn = 1 and ck =1, it implies Qn+1 = Qn = 1. 2.When input T is High or 1 (it means both J and K inputs of J-K flipflop are 1), and device is clocked, the output Qn+1 will change or toggle to the complement of the previous output. When T = 1, Qn = 0 and ck = 1, it implies Qn+1 = Qn = 1. Similarly, if T = 1, Qn = 1 and ck =1, it implies Qn+1 = Qn = 0. Truth-Table of T flip-flopPrev. O/P Qn 0 0 1 1 Qn T 0 1 Qn.T 1 0 1 Qn .T 1 Characteristic equation for T flip-flop is Qn+1 = Qn .T + Qn.T I/P Next O/P T Qn+1 0 0 1 1 0 1 1 0

Characteristic equation-

Racing Problem and its solution:- The difficulty of both inputs are equal to 1 (i.e. S=1 & R=1) being not allowed in an S-R flip-flop, is eliminated in a J-K flip-flop by using the feed-back connection from outputs (i.e. Qn & Qn ) to the inputs of gates G4 & G3 respectively. As we know the duration (tp) of the clock pulse is greater than the propagation delay time (t) of flip-flop. or it means duration (tp) of the clock pulse > propagation delay time (t) of flip-flop tp > t According to wave forms we can easily understood this problem
t

## leading +ve edge tp (Clock pulse)

trailing ve edge

Thus we conclude that for the duration tp of the clock pulse, the output will oscillate back and forth between 0 and 1, while clock pulse ck=1. At the end of the clock pulse (ck=0), the value of output Qn+1 is ambiguous. This situation is called Racing Problem or Race Around Condition. Solution to overcome the Racing Problem 1. Racing Problem can be avoided if tp < t < T ; but it is very difficult to Achieve. 2. If we use +ve or ve edge triggering in the given flip-flop. 3. The more practical method for overcome this difficulty is use of the Master-Slave (M-S) flip-flop or configuration.

Master-Slave Flip-Flops
As we know the condition S=1 and R=1 is not allowed in an clocked S-R flip-flop. this problem is eliminated by using J-K flip-flop in which the feed backe edge connection from the output to the inputs of the gates 3 and 4. But we find a situation which is known as race around condition or toggle condition or racing problem. To prevent the race around difficulty a most practical method is used, this is called Master-Slave (M-S) configuration. But M-S flip-flop is used before the development of edge triggered flip-flops. Principle- A Master-slave flip-flop is constructed by using two sections, master section and the slave section. Both sections are connected serially with feed back from the outputs of the second to the inputs of the first. Positive clock pulses are applied to the first section and the clock pulses are inverted before these are applied to the second section. The first section, called the master, is driven by the positive edge of the clock pulse and the second section, called slave, is driven by the negative edge of the clock pulse. Therefore, when the clock input has a +Ve edge, the master acts according to its J-K flip-flop inputs, but at this time slave does not respond because it

requires a negative edge at the clock input. When the clock input has a negative edge, the slave flip-flop copies the master outputs. But master does not respond to the feedback from Q and Q because of it requires a +Ve edge at its clock input. Hence the M-S flip-flop does not show racing problem but its speed is very slow. The block diagram using two methods i) Master Slave S-R flip-flopS ck R
Master

QM

S QS ck

QM
o

R
Slave

QS

QM

S QS Q
Q

R
Master

QM
o

R
Slave

QS

## Clocked M-S flip-flop using NAND gates-

J ck

G3

G1

QM

S G7

G5 o

Qn+1

ck K G4 o G2 o QM R G8 o G6 o Qn+1

o Operation- When positive clock pulse the first flip-flop is enabled and the output QM and QM respond to the inputs J and K according to J-K table. At this time the slave section flip-flop disabled until the negative clock pulse does not come. 1. If J=0, K=0 and positive clock pulse are applied, we find the hold condition. It

means input does not produce any change. 1. When J=1, K=0 and positive clock pulse are applied, master section will be in set state, not bother about the previous state. Now in the presence of negative clock pulse, high output of master section drives the S input of the slave section and the slave flip-flop sets. We observe that slave flip-flop copying the action of master flip-flop. 2. When J=0, K=1 and positive clock pulse are applied, master section will be in reset state, not bother about the previous state. Now in the presence of negative clock pulse, the slave flip-flop resets and again copying the action of master flip-flop. 3. When J=1, K=1 and positive clock pulse are applied, master section operates and the slave section then copies the output of master on the negative clock. But at this instant master does not respond to the feedback from Qn+1 and Qn+1 because of it requires a +Ve edge at its clock input and master flip-flop is inactive. This prevents the race around condition. Truth tableIf Previous state is reset
Prev.O/P Inputs
ck Qn(reset) 0 J 0 K 0

## If Previous state is set

Prev.O/P Inputs
ck Qn(set) 1 1 1 1 1 J 0 K 0

Outputs QM Qn+1
0 0

Outputs QM Qn+1
1 no output

no output

no output

no output

no output

no output

no output

no output

no output

0 0

1 1

0 1

no output 1

1 no output 1

1 1 1

no output

no output

no output

no output