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SYLLABUS

EE2356 - MICROPROCESSOR AND MICRO CONTROLLER LABORATORY


AIM
1. To understand programming using instruction sets of processors. 2. To study various digital & linear

8-bit Microprocessor 1. Simple arithmetic operations: Multi precision addition / subtraction / multiplication / division. 2. Programming with control instructions: Increment / Decrement, Ascending / Descending order, Maximum / Minimum of numbers, Rotate instructions - Hex / ASCII / BCD code conversions. 3. Interface Experiments: A/D Interfacing. D/A Interfacing. Traffic light controller. 4. Interface Experiments: Simple experiments using 8251, 8279, 8254. 8-bit Microcontroller

5. Demonstration of basic instructions with 8051 Micro controller execution, including: Conditional jumps, looping Calling subroutines. Stack parameter testing 6. Parallel port programming with 8051 using port 1 facility: - Stepper motor and D / A converter. 7. Study of Basic Digital ICs (Verification of truth table for AND, OR, EXOR, NOT, NOR, NAND, JK FF, RS FF,D FF) 8. Implementation of Boolean Functions, Adder / Subtractor circuits. 9. Combination Logic; Adder, Subtractor, Code converters, Encoder and Decoder 10. Sequential Logic; Study of Flip-Flop,Counters(synchronous and asynchronous),Shift Registers

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LIST OF EXPERIMENTS Ex. No 8 BIT MICROPROCESSOR (8085) 1(a) 8- bit Addition 1(b) 8 bit Subtraction 1(c) 8- bit Multiplication 1(d) 8- bit Division 2(a) Ascending order 2(b) Descending order 2( c) Largest of a given numbers 2(d) Smallest of a given numbers 3(a) Code Conversion: ASCII to Hexadecimal 3(b) Code Conversion: Hexadecimal to ASCII 3(c) Code Conversion: Hexadecimal to Binary 3(d) Code Conversion: Hexadecimal to BCD 4(a) Interfacing: ADC with 8085 4(b)Interfacing: DAC with 8085 Interfacing: Traffic Light Controller with 8085 6(a)Interfacing: 8251 with 8085 6(b) Interfacing: 8279 with 8085 6(c) Interfacing: 8253 with 8085 MICROCONTROLLER(8051) 7(a) Sum of elements in an array 7(b) Sum using Stack 7( c) Sum using call option 8(a) Interfacing: Stepper Motor with 8051 8(b) Interfacing: DAC with 8051 Page No.

4 5 6

7 8

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10 11 12 13 14 15

Verification of truth table for AND, OR, EXOR, NOT, NOR, NAND, JK FF, RS FF,D FF Implementation of Boolean Functions, Adder / Subtractor circuits Code converters, Encoder and Decoder Study of Flipflops Counters(synchronous and asynchronous), Shift registers Differentiator, Integrator Timer IC applications

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STUDY OF BASIC DIGITAL ICS

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8085 MICROPROCESSOR

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Ex.No: 1

SIMPLE ARITHMETIC OPERATIONS

AIM: To write an assembly language program to add, subtract, multiply and divide the given data stored at two consecutive locations using 8085 microprocessor.

A. 8 BIT DATA ADDITION: ALGORITHM: 1. 2. 3. 4. Initialize memory pointer to data location. Get the first number from memory in accumulator. Get the second number and add it to the accumulator. Store the answer at another memory location.

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FLOW CHART:

START

[C]

00H

[A]

[M]

[HL]

[HL]+1

[A]

[A]+[M]

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Is there a Carry ?

YES

[C]

[C]+1

[HL]

[HL]+1

[M]

[A]

[HL]

[HL]+1

[M]

[C]

STOP

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[HL]

4500H

PROGRAM: ADDRESS OPCODE LABEL 4100 START 4101 4102 4103 4104 4105 4106 MNEMONICS OPERAND MVI C, 00 LXI H, 4500 COMMENT Clear C reg. Initialize HL reg. to 4500 Transfer first data to accumulator Increment HL reg. to point next memory Location. Add first number to acc. Content. Jump to location if result does not yield carry. Increment C reg. Increment HL reg. to point next memory Location. Transfer the result from acc. to memory. Increment HL reg. to point next memory Location. Move carry to memory Stop the program

MOV INX

A, M H

4107 4108 4109 410A 410B 410C

ADD JNC

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L1 INR INX MOV INX MOV HLT

410D 410E

410F 4110

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L1 C H M, A H M, C

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B. 8 BIT DATA SUBTRACTION

ALGORITHM: 1. 2. 3. 4. Initialize memory pointer to data location. Get the first number from memory in accumulator. Get the second number and subtract from the accumulator. If the result yields a borrow, the content of the acc. is complemented and 01H is added to it (2s complement). A register is cleared and the content of that reg. is incremented in case there is a borrow. If there is no borrow the content of the acc. is directly taken as the result. 5. Store the answer at next memory location.

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FLOW CHART:

START

[C]

00H

[HL]

4500H

[A]

[M]

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NO
Is there a Borrow ?

YES

Complement [A] Add 01H to [A]

[C]

[C]+1

[HL]

[HL]+1

[M]

[A]

[HL]

[HL]+1

[M]

[C]

STOP

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[A]

[A]-[M]

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[HL]

[HL]+1

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PROGRAM: ADDRESS OPCODE LABEL 4100 START 4101 4102 4103 4104 4105 4106 MNEMONICS OPERAND MVI C, 00 LXI H, 4500 COMMENT Clear C reg. Initialize HL reg. to 4500 Transfer first data to accumulator Increment HL reg. to point next mem. Location. Subtract first number from acc. Content. Jump to location if result does not yield borrow. Increment C reg. Complement the Acc. content Add 01H to content of acc. Increment HL reg. to point next mem. Location. Transfer the result from acc. to memory. Increment HL reg. to point next mem. Location. Move carry to mem. Stop the program

MOV INX

A, M H

4107 4108 4109 410A 410B 410C 410D 410E 410F

SUB JNC

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INR CMA ADI INX L1 MOV INX MOV HLT

4110 4111

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4112 4113

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L1 C 01H H M, A H M, C

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C. 8 BIT DATA MULTIPLICATION:

ALGORITHM: LOGIC: Multiplication can be done by repeated addition. 1. 2. 3. 4. 5. 6. 7. 8. Initialize memory pointer to data location. Move multiplicand to a register. Move the multiplier to another register. Clear the accumulator. Add multiplicand to accumulator Decrement multiplier Repeat step 5 till multiplier comes to zero. The result, which is in the accumulator, is stored in a memory location.

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FLOW CHART:
START

[HL] 4500

[HL] [HL]+1

A 00

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[A] [A] +[M] Is there any carry NO YES C C+1 B B-1 NO IS B=0 YES A 9

C 00

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B M

[HL]

[HL]+1

[M]

[A]

[HL]

[HL]+1

STOP

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[C]

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PROGRAM: ADDRESS OPCODE LABEL 4100 START 4101 4102 4103 4104 MNEMONICS LXI OPERAND H, 4500 COMMENT Initialize HL reg. to 4500 Transfer first data to reg. B Increment HL reg. to point next mem. Location. Clear the acc. Clear C reg for carry

INX

4109 410A 410B 410C 410D 410E 410F 4110 4111 4112

L1

ADD JNC

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NEXT INR DCR JNZ INX MOV INX MOV HLT

4113 4114

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4115 4116

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M NEXT C B L1 H M, A H M, C

4105 4106 4107 4108

MVI MVI

A, 00H C, 00H

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MOV

B, M

Add multiplicand multiplier times. Jump to NEXT if there is no carry Increment C reg Decrement B reg Jump to L1 if B is not zero. Increment HL reg. to point next mem. Location. Transfer the result from acc. to memory. Increment HL reg. to point next mem. Location. Transfer the result from C reg. to memory. Stop the program

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D. 8 BIT DIVISION:
ALGORITHM: LOGIC: Division is done using the method Repeated subtraction. 1. Load Divisor and Dividend 2. Subtract divisor from dividend 3. Count the number of times of subtraction which equals the quotient 4. Stop subtraction when the dividend is less than the divisor .The dividend now becomes the remainder. Otherwise go to step 2. 5. stop the program execution.

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FLOWCHART:

START

B 00

[HL] 4500

A M

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IS A<0 NO
YES

[B] [B] +1

A A+ M

B B-1

[HL]

[HL]+1

[M]

[A]

[HL]

[HL]+1

[M]

[B]

STOP

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M A-M

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[HL] [HL]+1

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PROGRAM: ADDRESS 4100 4101 4102 4103 4104 4105 4106 OPCODE LABEL MNEMONICS MVI LXI OPERAND B,00 H,4500 COMMENTS Clear B reg for quotient Initialize HL reg. to 4500H Transfer dividend to acc. Increment HL reg. to point next mem. Location. Subtract divisor from dividend Increment B reg Jump to LOOP if result does not yield borrow Add divisor to acc. Decrement B reg Increment HL reg. to point next mem. Location. Transfer the remainder from acc. to memory. Increment HL reg. to point next mem. Location. Transfer the quotient from B reg. to memory. Stop the program

INX

410F 4110

4111 4112

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OBSERVATION: 14

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MOV INX M,A H MOV HLT M,B

4108 4109 410A 410B 410C 410D 410E

ADD DCR INX

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M B H

INR JNC

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B LOOP

4107

LOOP

SUB

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MOV

A,M

ADDITION:

S.NO 1 2

SUBTRACTION:

S.NO 1 2

MULTIPLICATION:

DIVISION:

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S.NO 1 2 INPUT ADDRESS DATA 4500 4501 4500 4501 S.NO 1 2 INPUT ADDRESS DATA 4500 4501 4500 4501

INPUT ADDRESS DATA 4500 4501 4500 4501

OUTPUT ADDRESS DATA 4502 4503 4502 4503

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OUTPUT ADDRESS DATA 4502 4503 4502 4503

OUTPUT ADDRESS DATA 4502 4503 4502 4503

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INPUT ADDRESS DATA 4500 4501 4500 4501

OUTPUT ADDRESS DATA 4502 4503 4502 4503

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RESULT: Thus the addition, subtraction, multiplication and division of two numbers was performed using the 8085 microprocessor. 16

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Ex.No: 2

SORTING OF AN ARRAY

AIM: To write an assembly language program to arrange an array of data in ascending and descending order and to find the smallest and largest data among the array.

A. ASCENDING ORDER
ALGORITHM:

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1. Get the numbers to be sorted from the memory locations. 2. Compare the first two numbers and if the first number is larger than second then I interchange the number. 3. If the first number is smaller, go to step 4 4. Repeat steps 2 and 3 until the numbers are in required order

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FLOWCHART:

START [B] 04H [HL] [8100H]

[C] 04H [A] [HL] [HL [HL] + 1

YES

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NO [D] [HL] [HL] [A] [HL] [HL] - 1 [HL] [D] [HL] [HL] + 1 [C] [C] 01 H A 18

IS [A] < [HL]?

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NO

YES [B] [B]-1

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YES STOP 19

IS [B] = 0?

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NO

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IS [C] = 0?

PROGRAM: ADDRESS 4100 4101 4102 4103 4104 4105 4106 4107 4108 LOOP 3 OPC ODE LABEL MNEMONICS MVI OPERA ND B,04 COMMENTS Initialize B reg with number of comparisons (n-1) Initialize HL reg. to 4200H

LXI

H,4200

MVI LOOP2 MOV INX

C,04 A,M H

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MOV MOV DCX MOV INX DCR JNZ D,M M,A H M,D LOOP1 H C LOOP2 DCR JNZ B LOOP3 HLT

4109 410A 410B 410C 410D 410E 410F 4110 4111 4112 4113 4114 4115 4116 4117 4118 4119 411A

CMP JC

M LOOP1

Initialize C reg with no. of comparisons(n-1) Transfer first data to acc. Increment HL reg. to point next memory location Compare M & A If A is less than M then go to loop1

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Transfer data from M to D reg Transfer data from acc to M Decrement HL pair Transfer data from D to M Increment HL pair Decrement C reg If C is not zero go to loop2 Decrement B reg If B is not Zero go to loop3 Stop the program

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B. DESCENDING ORDER

ALGORITHM: 1. Get the numbers to be sorted from the memory locations. 2. Compare the first two numbers and if the first number is smaller than second then I interchange the number. 3. If the first number is larger, go to step 4 4. Repeat steps 2 and 3 until the numbers are in required order

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FLOWCHART:

START [B] 04H [HL] [8100H]

[C] 04H
[A] [HL]

[HL [HL] + 1

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NO YES [D] [HL] [HL] [A] [HL] [HL] - 1 [HL] [D] [HL] [HL] + 1 [C] [C] 01 H A 22

IS [A] < [HL]?

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IS [C] = 0? YES [B] [B]-1

NO

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YES STOP 23

IS [B] = 0?

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NO

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PROGRAM: ADDRE SS 4100 4101 4102 4103 4104 4105 4106 4107 4108 4109 410A 410B 410C 410D 410E 410F 4110 4111 4112 4113 4114 4115 4116 4117 4118 4119 411A OPCO DE LABEL MNEM ONICS MVI LXI OPER AND B,04 H,4200 COMMENTS Initialize B reg with number of comparisons (n-1) Initialize HL reg. to 4200H

LOOP 3

MVI LOOP2 MOV INX CMP JNC

C,04 A,M H M LOOP1

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LOOP1 DCR JNZ B LOOP3 HLT

MOV MOV DCX MOV INX DCR JNZ

D,M M,A H M,D H C LOOP2

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Initialize C reg with no. of comparisons(n-1) Transfer first data to acc. Increment HL reg. to point next memory location Compare M & A If A is greater than M then go to loop1

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Stop the program

Transfer data from M to D reg Transfer data from acc to M Decrement HL pair Transfer data from D to M Increment HL pair Decrement C reg If C is not zero go to loop2

Decrement B reg If B is not Zero go to loop3

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C. LARGEST ELEMENT IN AN ARRAY


ALGORITHM: 1. Place all the elements of an array in the consecutive memory locations. 2. Fetch the first element from the memory location and load it in the accumulator. 3. Initialize a counter (register) with the total number of elements in an array. 4. Decrement the counter by 1.

5. Increment the memory pointer to point to the next element.

element).

(largest element) to the accumulator. Else continue. 8. Decrement the counter by 1.

9. Repeat steps 5 to 8 until the counter reaches zero

10. Store the result (accumulator content) in the specified memory location.

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7. If the accumulator content is smaller, then move the memory content

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6. Compare the accumulator content with the memory content (next

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FLOW CHART: START [HL] [8100H]

[B] 04H [A] [HL] [HL [HL] + 1

NO

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YES [A] [HL] [B] [B]-1 IS [B] = 0? NO YES [8105] [A] STOP 26

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IS [A] < [HL]?

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PROGRAM: ADDRE SS 4101 4102 4103 4104 4105 4106 4107 4108 4109 410A 410B 410C 410D 410E 410F 4110 4111 4112 4113 4114 OPCO DE LABEL MNEM ONICS LXI OPER AND H,4200 COMMENTS Initialize HL reg. to 4200H Initialize B reg with no. of comparisons(n-1) Transfer first data to acc. Increment HL reg. to point next memory location Compare M & A If A is greater than M then go to loop

MVI MOV INX CMP JNC

B,04 A,M H M LOOP

LOOP1

LOOP

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STA 4205 HLT

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MOV DCR JNZ

A,M B LOOP1

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Stop the program

Transfer data from M to A reg Decrement B reg If B is not Zero go to loop1

Store the result in a memory location.

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D.SMALLEST ELEMENT IN AN ARRAY


ALGORITHM: 1. Place all the elements of an array in the consecutive memory locations. 2. Fetch the first element from the memory location and load it in the accumulator. 3. Initialize a counter (register) with the total number of elements in an array.

5. Increment the memory pointer to point to the next element.

6. Compare the accumulator content with the memory content (next element).

7. If the accumulator content is smaller, then move the memory content (largest element) to the accumulator. Else continue. 8. Decrement the counter by 1.

10. Store the result (accumulator content) in the specified memory location.

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9. Repeat steps 5 to 8 until the counter reaches zero

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4. Decrement the counter by 1.

FLOW CHART: START [HL] [8100H]

[B] 04H [A] [HL] [HL [HL] + 1

YES

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NO [A] [HL] [B] [B]-1 IS [B] = 0? NO YES [8105] [A] STOP 29

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IS [A] < [HL]?

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PROGRAM: ADDRE SS 4101 4102 4103 4104 4105 4106 4107 4108 4109 410A 410B 410C 410D 410E 410F 4110 4111 4112 4113 4114 OPCO DE LABEL MNEM ONICS LXI OPER AND H,4200 COMMENTS Initialize HL reg. to 4200H Initialize B reg with no. of comparisons(n-1) Transfer first data to acc. Increment HL reg. to point next memory location Compare M & A If A is lesser than M then go to loop

MVI MOV INX CMP JC

B,04 A,M H M LOOP

LOOP1

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STA 4205 HLT

LOOP

MOV DCR JNZ

A,M B LOOP1

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Stop the program

Transfer data from M to A reg Decrement B reg If B is not Zero go to loop1

Store the result in a memory location.

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OBSERVATION: A. ASCENDING ORDER INPUT MEMORY DATA LOCATION 4200 4201 4202 4203 4204 B. DESCENDING ORDER INPUT MEMORY DATA LOCATION 4200 4201 4202 4203 4204 OUTPUT MEMORY DATA LOCATION 4200 4201 4202 4203 4204

C. SMALLEST ELEMENT

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D. LARGEST ELEMENT INPUT MEMORY DATA LOCATION 4200 4201 4202 4203 4204 OUTPUT MEMORY DATA LOCATION

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INPUT MEMORY DATA LOCATION 4200 4201 4202 4203 4204 4205 4205

OUTPUT MEMORY DATA LOCATION 4200 4201 4202 4203 4204

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OUTPUT MEMORY DATA LOCATION

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RESULT:

Thus the sorting operations of arranging an array in ascending, descending order and the largest and smallest element were found using the 8085 microprocessor.

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Ex.No: 3
AIM:

CODE CONVERSIONS

To write an assembly language program to perform the conversions of ASCII to hexadecimal number, hexadecimal to ASCII, hexadecimal to decimal number, binary to hexadecimal number and hexadecimal to binary number.

A.ASCII TO HEXADECIMAL
ALGORITHM: 1. 2. 3. 4. 5. 6. 7. 8. 9. Start the program Load the data from address 4200 to A Move data from accumulator to C Move data from M to HL pair to accumulator Subtract the data 30 from A Decrement content of register Stop the program if C is zero Jump to Step 5 End the program

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FLOWCHART: Start

Set the ASCII value

Subtract 30 from A

Decrement the register content

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Check for Carry? YES NO Subtract 07 from A Store the hex value Stop 34

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PROGRAM: ADDRE SS 4100 4101 4102 4103 4104 4105 4106 4107 4108 4109 410A 410B 410C 410D 410E 410F 4110 4111 4112 4113 4114 4115 4116 4117 OPCO DE LABEL MNEM ONICS LDA OPER AND H,4200 COMMENTS Load data 4200 to A

LXI

D,4301

Load address 4301 in DF

LOOP 1

MOV A,M SUI STAX D DCR C JZ

30

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LOOP INX H INX D JMP LOOP 1 LOOP HLT

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Stop

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Move data from M to A Subtract 30 from A Store data from accumulator to DE Decrement from C register Stop program if C is 0

Increment HL register pair Increment DE register pair Jump to 410A

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MOV C,A LXI

4F H,4201

Move data from A to C Load address 4201 in HL

B. HEXADECIMAL TO ASCII
ALGORITHM: 1. 2. 3. 4. 5. 6. 7. 8. 9. Start the program Load the data from address 4200 to A Move data from accumulator to C Move data from M to HL pair to accumulator Add the data 30 to A Decrement content of register Stop the program if C is zero Jump to Step 5 End the program

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FLOWCHART:

Start

Set the ASCII value

Add 30 to A

Decrement the register content

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Check for Carry? YES NO Store the decimal value Stop 37

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PROGRAM: ADDRE SS 4100 4101 4102 4103 4104 4105 4106 4107 4108 4109 410A 410B 410C 410D 410E 410F 4110 4111 4112 4113 4114 4115 4116 4117 OPCO DE LABEL MNEM ONICS LDA OPER AND H,4200 COMMENTS Load data 4200 to A

LXI

D,4301

Load address 4301 in DF

LOOP 1

MOV A,M ADI STAX D DCR C JZ

30

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LOOP INX H INX D JMP LOOP 1 LOOP HLT

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Stop

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Move data from M to A Subtract 30 from A Store data from accumulator to DE Decrement from C register Stop program if C is 0

Increment HL register pair Increment DE register pair Jump to 410A

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MOV C,A LXI

4F H,4201

Move data from A to C Load address 4201 in HL

C. HEXADECIMAL TO BINARY
ALGORITHM: 1. Start the program 2. Move the content of memory to accumulator 3. Move data 0B o register B 4. Increment the content of HL register pair 5. Rotate the accumulator right 6. Jump to the specified address if carry generated 7. Move 00 to memory 8. Jump to specified address if there is no zero 9. Move 01 to memory 10. Jump to specified address if there is no zero 11. End the program

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FLOWCHART: Start Load address in HL pair

Move data from M to A

Initialize counter B to 08

Increment HL register pair

Rotate accumulator right

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Check for Carry? YES NO Move data from 00 to M Move data from 01 to M Decrement B register NO If B=0? YES Stop 40

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PROGRAM: ADDRE SS 4100 4101 4102 4103 4104 4105 4106 4107 4108 4109 410A 410B 410C 410D 410E 410F 4110 4111 4112 4113 4114 4115 OPCO DE LABEL MNEM ONICS LXI OPERAND H,4200 COMMENTS Load address in HL pair

L3

INX H RRC JC

MVI M JMP

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L1 L2 MVI M DCR B JNZ 01 L3 HLT

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00 L2

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Move 01 to M

L1

Increment the content of HL pair Rotate accumulator right Jump to specified address if carry

Move 00 to M Decrement B register

Decrement B by 1 Jump to the specified address if no zero

Stop the program

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MOV A,M MVI B

08

Move content of M to A Move 0B to register pair

D. BINARY TO HEXADECIMAL
ALGORITHM: 1. Start the program 2. Load the address in HL pair 3. Move the content of memory to accumulator 4. Add the content of accumulator with previous content of accumulator 5. Move the content of B to accumulator 6. Add the content of accumulator with previous content of accumulator 7. Repeat step 6 8. Add B with accumulator content 9. Increment H by 1 10. Move content of M to A 11. End the program

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FLOWCHART: Start Load address in HL pair

Move data from M to A

Add content of A to register B

Add content of A with itself

Add content of A to register B

Add content of M with accumulator

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Increment HL reg pair Increment HL reg pair content Move content of M to accumulator Stop 43

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PROGRAM: ADDRE SS 4100 4101 4102 4103 4104 4105 4106 4107 4108 4109 410A 410B 410C OPCO DE LABEL MNEM ONICS LXI OPERAND H,4150 COMMENTS Load address in HL pair

MOV B,A ADD A ADD B INX H ADD M INX H MOV M,A HLT

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MOV M,A ADD A

Move content of A to M Add A content with previous content of A Move the content from A to B Add A content with previous content of A Add B content with A Increment H by 1 Add M content with A Increment H by 1 Move content of A to M Stop the program

E. HEXADECIMAL TO DECIMAL
ALGORITHM: 1. Start the program 2. Load the address in HL pair 3. Move the content from HL to A 4. Subtract 64 from A 5. Increment BC pair 6. Jump to address 4207 7. Subtract 0A from A 8. Increment HL pair 9. Rotate accumulator left 10. Increment HL pair 11. End the program

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FLOWCHART: Start Load address in HL pair Initialize D register Clear accumulator Move HL to C register Add 01 with A Adjust A to BCD

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NO Increment D register Increment C register NO Check Carry? YES Store A in 4151 H Move D to accumulator Store A in 4150 H Stop 46

Check Carry?

YES

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PROGRAM: ADDRE SS 4100 4101 4102 4103 4104 4105 4106 4107 4108 4109 410A 410B 410C 410D 410E 410F 4110 4111 4112 4113 4114 4115 4116 4117 4118 4119 411A 411B 411D 411E 411F 4120 4121 4122 4123 4124 4125 4126 4127 4128 OPCO DE LABEL MNEM ONICS LXI H LXI B OPER AND 4150 0000 COMMENTS Load data from 4150 to HL pair Load data from address to BC

L4

MOV A,M SUI JC

64 L1

Move the content from HL to A Subtract 64 from A

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L1 L3 ADI SUI JC 64 0A L2 L2 INR C JNC L3 ADI INX H MOV M,B MOV B,A MOV A,B RLC RLC RLC RLC ADD B INX H MOV M,A HLT 0A

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L4 Add 64 to A

INR B JMP

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Subtract 0A from A Stop if A has carry

Stop if A has carry

Increment BC Jump to specified address

Increment HL Stop if A has no carry

Add 0A to A Increment HL Move B to M Move A to B Move B to A Rotate accumulator Rotate accumulator Rotate accumulator Rotate accumulator Add B to A Increment H by 1 Move content of A to M Stop the program 47

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OBSERVATION: A. ASCII TO HEXADECIMAL INPUT MEMORY DATA LOCATION 4201 B. HEXADECIMAL TO ASCII INPUT MEMORY DATA LOCATION 4201 OUTPUT MEMORY DATA LOCATION 4301 OUTPUT MEMORY DATA LOCATION 4301

4200

D. BINARY TO HEXADECIMAL INPUT MEMORY DATA LOCATION 4150 4151

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E. HEXADECIMAL TO DECIMAL INPUT MEMORY DATA LOCATION 4150 4151 OUTPUT MEMORY DATA LOCATION 4152

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MEMORY LOCATION 4200 4201 4202 4203 OUTPUT MEMORY DATA LOCATION 4152

INPUT MEMORY DATA LOCATION

OUTPUT DATA MEMORY DATA LOCATION 4204 4205 4206 4207

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C. HEXADECIMAL TO BINARY

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RESULT: Thus the assembly language programs for various code conversions are executed using 8085 microprocessor.

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EX.No:4
AIM:

4(a) INTERFACING A/D AND D/A CONVERTER WITH 8085

A. ADC INTERFACING WITH 8085 APPARATUS REQUIRED: SL.NO 1 2 3 ITEM Microprocessor kit Power supply ADC Interface board SPECIFICATION 8085,Vi Microsystems +5 V dc Vi Microsystems

To program starts from memory location 4100H. The program is executed for various values of analog voltage which are set with the help of a potentiometer. The LED display is verified with the digital value that is stored in the memory location 4150H. THEORY: An ADC usually has two additional control lines: the SOC input to tell the ADC when to start the conversion and the EOC output to announce when the conversion is complete. The following program initiates the conversion process, checks the EOC pin of ADC 0419 as to whether the conversion is over and then inputs the data to the processor. It also instructs the processor to store the converted digital data at RAM 4200H. ALGORITHM: 1. 2. 3. 4. 5. 6.

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Select the channel and latch the address. Send the start conversion pulse. Read EOC signal. If EOC =1 continue else go to step (3) Read the digital output. Store it in a memory location.

PROBLEM STATEMENT:

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QUANTITY 1 1 1

To write an assembly language program to convert an analog signal into a digital signal and a digital signal into an analog signal using an ADC interfacing and DAC interfacing respectively.

50

PROGRAM: ADDRESS 4100 4101 4102 4103 4104 4105 4106 4107 4108 4109 410A 410B 410C 410D 410E 410F 4110 4111 4112 4113 4114 4115 4116 4117 4118 4119 411A 411B 411C 411D 411E 411F 4120 4121 LABEL MNEMON ICS MVI A OPCO DE OPERA ND 10 COMMENTS Select channel 0 and to make accumulator low Output the data

OUT MVI A OUT MVI A OUT XRA XRA XRA MVI A OUT IN

0C8H C8 A, 18 18 0C8H C8 01

0D0H D0 A A A

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00 D0 D8 LOOP ANI CPI 01 01 01 01 JNZ LOOP IN STA C0 4150 HLT

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Make accumulator high Display the data Display the data Load D0 in output port Store the data End the program

Make 01 to accumulator

XOR with accumulator XOR with accumulator XOR with accumulator Make 00 to accumulator

Do and operation directly Compare with accumulator Jump to specified address

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ADC- CIRCUIT:

SOC JUMPER SELECTION:

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J2 : SOC Jumper selection J5 : Channel selection 52

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OBSERVATION ANALOG VOLTAGE DIGITAL DATA LED DISPLAY ON HEX CODE LOCATION 4150 IN

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4(b) DAC INTERFACING WITH 8085


APPARATUS REQUIRED: SL.NO 1 2 3 ITEM Microprocessor kit Power supply DAC Interface board SPECIFICATION 8085,Vi Microsystems +5 V dc Vi Microsystems QUANTITY 1 1 1

SOFTWARE EXAMPLES

(a) SQUARE WAVE GENERATION:

ALGORITHM: 1. 2. 3. 4. 5.

Load the initial value (00) to Accumulator and move it to DAC. Call the delay program Load the final value (FF) to accumulator and move it to DAC. Call the delay program. Repeat steps 2 to 5.

PROGRAM: ADDRESS 4100 4101 4102 4103 4104 4107 4109 410B 410E 4112 4114

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LABEL START MNEMON ICS MVI A OUT CALL DELAY MVI A OUT CALL DELAY JMP START MVI B MVI C OPC ODE 00 C8 DELAY L1

The basic idea behind the generation of waveforms is the continuous generation of Analog output of DAC. With 00(HEX) as input to DAC2, the analog output is -5V. Similarly, with FF (Hex) as input, the output is +5V. Outputting digital data 00 and FF at regular intervals, to DAC2, results in a square wave of amplitude I5 Volts

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OPERAND DELAY FF C8 DELAY START 05 FF

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The following examples illustrate how to control the DAC using 8085 and generate sine wave, saw tooth wave by means of software.

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COMMENT

Move 00 to A register Load C8 to output port Call delay program Load FF to B register

Jump to start of address Move 05 to B register Move FF to C register 54

4116 4117 411A 411B 411E

L2

DCR C JNZ L2 DCR B JNZ L1 RET

L2 L1

Decrement C Jump to L2 if no zero Decrement B register Jump to L1 if no zero

Execute the program and using a CRO, verify that the waveform at the DAC2 output is a square-wave. Modify the frequency of the square-wave, by varying the time delay. (b) SAW TOOTH GENERATION: ALGORITHM:

PROGRAM: ADDRESS 4100 4102 4104 4105 4108

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LABEL START L1 MNEMON ICS MVI A OUT INR A JNZ L1 JMP START

OPCO OPERAN DE D 00 C0 L1 START

ALGORITHM:

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1. Load the initial value (00) to Accumulator. 2. Move the accumulator content to DAC 3. Increment the accumulator content by 1. 4. If accumulator content is zero proceed to next step. Else go to step 3. 5. Load value (FF) to accumulator. 6. Move the accumulator content to DAC. 7. Decrement the accumulator content by 1. 8. If accumulator content is zero go to step 2. Else go to step 2. The following program will generate a triangular wave at DAC2 output. 55

(c) TRIANGULAR WAVE GENERATION:

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1. Load the initial value (00) to Accumulator 2. Move the accumulator content to DAC. 3. Increment the accumulator content by 1. 4. Repeat steps 3 and 4. Output digital data from 00 to FF constant steps of 01 to DAC1 repeat this sequence again and again. As a result a saw tooth wave will be generated at DAC1 output.

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COMMENT

Load 00 to accumulator Load CO in output port Increment A register Jump to L1 if no zero Go to START unconditionally

PROGRAM: ADDRESS LABEL START L1 MNEMON ICS MVI L MOV A,L OUT INR L JNZ L1 MVI L MOV A,L OUT DCR L JNZ L2 JMP START OPC ODE OPERA ND 00 C8 L1 FF C8 L2 START COMMENT Move 00 to L register Load L to a register Load c8 to output port Increment L register Jump to L1 if no zero Load FF to L register Move L to a register Load C8 to output port Decrement L register Jump to L2 if no zero Go to START unconditionally

L2

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DAC - CIRCUIT:

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WAEFORMS:

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OBSERVATION: WAVE FORMS Square waveform Saw tooth waveform Triangular waveform AMPLITUDE TIME PERIOD

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Result: Thus the conversion of an analog signal into a digital signal and a digital signal into an analog signal was done using interfacing of ADC and DAC respectively with 8085.

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EX.No:5
AIM

TRAFFIC LIGHT CONTROLLER WITH 8085

To write an assembly language program to simulate the traffic light at an intersection using a traffic light interface. APPARATUS REQUIRED: SL.NO 1 2 3 ITEM Microprocessor kit Power supply Traffic light interface kit SPECIFICATION 4185,Vi Microsystems +5 V dc Vi Microsystems

A SAMPLE SEQUENCE: 1. (a) Vehicles from south can go to straight or left. (b) Vehicles from west can cross the road. (c) Each pedestrian can cross the road. (d) Vehicles from east no movement. (e) Vehicles from north, can go only straight.

2. All ambers are ON, indicating the change of sequence. 3. (a) Vehicles from east can go straight and left. (b) Vehicles from south, can go only left. (c) North pedestrian can cross the road. (d) Vehicles from north, no movement. (e) Vehicles from west, can go only straight.

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4. All ambers are ON, indicating the change of sequence. 5. (a) Vehicles from north can go straight and left. (b) Vehicles from east, can go only left. (c) West pedestrian can cross the road. (d) Vehicles from west, no movement. (e) Vehicles from south, can go only straight. 6. All ambers are ON, indicating the change of sequence.

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ALGORITHM: 1. Initialize the ports. 2. Initialize the memory content, with some address to the data. 3. Read data for each sequence from the memory and display it through the ports. 4. After completing all the sequences, repeat from step2.

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QUANTITY 1 1 1

7. (a) Vehicles from west can go straight and left. (b) Vehicles from north, can go only left. (c) South pedestrian can cross the road. (d) Vehicles from south, no movement. (e) Vehicles from east, can go only straight. 8. All ambers are ON, indicating the change of sequence.

BIT ALLOCATION: BIT PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 LED SOUTH LEFT SOUTH RIGHT SOUTH AMBER SOUTH RED EAST LEFT EAST RIGHT EAST AMBER EAST RED BIT PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 LED NORTH LEFT NORTH RIGHT NORTH AMBER NORTH RED WEST LEFT WEST RIGHT WEST AMBER WEST RED

BIT

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PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7

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LED WEST STRAIGHT NORTH STRAIGHT EAST STRAIGHT SOUTH STRAIGHT NORTH PD WEST PD SOUTH PD EAST PD 60

9. (a) All vehicles from all directions no movement. (b) All pedestrian can cross the road.

PATH REPRESENTATION:

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CONTROL PORT A PORT B PORT C

-----------------

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0F ( FOR 8255 PPI ) 0C 0D 0E 61

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PROGRAM : ADDRESS 4100 LABEL MNEMON ICS MVI A, 41 OPCO OPER DE AND 3E 41 A,41 4102 4104 OUT CONTROL LXI H,DATA_SQ D3 0F COMMENT

410E 410F 4111 4114 4115 4116 4117 411A 411B 411C 411E 4121 4122 4123 4124 4127 4128

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MOV A,M 7E OUT PORT A CALL DELAY1 XCHG INX D INX H CALL OUT XCHG MOV A,M OUT PORT B CALL DELAY1 XCHG INX D INX H CALL OUT XCHG MOV A,M D3 CD EB 13 23 CD EB 7E D3 CD EB 13 23 CD EB 7E

410A 410D

CALL OUT XCHG

CD EB

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42,41 0C 66,41 42,41 0D 66,41 42,41

4107

LXI D,DATA_E

11

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Move 80 immediately to accumulator A,41 Output contents of accumulator to OF port Load address 417B to HL register Load address 4187 to DE register Call out address Exchange contents of HL with DE pair Move M content to accumulator Load port A into output port Call delay address Exchange content of HL with DE pair Increment the content of D Increment the content of H Call out the address Exchange content of HL with DE pair Move M content to accumulator Load port B into output port Call DELAY address Exchange content of HL with DE pair Increment D register Increment H register Call specified address Exchange content of HL with DE pair Move M content to accumulator 62

4129 412B 412E 412F 4130 4131 4134 4135 4136 4138 4139 413A 413C 413F 4142 4143 4145 4146 4147 4149 414A 414B 414D 4150 4151 4152 4155 4158 4159

OUT PORT C CALL DELAY1 XCHG INX D INX H CALL OUT XCHG MOV A,M OUT PORT C INX H MOV A,M OUT PORT A CALL DELAY1 JMP REPEAT MOV A,M OUT PORT C INX H MOV A,M OUT PORT B INX H MOV A,M

D3 CD EB 13 23 CD EB 7E D3 23 7E D3 CD C3 7E D3 23 7E D3 23 7E

0E 66,41

42,41

0E

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415A

415B 415E 415F

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0E 0D OUT PORT A CALL DELAY RET PUSH H LXI H,001F LXI B,FFFF DCX B MOV A,B ORA C JNZ LOOP DCX H MOV A,L D3 CD C9 E5 21 01 0B 78 B1 C2 2B 7D

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0C 51,41 1F,00 FF,FF 58,41

0C 66,41 04,41

Load port C into output port Call DELAY address Exchange content of HL with DE pair Increment D register Increment H register Call specified address Exchange content of HL with DE pair Move M content to accumulator Load port C into output port Increment H register Move M content to accumulator Load port A into output port Call DELAY address Jump to specified address Move M content to accumulator Load port C into output port Increment H register Move M content to accumulator Load port B into output port Increment H register Move M content to accumulator Load port A into output port Call DELAY address Return to accumulator Push the register H Load 00 1F in HL register pair Load FF FF in DE register pair Decrement B register Move B content to accumulator OR content of C with accumulator Jump to LOOP if no zero Decrement H register Move L content to accumulator 63

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4160 4161 4164 4165 4166 4167 416A 416D 416E 416F 4170 4173 4174 4175 4176 4179 417A 417B

ORA H JNZ L1 POP H RET PUSH H LXI H,001F LXI B,FFFF DCX B MOV A,B ORA C JNZ LOOP2 DCX H MOV A,L ORA H

B4 C2 E1 C9 E5 21 01 0B 78 B1 C2 2B 7D B4 55,41

OR content of H with accumulator Jump to L1 if no zero Pop the register H


Return from subroutine

1F,00 FF,FF

6D,41

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JNZ L2 POP H RET DATA 12 27 44 10 2B SEQ DB 92 10 9D 84 48 2E 84 48 4B 20 49 04 C2 E1 C9

6A,41

Push the register H Load 00 1F in HL register pair Load FF FF in DE register pair Decrement B register Move B content to accumulator OR content of C with accumulator Jump to LOOP2 if no zero Decrement H register Move L content to accumulator OR content of H with accumulator Jump to L2 if no zero Pop the register H
Return to subroutine

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RESULT:
Thus an assembly language program to simulate the traffic light at an intersection using a traffic light interfaces was written and implemented. 64

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EX.No:6
AIM:

6(a) INTERFACING 8251 WITH 8085

To write a program to initiate 8251 and to check the transmission and reception of character. APPARATUS REQUIRED: 1. 8085 Microprocessor kit 2. 8251 Interface board 3. DC regulated power supply THEORY:

Prior to starting data transmission or reception ,the 8251 must be loaded with a set of control words generated by the CPU.These control signals define the complete functional definition of the 8251 and must immediately follow a RESET operation. Control words should be written in to the control register of 8251. words should be written in to the control register of 8251.words should be written in to the control register of 8251.Thesecontrol words are split into two formats. 1. MODE INSTRUCTION WORD 2. COMMAND INSTRUCTION WORD. 1. MODE INSTRUCTION WORD

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This format defines the BAUD rate, character length, parity and stop bits required to work with asynchronous data communication. by selecting the appropriate BAUD factor synchronous mode, the 8251 can be operated in synchronous mode. Initializing 8251 using the Mode instructions to the following conditions. 8 bit data No parity Baud rate factor(16X) 1 stop bit Gives a mode command word of 01001110=4E(X)

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The 8251 is used as a peripheral device for serial communication and is programmed by the CPU to operate using virtually any serial data transmission technique. The USART accepts data characters from the CPU in parallel format and the converts them in a continuous serial data stream of transmission. Simultaneously, it can receive serial data streams and convert them into parallel data characters for the CPU. The CPU can read the status of USART at any time. These include data transmissions errors and control signals.

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PROGRAM: ADDRES S 4100 4102 4104 4106 4108 410A 410C 410F 4111 4113 4115 4117 4119 LA BE L MNEMON ICS MVI A OUT MVI A OUT MVI A OUT LXI H MVI A OUT MVI A OUT MVI A OUT RST1 IN STA RST1

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OPC OPE COMMENT ODE RAN D 36 Move 36 to A CE Output contents of accumulator to CE port 0A Move 0A to accumulator C8 Output contents of accumulator to C8 port 00 Move 00 to accumulator C8 Output contents of accumulator to C8 port 4200 Store 4200 address in HL register pair 4E Move 4E to accumulator C2 Output contents of accumulator to C2 port 37 Move 37 to accumulator C2 Output contents of accumulator to C2 port 41 Move 41 to accumulator C0 Output contents of accumulator to C0 port C0 4150

411B 4200 4202 4205

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Input the contents from port C0 to accumulator Store the output from accumulator to 4150

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ALGORITHM 1. Initialize timer (8253) IC 2. Move the Mode command word (4EH) to A reg. 3. Output it port address C2 4. Move the command instruction word (37H) to A reg. 5. Output it to port address C2 6. Move the data to be transfer to A reg. 7. Output it to port address C0. 8. Reset the system 9. Get the data through input port address C0. 10. Store the value in memory 11. Reset the system

SYNCHRONOUS MODE:

S2

S1

EP

PEN

L2

L1

B2

B1 0 0 5 BIT 1 0 6 BIT 0 1 7 BIT 1 1 8 BIT

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EVEN PARITY GENERATION 0-Odd 1-Even EXTERNAL SYNC DETECT 1-Sysdetect is an input 0- Sysdetect is an output SINGLE CHARACTER SYNC 1-Single sync character 0- Double sync character 67

PARITY ENABLE 1-Enable 0-Disable

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ASYNCHRONOUS MODE:

S2

S1

EP

PEN

L2

L1

B2

B1 0 0 1 0 0 1 1 1

Synch mode 0 0 5 BIT

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0 1

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1 0 61BIT

PARITY ENABLE 1-Enable 0-Disable

EVEN PARITY GENERATION 0-Odd 1-Even

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(1 X) 1 0 1 1 8 BIT 6 BIT 7 BIT 0 1 1.5BIT 1 1

(16 X) (64 X)

2 BIT

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OBSERVATION: MEMORY LOCATION INPUT DATA OUTPUT DATA

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RESULT:

Thus the program to initiate 8251 was written and the transmission and reception of character was checked by interfacing 8251 with 8085.

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6(b) INTERFACING 8253 TIMER WITH 8085


AIM: To interface 8253 Interface board to 8085 microprocessor to demonstrate the generation of square wave. APPARATUS REQUIRED: 1. 8085 microprocessor kit 2. 8253 Interface board 3. DC regulated power supply 4. CRO. . PROGRAM: Address 4100 4102 4104 4106 4108 410A 410C Opcodes 3E 36 D3 CE 3E 0A D3 C8 3E 00 D3 C8 76

Set the jumper, so that the clock 0 of 8253 is given a square wave of frequency 1.5 MHz. This program divides this PCLK by 10 and thus the output at channel 0 is 150 KHz. Vary the frequency by varying the count. Here the maximum count is FFFF H. So, the square wave will remain high for 7FFF H counts and remain low for 7FFF H counts. Thus with the input clock frequency of 1.5 MHz, which corresponds to a period of 0.067 microseconds, the resulting square wave has an ON time of 0.02184 microseconds and an OFF time of 0.02184 microseconds. To increase the time period of square wave, set the jumpers such that CLK2 of 8253 is connected to OUT 0. Using the above-mentioned program, output a square wave of frequency 150 KHz at channel 0. Now this is the clock to channel 2.

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Label Mnemonic Operands START: MVI A, 36 OUT CE MVI A, 0A OUT C8 MVI A, 00 OUT C8 HLT

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Comments Channel 0 in mode 3 Send Mode Control word LSB of count Write count to register MSB of count Write count to register 70

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CONTROL WORD: SC1 SC2 RW1 RW0 M2 M1 M0 BCD

SC-SELECT COUNTER:

0 0 1 1

0 1 0 1

Select counter 0 Select counter 1 Select counter 2 Read back command

M-MODE: M2 0 0 X X 1 1 M1 0 0 1 1 0 0 M0 0 1 0 1 0 1 MODE Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5

READ/WRITE: RW1 0 0 1 1 RW0 0 1 0 1

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BCD:

0 1

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Counter latch command R/W least significant bit only R/W most significant bit only R/W least sig first and most sig byte Binary counter 16-bit Binary coded decimal counter 71

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SC1

SC0

SELECT COUNTER

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Result: Thus the 8253 has been interfaced to 4185 p and six different modes of 8253 have been studied.

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6(c) INTERFACING 8279 WITH 8085

AIM: To interface 8279 Programmable Keyboard Display Controller to 8085 Microprocessor.

1. 8085 Microprocessor toolkit. 2. 8279 Interface board 3. Regulated D.C. power supply.

PROGRAM: ADDRESS 4100 4103 4105 4107 LABEL START MNEMON ICS LXI H

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MVI D MVI A OUT MVI A OUT

4109 410B 410D 410F 4111 4112 4114 4117 4118

MVI A OUT

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LOOP

MOV A, M OUT CALL DELAY INX H DCR D D C0H C0 DELAY DELAY

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OPCO DE 4130 H, 4130H D, 0FH 0F 10 C2 C2H A,CC 90H C2 A,90 90H C2 C2H

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OPERA COMMENT ND Store the 16 bit address in HL pair Move 0F to D register Move 10 to A Output the contents of A to C2 output port Move CC to A Output the contents of A to C2 output port Move 90 to A Output the contents of A to C2 output port Move content of M to A Output the contents of M to A Call the delay address Increment H register Decrement D register 73

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APPARATUS REQUIRED:

4119 411C 411F 4121 4123 4124 4127 4128 412B DELAY LOOP1 LOOP2

JNZ LOOP JMP START MVI B MVI C DCR C JNZ LOOP 1 DCR B JNZ LOOP 2 RET

LOOP START START A0 FF

Jump to specified address Jump to START address Move a to B register Move FF to C register

LOOP 1

Pointer equal to 4130 .FF repeated eight times 4130 4131 4132 4133 4134 4135 4136 4137 4138 4139 413 413B 413C 413D 413E 413F FF FF FF FF FF FF FF FF 98 68 7C C8 1C 29 FF FF

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Decrement C register Jump to LOOP 1 if no zero Decrement B register Jump to LOOP 2 if no zero

SEGMENT DEFINITION:

DATA BUS SEGMETS

D7 d

D6 c

D5 D4 b a

D3 D2 D1 D0 dp g f e

OBSERVATION:

LETTER 7 SEGMENT

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DATA BUS D3 D7 D6 D5 D4

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RESULT:

Thus 8279 controller was interfaced with 8085 and program for rolling display was executed successfully.

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HEXADECIMAL D2 D1 D0 75

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MICROCONTROLLER

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Ex.No:7
AIM:

7(a) 8051 - SUM OF ELEMENTS IN AN ARRAY

To find the sum of elements in an array.

1.

Load the array in the consecutive memory location and initialize the memory pointer with the starting address.

2. 3. 4. 5. 6.

Load the total number of elements in a separate register as a counter. Clear the accumulator.

Load the other register with the value of the memory pointer. Add the register with the accumulator.

Check for carry, if exist, increment the carry register by 1. otherwise, continue

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7. memory pointer by 1 and go to step 4.

Decrement the counter and if it reaches 0, stop. Otherwise increment the

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ALGORITHM:

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PROGRAM: ADDRESS OPCODE LABEL MNEMONICS 4100 MOV 4103 4104 4105 4108 410A 410B 410C 410D 410F 4111 4113 4114 4116 4119 411A 411B 411C 411E 411F ADD MOVX MOV MOV MOV CLR C INC DPTR MOVX ADD MOV JNC INC INC OPERAND DPTR, #4200 A, @DPTR COMMENT

B, #00 R1, B C3 A3

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NC R1 NC MOV MOV MOVX INC MOV MOVX SJMP

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A, B B, A DPTR DPTR, #4500 A, R1 @DPTR, A DPTR A, B @DPTR, A HLT 78

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R0, A

OBSERVATION:

INPUT 4200 4201 4202 4203 4501 4500

OUTPUT

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RESULT: The sum of elements in an array is calculated.

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7(b) 8051 - SUM USING STACK


AIM: To find the sum of elements in an array using stack. ALGORITHM: 1. Start 2. Move the data to stack pointer 3. Move the data to accumulator 4. Move the data to reg B 5. Move the data to DPL 6. Push the value of A to stack 7. Push the value of B to stack

8. Push the value of DPL to stack 9. Halt

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PROGRAM: ADDRESS OPCODE LABEL MNEMONICS 4100 MOV SP, #67 4103 4105 4108 410B 410D 410F 4111 MOV A, #88 MOV B, #66 MOV DPL, #43 PUSH A PUSH B PUSH DPL SJMP OPERAND 67 88 COMMENT

43

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RESULT: The sum of elements in an array is calculated. 81

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7(c) 8051 - SUM USING CALL OPTION


AIM: To find the sum of elements in an array using call option. ALGORITHM: 1. Start 2. Move the data to DPTR 3. Move the data to accumulator 4. Adjacent call 4200 5. Add A & R0 6. Move the 16 bit data from A to DPTR 7. Move the data to accumulator 8. Move the data to R0 9. Return to 4107

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PROGRAM: ADDRESS OPC ODE 4100 4103 4105 4108 410B 410D 410F 4111 LABEL MNEMONICS MOV DPTR,# 4300 MOV A, # 00 ACALL 4200 ADD A, R0 MOVX @DPTR,A SJMP MOVA,#02 MOV R0, #01 RET 80 OPERAND 43,00 COMMENT

42,00

OBSERVATION:

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INPUT 4300

4200 4202

RESULT: The sum of elements in an array using call option is calculated is calculated.

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OUTPUT 83

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00

Ex.No:8 AIM:

8(a) STEPPER MOTOR INTERFACING WITH 8051

To interface a stepper motor with 8051 microcontroller and operate it. THEORY: A motor in which the rotor is able to assume only discrete stationary angular position is a stepper motor. The rotary motion occurs in a step-wise manner from one equilibrium position to the next. Stepper Motors are used very wisely in position control systems like printers, disk drives, process control machine tools, etc. The basic two-phase stepper motor consists of two pairs of stator poles. Each of the four poles has its own winding. The excitation of any one winding generates a North Pole. A South Pole gets induced at the diametrically opposite side. The rotor magnetic system has two end faces. It is a permanent magnet with one face as South Pole and the other as North Pole. The Stepper Motor windings A1, A2, B1, B2 are cyclically excited with a DC current to run the motor in clockwise direction. By reversing the phase sequence as A1, B2, A2, B1, anticlockwise stepping can be obtained.

ANTICLOCKWISE STEP A1 A2 B1

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B2 DATA

2-PHASE SWITCHING SCHEME: In this scheme, any two adjacent stator windings are energized. The switching scheme is shown in the table given below. This scheme produces more torque.
CLOCKWISE STEP A1 A2

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B1

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B2

1 2 3 4

1 0 0 1

0 1 1 0

0 0 1 1

1 1 0 0

9h 5h 6h Ah

1 2 3 4

1 0 0 1

0 1 1 0

ADDRESS DECODING LOGIC: The 74138 chip is used for generating the address decoding logic to generate the device select pulses, CS1 & CS2 for selecting the IC 74175.The 74175 latches the data bus to the stepper motor driving circuitry. Stepper Motor requires logic signals of relatively high power. Therefore, the interface circuitry that generates the driving pulses use silicon darlington pair transistors. The inputs for the interface circuit are TTL pulses generated under software control using the Microcontroller Kit. The TTL levels of pulse sequence from the data bus is translated to high voltage output pulses using a buffer 7407 with open collector.

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DATA

1 1 0 0

0 0 1 1

Ah 6h 5h 9h

84

BLOCK DIAGRAM:

8051 MICROCONTROLLER

8255

DRIVER CIRCUIT

REPRESENTATION:

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STEPPER MOTOR

PROGRAM : Address OPCODES Label MNEM ONICS ORG OPERAND 4100h DPTR, #TABLE Load the start address of switching scheme data TABLE into Data Pointer (DPTR) Load the count in R0 Load the number in TABLE into A Push DPTR value to Stack Load the Motor port address into DPTR Send the value in A to stepper Motor port address Delay loop to cause a specific amount of time delay before next data item is sent to the Motor Comments

4100

START MOV

4103 4105 4106 4108 410A 410D

LOOP:

MOV MOVX PUSH PUSH MOV MOVX

R0, #04 A, @DPTR DPH DPL DPTR, #0FFC0h @DPTR, A

410E 4110 4112 4114 4116 4118 411A

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DELA Y: DELA Y1: MOV MOV R4, #0FFh R5, #0FFh DJNZ DJNZ POP POP INC R5, DELAY1 R4, DELAY DPL DPH DPTR

411D

411B

DJNZ SJMP

R0, LOOP START

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411F

TABLE DB :

09 05 06 0Ah

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POP back DPTR value from Stack Increment DPTR to point to next item in the table Decrement R0, if not zero repeat the loop Short jump to Start of the program to make the motor rotate continuously Values as per twophase switching scheme 86

PROCEDURE: 1. Enter the above program starting from location 4100.and execute the same. 2. The stepper motor rotates. 3. Varying the count at R4 and R5 can vary the speed. 4. Entering the data in the look-up TABLE in the reverse order can vary direction of rotation.

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RESULT: Thus a stepper motor was interfaced with 8051 and run in forward and reverse directions at various speeds.

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8 (b) INTERFACING D/A CONVERTER WITH 8051


AIM: To interface DAC with 8051 to demonstrate the generation of square, saw tooth and triangular wave. APPARATUS REQUIRED: SL.NO 1 2 3 THEORY: SOFTWARE EXAMPLES ITEM Microprocessor kit Power supply DAC Interface board SPECIFICATION 4185,Vi Microsystems +5 V dc Vi Microsystems

ALGORITHM:

(a) SQUARE WAVE GENERATION: 1. Load the initial value (00) to Accumulator and move it to DAC. 2. Call the delay program 3. Load the final value (FF) to accumulator and move it to DAC. 4. Call the delay program. 5. Repeat steps 2 to 5.

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After going through the software examples you can learn how to control the DAC using 8051 and generate sine wave, saw tooth wave etc by means of software.

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QUANTITY 1 1 1

DAC - CIRCUIT:

WAVEFORMS:

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89

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OBSERVATION: WAVE FORMS Square waveform Saw tooth waveform Triangular waveform AMPLITUDE TIME PERIOD

ADDRESS

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MNEMON ICS OPCODE OPERAND COMMENT MOV DPTR,#FFC8 START MOV A,#00 MOVX @DPTR,A LCALL DELAY MOV A,# FF MOVX @DPTR,A LCALL DELAY LJMP START DELAY MOV R1,#05 LOO[P MOV R2,#FF DJNZ R2,HERE DJNZ R1,LOOP RET SJMP START Execute the program and using a CRO, verify that the waveform at the DAC2 output is a square-wave. Modify the frequency of the square-wave, by varying the time delay. (b) SAW TOOTH GENERATION 1. Load the initial value (00) to Accumulator 2. Move the accumulator content to DAC. 3. Increment the accumulator content by 1. 4. Repeat steps 3 and 4. Output digital data from 00 to FF constant steps of 01 to DAC1 repeat this sequence again and again. As a result a saw tooth wave will be generated at DAC1 output.

LABEL

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PROGRAM: The basic idea behind the generation of waveforms is the continuous generation of Analog output of DAC. With 00(HEX) as input to DAC2, the analog output is -5V. Similarly, with FF (Hex) as input, the output is +5V. Outputting digital data 00 and FF at regular intervals, to DAC2, results in a square wave of amplitude I5 Volts.

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90

PROGRAM: ADDRESS LABEL MNEMON ICS MOV DPTR,#FFC0 MOV A,#00 MOVX @DPTR,A INC A SJMP LOOP OPCODE OPERAND COMMENT

LOOP

The following program will generate a triangular wave at DAC2 output. The program is self explanatory. ADDRESS LABEL START LOOP1 MNEMON ICS MOV DPTR,#FFC8 MOV A,#00 MOVX @DPTR,A INC A JNZ LOOP1 MOV A,#FF MOVX @DPTR,A DEC A JNZ LOOP2 LJMP START OPCODE OPERAND COMMENT

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OBSERVATION: WAVE FORMS Square waveform Saw tooth waveform Triangular waveform AMPLITUDE TIME PERIOD

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LOOP2

(c) TRIANGULAR WAVE GENERATION 1. Load the initial value (00) to Accumulator. 2. Move the accumulator content to DAC 3. Increment the accumulator content by 1. 4. If accumulator content is zero proceed to next step. Else go to step 3. 5. Load value (FF) to accumulator. 6. Move the accumulator content to DAC. 7. Decrement the accumulator content by 1. 8. If accumulator content is zero go to step 2. Else go to step 2.

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Result: Thus the square, triangular and saw tooth wave form were generated by interfacing DAC with 8051 trainer kit.

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Ex. No: 9

STUDY OF BASIC DIGITAL ICS

AIM: To verify the truth table of basic digital ICs of AND, OR, NOT, NAND, NOR, EX-OR gates. APPARATUS REQUIRED: S.No 1. 2. 3. 4. 5. 6. 7. 8. Name of the Apparatus Digital IC trainer kit AND gate OR gate NOT gate NAND gate NOR gate EX-OR gate IC 7408 IC 7432 IC 7404 IC 7400 IC 7402 IC 7486

Range

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As required

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Connecting wires

THEORY:

a. AND gate:

b. OR gate:

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c. NOT gate:

An AND gate is the physical realization of logical multiplication operation. It is an electronic circuit which generates an output signal of 1 only if all the input signals are 1.

An OR gate is the physical realization of the logical addition operation. It is an electronic circuit which generates an output signal of 1 if any of the input signal is 1.

A NOT gate is the physical realization of the complementation operation. It is an electronic circuit which generates an output signal which is the reverse of the input signal. A NOT gate is also known as an inverter because it inverts the input.

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1 1 1 1 1 1 1

Quantity

93

d. NAND gate: A NAND gate is a complemented AND gate. The output of the NAND gate will be 0 if all the input signals are 1 and will be 1 if any one of the input signal is 0. e. NOR gate: A NOR gate is a complemented OR gate. The output of the OR gate will be 1 if all the inputs are 0 and will be 0 if any one of the input signal is 1. f. EX-OR gate:

B = ( A . B ) + ( A . B )

PROCEDURE:

1. Connections are given as per the circuit diagram 1. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply. 2. Apply the inputs and verify the truth table for all gates. AND GATE

LOGIC DIAGRAM:

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It is similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive OR is a function that give an output signal 0 when the two input signals are equal either 0 or 1.

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An Ex-OR gate performs the following Boolean function,

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PIN DIAGRAM OF IC 7408:

CIRCUIT DIAGRAM:

TRUTH TABLE:

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LOGIC DIAGRAM:

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S.No 1. 2. 3. 4. INPUT A 0 0 1 1 B 0 1 0 1 OUTPUT Y=A.B 0 0 0 1 OR GATE 95

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PIN DIAGRAM OF IC 7432 :

CIRCUIT DIAGRAM:

TRUTH TABLE:

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LOGIC DIAGRAM:

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S.No 1. 2. 3. 4. INPUT A 0 0 1 1 B 0 1 0 1 OUTPUT Y=A+B 0 1 1 1 NOT GATE 96

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PIN DIAGRAM OF IC 7404 :

TRUTH TABLE:

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LOGIC DIAGRAM:

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S.No 1. 2. INPUT A 0 1 OUTPUT Y = A 1 0 NAND GATE 97

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CIRCUIT DIAGRAM:

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PIN DIAGRAM OF IC 7400 :

CIRCUIT DIARAM:

TRUTH TABLE:

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S.No 1. 2. 3. 4. INPUT A 0 0 1 1 B 0 1 0 1 OUTPUT Y = (A. B) 1 1 1 0 98

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NOR GATE LOGIC DIAGRAM:

PIN DIAGRAM OF IC 7402 :

CIRCUIT DIAGRAM:

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TRUTH TABLE:

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S.No 1. 2. 3. 4. INPUT A 0 0 1 1 B 0 1 0 1 OUTPUT Y = (A + B) 1 0 0 0 99

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EX-OR GATE LOGIC DIAGRAM

PIN DIAGRAM OF IC 7486:

CIRCUIT DIAGRAM:

TRUTH TABLE:

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S.No 1. 2. 3. 4. INPUT A 0 0 1 1 B 0 1 0 1 OUTPUT Y=A B 0 1 1 0 100

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RESULT: The truth tables of all the basic digital ICs were verified. .

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101

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EX.NO.10 AIM:

DESIGN AND IMPLEMENTATION OF ADDER/SUBTRACTOR

To design and construct half adder, full adder, half subtractor and full subtractor circuits and verify the truth table using logic gates. APPARATUS REQUIRED: S. No 1. 2. 3. IC Digital IC Trainer Kit Patch chords Name Specification

7432, 7408, 7486, 7483

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0+0=0 0+1=1 1+0=1 1 + 1 = 102

THEORY:

The first three operations produce a sum of whose length is one digit, but when the last operation is performed the sum is two digits. The higher significant bit of this result is called a carry and lower significant bit is called the sum. HALF ADDER:

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A combinational circuit which performs the addition of two bits is called half adder. The input variables designate the augend and the addend bit, whereas the output variables produce the sum and carry bits. FULL ADDER:

A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented with two half adders and one OR gate.

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The most basic arithmetic operation is the addition of two binary digits. There are four possible elementary operations, namely,

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Quantity 1 1 102

HALF ADDER TRUTH TABLE: S.No 1. 2. 3. 4. DESIGN: INPUT A 0 0 1 1 B 0 1 0 1 S 0 1 1 0 OUTPUT C 0 0 0 1

CIRCUIT DIAGRAM:

TRUTH TABLE:

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FULL ADDER S.No 1. 2. 3. 4. 5. 6. 7. 8. A 0 0 0 0 1 1 1 1 INPUT B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 OUTPUT SUM CARRY 0 0 1 0 1 0 0 1 1 0 0 1 0 1 1 1 103

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From the truth table the expression for sum and carry bits of the output can be obtained as, Sum, S = A B ; Carry, C = A . B

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DESIGN: From the truth table the expression for sum and carry bits of the output can be obtained as,SUM = ABC + ABC + ABC + ABC;CARRY = ABC + ABC + ABC +ABC Using Karnaugh maps the reduced expression for the output bits can be obtained as, SUM

SUM = ABC + ABC + ABC + ABC = A CARRY

CIRCUIT DIAGRAM:

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CARRY = AB + AC + BC 104

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B C

HALF SUBTRACTOR: A combinational circuit which performs the subtraction of two bits is called half subtractor. The input variables designate the minuend and the subtrahend bit, whereas the output variables produce the difference and borrow bits. FULL SUBTRACTOR:

HALF SUBTRACTOR

TRUTH TABLE: S.No 1. 2. 3. 4. INPUT A 0 0 1 1 B 0 1 0 1

DESIGN:

From the truth table the expression for difference and borrow bits of the output can be obtained as, Difference, DIFF = A B; Borrow, BORR = A . B CIRCUIT DIAGRAM:

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OUTPUT DIFF BORR 0 0 1 1 1 0 0 0 105

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A combinational circuit which performs the subtraction of three input bits is called full subtractor. The three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be implemented with two half subtractors and one OR gate.

FULL SUBTRACTOR TRUTH TABLE: S.No 1. 2. 3. 4. 5. 6. 7. 8. DESIGN: INPUT B 0 0 1 1 0 0 1 1 OUTPUT DIFF BORR 0 0 1 1 1 1 0 1 1 0 0 0 0 0 1 1

Using Karnaugh maps the reduced expression for the output bits can be obtained as, DIFFERENCE

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BORR = AB + AC + BC

Difference, DIFF= ABC + ABC + ABC + ABC Borrow, BORR = ABC + ABC + ABC +ABC

DIFF = ABC + ABC + ABC + ABC = A

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B

From the truth table the expression for difference and borrow bits of the output can be obtained as,

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BORROW

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C

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106

A 0 0 0 0 1 1 1 1

C 0 1 0 1 0 1 0 1

CIRCUIT DIAGRAM:

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RESULT:

Thus the half adder, full adder, half subtractor and full subtractor circuits were designed and their truth table were verified.

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The connections are given as per the circuit diagram. Two 4 bit numbers added or subtracted depend upon the control input and the output is obtained. Apply the inputs and verify the truth table for thehalf adder or s subtractor and full adder or subtractor circuits.

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PROCEDURE:

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EX.NO.11
AIM:

11(a) CODE CONVERTER

To construct and verify the performance of binary to gray and gray to binary.

S. No 1. 2. 3. IC

Name

Specification 7404, 7486

Digital IC Trainer Kit Patch chords

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BINARY TO GRAY:

The MSB of the binary code alone remains unchanged in the Gray code. The remaining bits in the gray are obtained by EX-OR ing the corresponding gray code bit and previous bit in the binary code. The gray code is often used in digital systems because it has the advantage that only one bit in the numerical representation changes between successive numbers.

GRAY TO BINARY:

obtained by EX OR ing the corresponding gray code bit and the previous output binary bit.

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PROCEDURE:

The MSB of the Gray code remains unchanged in the binary code the remaining bits are

Connections are given as per the logic diagram. The given truth tables are verified.

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THEORY:

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Quantity 1 1 108

APPARATUS REQUIRED:

BINARY TO GRAY:

GRAY TO BINARY

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109

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TRUTH TABLE Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 D 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Binary code C B A 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Gray code G2 G1 0 0 0 0 0 1 0 1 1 1 1 1 1 0 1 0 1 0 1 0 1 1 1 1 0 1 0 1 0 0 0 0

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RESULT:

converter circuits was done and its truth table was verified.

The design of the three bit Binary to Gray code converter & Gray to Binary code

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G3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

GO 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0

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11(b) ENCODER
AIM: To design and implement encoder using IC 74148 (8-3 encoder) APPARATUS REQUIRED:

1. 2. 3.

IC Digital IC Trainer Kit Patch chords

74148

An encoder is digital circuit that has 2n input lines and n output lines. The output lines

for each of the octal digits and three outputs that generate the corresponding binary number. Enable inputs E1 should be connected to ground and Eo should be connected to VCC

PROCEDURE:

Connections are given as per the logic diagram.

The truth table is verified by varying the inputs.

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PIN DIAGRAM

1 2

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ENCODER

generate a binary code corresponding to the input values 8 3 encoder circuit has 8 inputs, one

2N INPUT

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THEORY:

N-1

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1 1 N OUTPUT

S. No

Name

Specification

Quantity

111

TRUTH TABLE
E1 0 0 0 0 0 0 0 0 1 A0 0 1 1 1 1 1 1 1 1 A1 1 0 1 1 1 1 1 1 1 A2 1 1 0 1 1 1 1 1 1 INPUTS A3 A4 1 1 1 1 1 1 0 1 1 0 1 1 1 1 1 1 1 1 A5 1 1 1 1 1 0 1 1 1 A6 1 1 1 1 1 1 0 1 1

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A7 1 1 1 1 1 1 1 0 1

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OUTPUTS D2 D1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 1 1 D0 0 1 0 1 0 1 0 1 1 112

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11(c) DECODER
AIM: To design and implement decoder using IC 74155 (3-8 decoder). APPARATUS REQUIRED:

S. No 1. 2. 3.

Name IC Digital IC Trainer Kit Patch chords

Specification 74155

THEORY: to 2n unique output lines.

A decoder is a combinational circuit that converts binary information from n input lines

In 3-8 line decoder the three inputs are decoded into right outputs in which each output representing one of the minterm of 3 input variables. IC 74155 can be connected as a dual 2*4 decoder or a single 3*8 decoder desired input in C1 and C2 must be connected together and used as the C input. G1 and G2 should be connected and used as the G (enable) input. G is the enable input and must be equal to 0 for proper operation. PROCEDURE:

Connections are given as per the logic diagram.

The truth table is verified by varying the inputs. CIRCUIT DIAGRAM:

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1 2

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DECODER

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N INPUT

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Quantity 1 1 113

TRUTH TABLE INPUTS C B X X 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1

G 1 0 0 0 0 0 0 0 0

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A X 0 1 0 1 0 1 0 1 2Y0 1 0 1 1 1 1 1 1 1 2Y1 1 1 0 1 1 1 1 1 1 2Y2 1 1 1 0 1 1 1 1 1

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OUTPUTS 2Y3 1Y0 1 1 1 1 1 1 1 1 0 1 1 0 1 1 1 1 1 1 1Y1 1 1 1 1 1 1 0 1 1 1Y2 1 1 1 1 1 1 1 0 1 1Y3 1 1 1 1 1 1 1 1 0 114

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RESULT: Thus the encoder and decoder circuits were designed and implemented.

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EX.NO.12 AIM:

STUDY OF FLIP FLOPS

To verify the characteristic table of RS, D, JK, and T Flip flops . APPARATUS REQUIRED: S.No 1. 2. 3. 4. 5. 6. Name of the Apparatus Digital IC trainer kit NOR gate NOT gate AND gate ( three input ) NAND gate Connecting wires Range IC 7402 IC 7404 IC 7411 IC 7400

RS FLIP FLOP:

The clocked RS flip flop consists of NAND gates and the output changes its state with respect to the input on application of clock pulse. When the clock pulse is high the S and R inputs reach the second level NAND gates in their complementary form. The Flip Flop is reset when the R input high and S input is low. The Flip Flop is set when the S input is high and R input is low. When both the inputs are high the output is in an indeterminate state. D FLIP FLOP:

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To eliminate the undesirable condition of indeterminate state in the SR Flip Flop when both inputs are high at the same time, in the D Flip Flop the inputs are never made equal at the same time. This is obtained by making the two inputs complement of each other. JK FLIP FLOP:

The indeterminate state in the SR Flip-Flop is defined in the JK Flip Flop. JK inputs behave like S and R inputs to set and reset the Flip Flop. The output Q is ANDed with K input and the clock pulse, similarly the output Q is ANDed with J input and the Clock pulse. When the clock pulse is zero both the AND gates are disabled and the Q and Q output retain their previous values. When the clock pulse is high, the J and K inputs reach the NOR gates. When both the inputs are high the output toggles continuously. This is called Race around condition and this must be avoided. T FLIP FLOP: 115

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A Flip Flop is a sequential device that samples its input signals and changes its output states only at times determined by clocking signal. Flip Flops may vary in the number of inputs they possess and the manner in which the inputs affect the binary states.

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THEORY:

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As required

Quantity 1

This is a modification of JK Flip Flop, obtained by connecting both inputs J and K inputs together. T Flip Flop is also called Toggle Flip Flop. RS FLIP FLOP LOGIC SYMBOL:

CIRCUIT DIAGRAM:

CHARACTERISTIC TABLE: CLOCK PULSE 1 2 3 4 5 6 7 8

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INPUT R 0 0 1 1 0 0 1 1 S 0 0 0 0 1 1 1 1 PRESENT STATE (Q) 0 1 0 1 0 1 0 1 D FLIP FLOP NEXT STATE(Q+1) 0 1 0 0 1 1 X X STATUS 116

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LOGIC SYMBOL:

CIRCUIT DIAGRAM:

CHARACTERISTIC TABLE: CLOCK PULSE 1 2 3 4

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INPUT D 0 0 1 1 PRESENT STATE (Q) 0 1 0 1 NEXT STATE(Q+1) 0 0 1 1 STATUS 117

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JK FLIP FLOP LOGIC SYMBOL:

CIRCUIT DIAGRAM:

CHARACTERISTIC TABLE: CLOCK PULSE 1 2 3 4 5 6 7 8

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INPUT K 0 0 1 1 0 0 1 1 J 0 0 0 0 1 1 1 1 PRESENT STATE (Q) 0 1 0 1 0 1 0 1 NEXT STATE(Q+1) 0 1 0 0 1 1 1 0 STATUS 118

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T FLIP FLOP LOGIC SYMBOL:

CIRCUIT DIAGRAM:

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CHARACTERISTIC TABLE: CLOCK PULSE 1 2 3 4 INPUT T 0 0 1 1 PRESENT STATE (Q) 0 1 0 1 NEXT STATE(Q+1) 0 0 1 0 STATUS

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PROCEDURE: 1. Connections are given as per the circuit diagrams. 2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply. 3. Apply the inputs and observe the status of all the flip flops.

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RESULT:

The Characteristic tables of RS, D, JK, T flip flops were verified.

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EX.NO.13 AIM:

13(a)ASYNCHRONOUS COUNTER

To implement and verify the truth table of an asynchronous decade counter. APPARATUS REQUIRED: S.No 1. 2. 4. 5. Name of the Apparatus Digital IC trainer kit JK Flip Flop NAND gate Connecting wires Range IC 7473 IC 7400

THEORY:

PIN DIAGRAM OF IC 7473:

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Asynchronous decade counter is also called as ripple counter. In a ripple counter the flip flop output transition serves as a source for triggering other flip flops. In other words the clock pulse inputs of all the flip flops are triggered not by the incoming pulses but rather by the transition that occurs in other flip flops. The term asynchronous refers to the events that do not occur at the same time. With respect to the counter operation, asynchronous means that the flip flop within the counter are not made to change states at exactly the same time, they do not because the clock pulses are not connected directly to the clock input of each flip flop in the counter.

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Quantity 1 2 1 As required 121

CIRCUIT DIAGRAM:

TRUTH TABLE: S.No 1 2 3 4 5 6 7 8 9 10 11

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CLOCK PULSE 1 2 3 4 5 6 7 8 9 10 D(MSB) 0 0 0 0 0 0 0 0 1 1 0 C 0 0 0 0 1 1 1 1 0 0 0

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OUTPUT B 0 0 1 1 0 0 1 1 0 1 0 A(LSB) 0 1 0 1 0 1 0 1 0 0 0

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PROCEDURE: 1. Connections are given as per the circuit diagrams. 2. Apply the input and verify the truth table of the counter. 122

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RESULT: The truth table of the Asynchronous counter was hence verified.

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EX.NO.13 AIM:

13(b) SHIFT REGISTERS

To implement the following shift register using flip flop (i) (ii) (iii) (iv) SIPO SISO PISO PIPO

APPARATUS REQUIRED: S. No 1. 2. 3. IC Digital IC Trainer Kit Patch chords Name

Specification 7474

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THEORY:

A register is used to move digital data. A shift register is a memory in which information is shifted from one position in to another position at a line when one clock pulse is applied. The data can be shifted either left or right direction towards right or towards left. A shift register can be used in four ways depending upon the input in which the data are entered in to and takes out of it. The four configuration are given as Serial input Serial output Parallel input Serial output

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PROCEDURE:

Serial input Parallel output Parallel input Parallel output

RS or JK flip flop are used to construct shift register have D flip flop is used for constructing shift register. Give the connections as per the circuit Set or Reset at the pin 2 which its the MSB of serial data. Apply a single clock Set or Reset second digital input at pin 2. Repeat step 2 until all 4-bit data are taken away.

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Quantity 1 1 124

SHIFT REGISTER:
_
+5VCC CLR2
D2 CLK PR2 Q2 Q2

14

13

12

11

10

IC 7474
1 2 3 4 5 6

CLR1

D1

CLK

PR1

Q1

_
Q1

SIPO LEFT SHIFT


Q3

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Q0 10 4 5 2 9 12

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+5VCC Q2 Q1 4 2 5 D IN

10 9 IC 7474 13

12 11

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IC 7474
1

IC 7474
13

11

SIPO RIGHT SHIFT

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7
GND
IC 7474
1 3 +5VCC CLK

125

SISO
DOUT

+5VCC

10 12 9 IC 7474 11 13 5

4 2 9

10

12

IC 7474
3 1

IC 7474
13 11

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Q2 Q1 Q0

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+5VCC CLK

PIPO

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Q2

SISO Data input = 1100

Clock 0 4 8 12 16

Serial input 0 1 1 0 0

Serial output 0 1 1 0 0 126

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4 5 2 D IN

IC 7474
1

PIPO Clock A 0 1 Parallel input B 0 1 C 0 0 D 0 1 QA 0 1 Parallel output QB 0 1 QC 0 0 QD 0 1

0 1

SIPO Left shift No of clk pulse 0 1 2 3 4 5 6 7 8 Serial input Din 0 1 1 0 1 0 0 0 0

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1 1 0 1 0 No of clock pulse 0 1 2 3 4 5 6 7 8 Serial input Din 0 1 1 0 1 0 0 0 0 1 0 0 0 0

Right Shift

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1 0 1 0 0 0 1 0 0 0 1 1 0 0 0 0 1 1 0 0

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Parallel output Q3 Q2 Q1 0 0 0 0 0 0 0 0 1 0 1 1 Q0 0 1 1 0 1 0 0 0 0 Parallel output Q3 Q2 Q1 Q0 0 0 0 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0 127

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RESULT:

Thus the SISO, SIPO, PISO, PIPO shift registers were designed and implemented.

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EX.NO.14

14(a) DIFFERENTIATOR

AIM: To design a Differentiator circuit for the given specifications using Op-Amp IC 741.

As required

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THEORY: The differentiator circuit performs the mathematical operation of differentiation; that is, the output waveform is the derivative of the input waveform. The differentiator may be constructed from a basic inverting amplifier if an input resistor R 1 is replaced by a capacitor C1. The expression for the output voltage is given as, Vo = - Rf C1 (dVi /dt) Here the negative sign indicates that the output voltage is 180 0 out of phase with the input signal. A resistor Rcomp = Rf is normally connected to the non-inverting input terminal of the op-amp to compensate for the input bias current. A workable differentiator can be designed by implementing the following steps: 1. Select fa equal to the highest frequency of the input signal to be differentiated. Then, assuming a value of C1 < 1 F, calculate the value of Rf. 2. Choose fb = 20 fa and calculate the values of R1 and Cf so that R1C1 = Rf Cf. 3. The differentiator is most commonly used in waveshaping circuits to detect high frequency components in an input signal and also as a rateofchange detector in FM modulators. PIN DIAGRAM:

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S.No 1. 2. 3. 4. 5. 6. 7. 8.

Name of the Apparatus Function Generator CRO Dual RPS Op-Amp Bread Board Resistors Capacitors Connecting wires and probes

Range 3 MHz 30 MHz 0 30 V IC 741

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Quantity 1 1 1 1 1

APPARATUS REQUIRED:

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DESIGN: Given fa = --------------We know the frequency at which the gain is 0 dB, fa = 1 / (2 Rf C1) Let us assume C1 = 0.1 F; then Rf = _________ Since fb = 20 fa, fb = --------------We know that the gain limiting frequency fb = 1 / (2 R1 C1) Hence R1 = _________ Also since R1C1 = Rf Cf ; Cf = _________ PROCEDURE: 1. Connections are given as per the circuit diagram. 2. + Vcc and - Vcc supply is given to the power supply terminal of the Op-Amp IC. 3. By adjusting the amplitude and frequency knobs of the function generator, appropriate input voltage is applied to the inverting input terminal of the Op-Amp. 4. The output voltage is obtained in the CRO and the input and output voltage waveforms are plotted in a graph sheet.

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CIRCUIT DIAGRAM OF DIFFERENTIATOR:

DIFFERENTIATOR: INPUT SIGNAL:

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Time Period

Amplitude

OUTPUT SIGNAL:

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Amplitude

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Time Period 131

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OBSERVATIONS: Input - Sine wave S.No. Amplitude ( No. of div x Volts per div ) Input Output Input Square wave S.No. Amplitude ( No. of div x Volts per div ) Input Output

Time period ( No. of div x Time per div )

Time period ( No. of div x Time per div )

RESULT:

The design of the Differentiator circuit was done and the input and output waveforms were obtained.

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14(b) INTEGRATOR AIM: To design an Integrator circuit for the given specifications using Op-Amp IC 741. APPARATUS REQUIRED: S.No Name of the Apparatus 1. Function Generator 2. CRO 3. Dual RPS 4. Op-Amp 5. Bread Board 6. Resistors 7. Capacitors 8. Connecting wires and probes

Range 3 MHz 30 MHz 0 30 V IC 741

Vo = - (1/Rf C1) Vi dt Here the negative sign indicates that the output voltage is 180 0 out of phase with the input signal. Normally between fa and fb the circuit acts as an integrator. Generally, the value of fa < fb . The input signal will be integrated properly if the Time period T of the signal is larger than or equal to Rf Cf. That is, T R f Cf The integrator is most commonly used in analog computers and ADC and signal-wave shaping circuits.

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PIN DIAGRAM:

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THEORY: A circuit in which the output voltage waveform is the integral of the input voltage waveform is the integrator. Such a circuit is obtained by using a basic inverting amplifier configuration if the feedback resistor Rf is replaced by a capacitor Cf . The expression for the output voltage is given as,

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As required

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Quantity 1 1 1 1 1

CIRCUIT DIAGRAM OF INTEGRATOR:

DESIGN:

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PROCEDURE:

1. Connections are given as per the circuit diagram. 2. + Vcc and - Vcc supply is given to the power supply terminal of the Op-Amp IC. 3. By adjusting the amplitude and frequency knobs of the function generator, appropriate input voltage is applied to the inverting input terminal of the Op-Amp.

We know the frequency at which the gain is 0 dB, fb = 1 / (2 R1 Cf) Therefore fb = _____ Since fb = 10 fa, and also the gain limiting frequency fa = 1 / (2 Rf Cf) We get, Rf = _______ and hence R1 = __________

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4. The output voltage is obtained in the CRO and the input and output voltage waveforms are plotted in a graph sheet.

OBSERVATIONS: S.No. Input Output MODEL GRAPH: INTEGRATOR: INPUT SIGNAL: Amplitude ( No. of div x Volts per div ) Time period ( No. of div x Time per div )

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Amplitude

OUTPUT SIGNAL:

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RESULT: The design of the Integrator circuit was done and the input and output waveforms were obtained.

Amplitude

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Time Period 135

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EX.NO. 15 AIM:

15(a) TIMER IC APPLICATIONS - I (ASTABLE MULTIVIBRATOR)

To design an astable multivibrator circuit for the given specifications using 555 Timer IC. APPARATUS REQUIRED: S. No 1. 2. 3. 4. 5. 6. 7. 8. Name of the Apparatus Function Generator CRO Dual RPS Timer IC Bread Board Resistors Capacitors Connecting wires and probes Range 3 MHz 30 MHz 0 30 V IC 555

As required

THEORY: An astable multivibrator, often called a free-running multivibrator, is a rectangularwave-generating circuit. This circuit do not require an external trigger to change the state of the output. The time during which the output is either high or low is determined by two resistors and a capacitor, which are connected externally to the 555 timer. The time during which the capacitor charges from 1/3 Vcc to 2/3 Vcc is equal to the time the output is high and is given by, tc = 0.69 (R1 + R2) C

Similarly the time during which the capacitor discharges from 2/3 Vcc to 1/3 Vcc is equal to the time the output is low and is given by,

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Thus the total time period of the output waveform is, T = tc + td = 0.69 (R1 + 2 R2) C

The term duty cycle is often used in conjunction with the astable multivibrator. The duty cycle is the ratio of the time tc during which the output is high to the total time period T. It is generally expressed in percentage. In equation form, % duty cycle = [(R1 + R2) / (R1 + 2 R2)] x 100

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td = 0.69 (R2) C

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Quantity 1 1 1 1 1

PIN DIAGRAM:

CIRCUIT DIAGRAM OF ASTABLE MULTIVIBRATOR:

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DESIGN:

Given f= 4 KHz, Therefore, Total time period, T = 1/f = ____________ We know, duty cycle = tc / T Therefore, tc = -----------------------and td = ____________ We also know for an astable multivibrator td = 0.69 (R2) C Therefore, R2 = _____________ tc = 0.69 (R1 + R2) C Therefore, R1 = _____________

PROCEDURE:

1. Connections are given as per the circuit diagram. 2. + 5V supply is given to the + Vcc terminal of the timer IC. 3. At pin 3 the output waveform is observed with the help of a CRO 4. At pin 6 the capacitor voltage is obtained in the CRO and the V 0 and Vc voltage waveforms are plotted in a graph sheet.

OBSERVATIONS:

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Waveforms Amplitude ( No. of div x Volts per div )

S.No

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Time period ( No. of div x Time per div ) tc td 138

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1.

Output Voltage , Vo

2.

Capacitor voltage , Vc

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MODEL GRAPH:

O/p voltage

Vcc

Capacitor voltage

1/3 Vcc TON

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RESULT:

The design of the Astable multivibrator circuit was done and the output voltage and capacitor voltage waveforms were obtained.

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TOFF

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2/3 Vcc

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T (ms)

15(b) TIMER IC APPLICATIONS II (MONOSTABLE MULTIVIBRATOR) AIM: To design a monostable multivibrator for the given specifications using 555 Timer IC. APPARATUS REQUIRED: S.No 1. 2. 3. 4. 5. 6. 7. 8. Name of the Apparatus Function Generator CRO Dual RPS Timer IC Bread Board Resistors Capacitors Connecting wires and probes

THEORY: A monostable multivibrator often called a one-shot multivibrator is a pulse generating circuit in which the duration of the pulse is determined by the RC network connected externally to the 555 timer. In a stable or stand-by state the output of the circuit is approximately zero or at logic low level. When an external trigger pulse is applied, the output is forced to go high (approx. Vcc). The time during which the output remains high is given by, tp = 1.1 R1 C At the end of the timing interval, the output automatically reverts back to its logic low state. The output stays low until a trigger pulse is applied again. Then the cycle repeats. Thus the monostable state has only one stable state hence the name monostable. PIN DIAGRAM:

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As required

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Range 3 MHz, Analog 30 MHz 0 30 V IC 555

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Quantity 1 1 1 1 1 140

CIRCUIT DIAGRAM OF MONOSTABLE MULTIVIBRATOR:

DESIGN: Given tp = 0.616 ms = 1.1 R1 C Therefore, R1 = _____________

PROCEDURE: 1. 2. 3. 4. 5.

Connections are given as per the circuit diagram. + 5V supply is given to the + Vcc terminal of the timer IC. A negative trigger pulse of 5V, 2 KHz is applied to pin 2 of the 555 IC At pin 3 the output waveform is observed with the help of a CRO At pin 6 the capacitor voltage is obtained in the CRO and the V 0 and Vc voltage waveforms are plotted in a graph sheet.

OBSERVATIONS:

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Amplitude ( No. of div x Volts per div )

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S.No

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Time period ( No. of div x Time per div ) ton toff 141

1.

Trigger input

2. 3.

Output Voltage , Vo

Capacitor voltage , Vc

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MODEL GRAPH:

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RESULT: The design of the Monostable multivibrator circuit was done and the input and output waveforms were obtained.

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