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Introduction to CMOS VLSI Design

Lecture 4: CMOS Inverter


Dr.Theerayod Wiagntong
Electronic Department, MUT

Outline
CMOS Inverter DC Response Logic Levels and Noise Margins Transient Response Delay Estimation

4: DC and Transient Response

CMOS VLSI Design

Slide 2

Activity
1) If the width of a transistor increases, the current will increase decrease not change 2) If the length of a transistor increases, the current will increase decrease not change 3) If the supply voltage of a chip increases, the maximum transistor current will increase decrease not change 4) If the width of a transistor increases, its gate capacitance will increase decrease not change 5) If the length of a transistor increases, its gate capacitance will increase decrease not change 6) If the supply voltage of a chip increases, the gate capacitance of each transistor will increase decrease not change
4: DC and Transient Response CMOS VLSI Design Slide 3

Activity
1) If the width of a transistor increases, the current will increase decrease not change 2) If the length of a transistor increases, the current will increase decrease not change 3) If the supply voltage of a chip increases, the maximum transistor current will increase decrease not change 4) If the width of a transistor increases, its gate capacitance will increase decrease not change 5) If the length of a transistor increases, its gate capacitance will increase decrease not change 6) If the supply voltage of a chip increases, the gate capacitance of each transistor will increase decrease not change
4: DC and Transient Response CMOS VLSI Design Slide 4

Static Load MOS Inverter

4: DC and Transient Response

CMOS VLSI Design

Slide 5

CMOS Inverter
VDD

N Well

VDD 2

PMOS

PMOS In Out
In Polysilicon

Contacts

Out Metal 1

NMOS
NMOS GND

4: DC and Transient Response

CMOS VLSI Design

Slide 6

Two Inverters
Share power and ground Abut cells

VDD
Connect in Metal

4: DC and Transient Response

CMOS VLSI Design

Slide 7

CMOS Inverter as Switch


V DD Rp V DD

tpHL = f(Ron.CL) = 0.69 RonCL


V out CL Rn V out CL

V in 5 0 (a) Low-to-high
4: DC and Transient Response

V in 5 V DD (b) High-to-low
CMOS VLSI Design Slide 8

DC Response
DC Response: Vout vs. Vin for a gate Ex: Inverter When Vin = 0 -> Vout = VDD When Vin = VDD -> Vout = 0 VDD In between, Vout depends on Idsp transistor size and current Vin Vout By KCL, must settle such that Idsn Idsn = |Idsp| We could solve equations But graphical solution gives more insight
4: DC and Transient Response CMOS VLSI Design Slide 9

Transistor Operation
Current depends on region of transistor behavior For what Vin and Vout are nMOS and pMOS in Cutoff? Linear? Saturation?

4: DC and Transient Response

CMOS VLSI Design

Slide 10

nMOS Operation
Cutoff Vgsn < Linear Vgsn > Vdsn < Saturated Vgsn > Vdsn >

VDD Vin Idsp Idsn


4: DC and Transient Response CMOS VLSI Design Slide 11

Vout

nMOS Operation
Cutoff Vgsn < Vtn Linear Vgsn > Vtn Vdsn < Vgsn Vtn Saturated Vgsn > Vtn Vdsn > Vgsn Vtn

VDD Vin Idsp Idsn


4: DC and Transient Response CMOS VLSI Design Slide 12

Vout

nMOS Operation
Cutoff Vgsn < Vtn Linear Vgsn > Vtn Vdsn < Vgsn Vtn Saturated Vgsn > Vtn Vdsn > Vgsn Vtn

VDD

Vgsn = Vin Vdsn = Vout


4: DC and Transient Response CMOS VLSI Design

Vin

Idsp Idsn

Vout

Slide 13

nMOS Operation
Cutoff Vgsn < Vtn Vin < Vtn Linear Vgsn > Vtn Vin > Vtn Vdsn < Vgsn Vtn Vout < Vin - Vtn Saturated Vgsn > Vtn Vin > Vtn Vdsn > Vgsn Vtn Vout > Vin - Vtn
VDD

Vgsn = Vin Vdsn = Vout


4: DC and Transient Response CMOS VLSI Design

Vin

Idsp Idsn

Vout

Slide 14

pMOS Operation
Cutoff Vgsp > Linear Vgsp < Vdsp > Saturated Vgsp < Vdsp <

VDD Vin Idsp Idsn


4: DC and Transient Response CMOS VLSI Design Slide 15

Vout

pMOS Operation
Cutoff Vgsp > Vtp Linear Vgsp < Vtp Vdsp > Vgsp Vtp Saturated Vgsp < Vtp Vdsp < Vgsp Vtp

VDD Vin Idsp Idsn


4: DC and Transient Response CMOS VLSI Design Slide 16

Vout

pMOS Operation
Cutoff Vgsp > Vtp Linear Vgsp < Vtp Vdsp > Vgsp Vtp Saturated Vgsp < Vtp Vdsp < Vgsp Vtp

VDD

Vgsp = Vin - VDD Vdsp = Vout - VDD


4: DC and Transient Response

Vtp < 0
Vin

Idsp Idsn

Vout

CMOS VLSI Design

Slide 17

pMOS Operation
Cutoff Vgsp > Vtp Vin > VDD + Vtp Linear Vgsp < Vtp Vin < VDD + Vtp Vdsp > Vgsp Vtp Vout > Vin - Vtp Saturated Vgsp < Vtp Vin < VDD + Vtp Vdsp < Vgsp Vtp Vout < Vin - Vtp
VDD

Vgsp = Vin - VDD Vdsp = Vout - VDD


4: DC and Transient Response

Vtp < 0
Vin

Idsp Idsn

Vout

CMOS VLSI Design

Slide 18

I-V Characteristics
Make pMOS is wider than nMOS such that n = p
Vgsn5

Idsn -Vdsp Vgsp1 Vgsp2 Vgsp3 Vgsp4 -Idsp -VDD 0 Vdsn VDD

Vgsn4 Vgsn3 Vgsn2 Vgsn1

Vgsp5
4: DC and Transient Response CMOS VLSI Design Slide 19

Current vs. Vout, Vin


Vin0 Vin5

Idsn, |Idsp|

Vin1 Vin2 Vin3 Vin4 Vout VDD

Vin4 Vin3 Vin2 Vin1

4: DC and Transient Response

CMOS VLSI Design

Slide 20

Load Line Analysis


For a given Vin: Plot Idsn, Idsp vs. Vout Vout must be where |currents| are equal in
Vin0 Vin5

Idsn, |Idsp|

Vin1 Vin2 Vin3 Vin4 Vout VDD

Vin4 Vin3 Vin2 Vin1


Vin VDD Idsp Idsn Vout

4: DC and Transient Response

CMOS VLSI Design

Slide 21

Load Line Analysis


Vin = 0
Vin0

Idsn, |Idsp|

Vin0 Vout
4: DC and Transient Response CMOS VLSI Design

VDD

Slide 22

Load Line Analysis


Vin = 0.2VDD

Idsn, |Idsp|

Vin1

Vin1 Vout
4: DC and Transient Response CMOS VLSI Design

VDD

Slide 23

Load Line Analysis


Vin = 0.4VDD

Idsn, |Idsp| Vin2 Vin2 Vout


4: DC and Transient Response CMOS VLSI Design

VDD

Slide 24

Load Line Analysis


Vin = 0.6VDD

Idsn, |Idsp| Vin3 Vin3 Vout


4: DC and Transient Response CMOS VLSI Design

VDD

Slide 25

Load Line Analysis


Vin = 0.8VDD

Idsn, |Idsp|

Vin4

Vin4 Vout
4: DC and Transient Response CMOS VLSI Design

VDD

Slide 26

Load Line Analysis


Vin = VDD
Vin0 Vin5

Idsn, |Idsp|

Vin1 Vin2 Vin3 Vin4 Vout VDD

4: DC and Transient Response

CMOS VLSI Design

Slide 27

Load Line Summary


Vin0 Vin5

Idsn, |Idsp|

Vin1 Vin2 Vin3 Vin4 Vout VDD

Vin4 Vin3 Vin2 Vin1

4: DC and Transient Response

CMOS VLSI Design

Slide 28

DC Transfer Curve
Transcribe points onto Vin vs. Vout plot

Vin0

Vin5

VDD A Vout B

Vin1 Vin2 Vin3 Vin4 Vout VDD

Vin4 Vin3 Vin2 Vin1

D 0
Vtn VDD/2

E
VDD+Vtp

VDD

Vin

4: DC and Transient Response

CMOS VLSI Design

Slide 29

Operating Regions
Revisit transistor operating regions

Region A B C D E

nMOS

pMOS

VDD A Vout B

D 0
Vtn VDD/2

E
VDD+Vtp

VDD

Vin

4: DC and Transient Response

CMOS VLSI Design

Slide 30

Operating Regions
Revisit transistor operating regions

Region A B C D E

nMOS Cutoff Saturation Saturation Linear Linear

pMOS Linear Linear Saturation Saturation Cutoff

VDD A Vout B

D 0
Vtn VDD/2

E
VDD+Vtp

VDD

Vin

4: DC and Transient Response

CMOS VLSI Design

Slide 31

Region Operation

4: DC and Transient Response

CMOS VLSI Design

Slide 32

Region A
0 Vin VTn n-device Cut-off p-device Linear Idsn = -Idsp = 0 Vdsp = Vout VDD, but Vdsp = 0 Vout = VDD

4: DC and Transient Response

CMOS VLSI Design

Slide 33

Region B
VTn Vin VDD/2 n-device Saturation p-device Linear p-device n-device

4: DC and Transient Response

CMOS VLSI Design

Slide 34

Region C
n p-device Saturation

n = p VTn = VTp

4: DC and Transient Response

CMOS VLSI Design

Slide 35

Region D
VDD/2 < Vin VDD- VTp p-device Saturation n-device Linear

4: DC and Transient Response

CMOS VLSI Design

Slide 36

Region E
Vin VDD- VTp p-device Cut-off n-device Linear Vgsp = Vin- VDD Threshold p-device (VTp) Vout = 0

4: DC and Transient Response

CMOS VLSI Design

Slide 37

Beta Ratio
If p / n 1, switching point will move from VDD/2 Called skewed gate Other gates: collapse into equivalent inverter
VDD
p = 10 n

Vout
p = 0.1 n

2 1 0.5

0 Vin
4: DC and Transient Response CMOS VLSI Design

VDD

Slide 38

Transition (undefined) Region


Vm = Switching Threshold Voltage
VOH Vy = Vx Vy

Undefined (Indeterminate) region


VOL VIL

VM

VIH

Vx

4: DC and Transient Response

CMOS VLSI Design

Slide 39

Noise Margins
How much noise can a gate input see before it does not recognize the input?

Output Characteristics Logical High Output Range

VDD

Input Characteristics Logical High Input Range Indeterminate Region Logical Low Input Range

VOH NMH VIH VIL NML

Logical Low Output Range

VOL GND

4: DC and Transient Response

CMOS VLSI Design

Slide 40

Logic Levels
To maximize noise margins, select logic levels at
Vout VDD

p / n > 1 Vin Vout

0 VDD

Vin

4: DC and Transient Response

CMOS VLSI Design

Slide 41

Logic Levels
To maximize noise margins, select logic levels at unity gain point of DC transfer characteristic
Vout VDD VOH p / n > 1 Vin Vout Unity Gain Points Slope = -1

VOL 0 Vtn VIL VIH VDD- VDD |Vtp|

Vin

4: DC and Transient Response

CMOS VLSI Design

Slide 42

Delay Definitions
tpdr : rising propagation delay From input to rising output crossing VDD/2 tpdf: falling propagation delay From input to falling output crossing VDD/2 tpd: average propagation delay tpd = (tpdr + tpdf)/2
2.0 1.5

1.0 (V)

Vin
0.5

tpdf = 66ps

tpdr = 83ps

Vout

0.0

0.0

200p

400p t(s)

600p

800p

1n

4: DC and Transient Response

CMOS VLSI Design

Slide 43

Delay Definitions
tr: rise time From output crossing 0.1 VDD to 0.9 VDD tf: fall time From output crossing 0.9 VDD to 0.1 VDD

4: DC and Transient Response

CMOS VLSI Design

Slide 44

Delay Estimation
We would like to be able to easily estimate delay Not as accurate as simulation But easier to ask What if? The step response usually looks like a 1st order RC response with a decaying exponential. Use RC delay models to estimate delay C = total capacitance on output node Use effective resistance R So that tpd = RC Characterize transistors by finding their effective R Depends on average current as gate switches
4: DC and Transient Response CMOS VLSI Design Slide 45

RC Delay Models
Use equivalent circuits for MOS transistors Ideal switch + capacitance and ON resistance Unit nMOS has resistance R, capacitance C Unit pMOS has resistance 2R, capacitance C Capacitance proportional to width Resistance inversely proportional to width
d R/k g kC s
4: DC and Transient Response CMOS VLSI Design

s kC d k s kC g

kC 2R/k

d k s

g kC

kC d
Slide 46

Switching Characteristic

4: DC and Transient Response

CMOS VLSI Design

Slide 47

Fall Time

4: DC and Transient Response

CMOS VLSI Design

Slide 48

Rise Time

How to make rise time = fall time?

4: DC and Transient Response

CMOS VLSI Design

Slide 49

Effective

How to make rise time = fall time?


4: DC and Transient Response CMOS VLSI Design Slide 50

Switch Level RC Models


Simple RC Model

4: DC and Transient Response

CMOS VLSI Design

Slide 51

Switch Level RC Models


Penfield-Rubenstein Model (Distributed RC)

4: DC and Transient Response

CMOS VLSI Design

Slide 52

CMOS Gate Transistor Sizing

4: DC and Transient Response

CMOS VLSI Design

Slide 53

Fan-in/Fan-out

4: DC and Transient Response

CMOS VLSI Design

Slide 54

Inverter Chain
In Out CL

If CL is given: - How many stages are needed to minimize the delay? - How to size the inverters? May need some additional constraints.
4: DC and Transient Response CMOS VLSI Design Slide 55

Inverter Delay
Minimum length devices, L=0.25m Assume that for WP = 2WN =2W same pull-up and pull-down currents approx. equal resistances RN = RP approx. equal rise tpLH and fall tpHL delays Analyze as an RC network
WP RP = Runit W unit
Delay (D):
1

2W

WN Runit W unit

= RN = RW
tpLH = (ln 2) RPCL

tpHL = (ln 2) RNCL


C gin = 3 W Cunit Wunit

Load for the next stage:


4: DC and Transient Response

CMOS VLSI Design

Slide 56

Inverter with Load


Delay

RW

CL RW tp = k RWCL k is a constant, equal to 0.69 Assumptions: no load -> zero delay


4: DC and Transient Response CMOS VLSI Design

Load (CL)

Wunit = 1
Slide 57

Inverter with Load


CP = 2Cunit 2W
Delay

Cint

CL
Load

CN = Cunit
Delay = kRW(Cint + CL) = kRWCint + kRWCL = kRW Cint(1+ CL /Cint) = Delay (Internal) + Delay (Load)
4: DC and Transient Response CMOS VLSI Design

Slide 58

Delay Formula
Delay ~ RW (C int + C L ) t p = kR W C int (1 + C L / C int ) = t p 0 (1 + f /
Cint = Cgin with 1 f = CL/Cgin - effective fanout R = Runit/W ; Cint =WCunit tp0 = 0.69RunitCunit
4: DC and Transient Response CMOS VLSI Design Slide 59

Apply to Inverter Chain


In 1 2 N Out CL

tp = tp1 + tp2 + + tpN

C gin , j +1 t pj ~ Runit Cunit 1 + C , gin j N N C gin , j +1 , C gin , N +1 = C L t p = t p , j = t p 0 1 + C j =1 i =1 gin , j


4: DC and Transient Response CMOS VLSI Design Slide 60

Optimal Tapering for Given N


Delay equation has N - 1 unknowns, Cgin,2 Cgin,N Minimize the delay, find N - 1 partial derivatives Result: Cgin,j+1/Cgin,j = Cgin,j/Cgin,j-1 Size of each stage is the geometric mean of two neighbors
C gin , j = C gin , j 1C gin , j +1

- each stage has the same effective fanout (Cout/Cin) - each stage has the same delay
4: DC and Transient Response CMOS VLSI Design Slide 61

Optimum Delay and Number of Stages


When each stage is sized by f and has same eff. fanout f:

= F = C L / C gin ,1

Effective fanout of each stage:

f =NF
Minimum path delay

t p = Nt p 0 1 + N F /
4: DC and Transient Response CMOS VLSI Design

)
Slide 62

Example
In C1 1 f f2 Out CL= 8 C1

CL/C1 has to be evenly distributed across N = 3 stages:

f =38 =2

4: DC and Transient Response

CMOS VLSI Design

Slide 63

Optimum Number of Stages


For a given load, CL and given input capacitance Cin Find optimal sizing f
C L = F Cin = f Cin
N

ln F with N = ln f

t p 0 ln F f t p = Nt p 0 F / + 1 = + ln f ln f t p t p 0 ln F ln f 1 f = =0 2 f ln f

1/ N

For = 0, f = e, N = lnF
4: DC and Transient Response CMOS VLSI Design

f = exp(1 + f )
Slide 64

Optimum Effective Fanout f


Optimum f for given process defined by

f = exp(1 + f )

fopt = 3.6 for =1

4: DC and Transient Response

CMOS VLSI Design

Slide 65

Buffer Design
N
1 64

f 64

tp 65

64

18

16

64

15

2.8

22.6

64

2.8

15.3
Slide 66

4: DC and Transient Response

CMOS VLSI Design

Power Dissipation
Static reverse bias Diffusion Substrate

4: DC and Transient Response

CMOS VLSI Design

Slide 67

Power Dissipation
Dynamic Switching transient current (short-circuit current) Charging and discharging of load capacitances (major)

4: DC and Transient Response

CMOS VLSI Design

Slide 68

Short Circuit Current

4: DC and Transient Response

CMOS VLSI Design

Slide 69

Charge-Discharge Current

* step input in(t) = C (dVout/dt)


L

(E) E(switching) Pd = CLVDD2fpE(switching)


4: DC and Transient Response CMOS VLSI Design Slide 70

CMOS Latch-up Problem

4: DC and Transient Response

CMOS VLSI Design

Slide 71