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EL 511 VLSI Design

Instructor: Mazad S. Zaveri Faculty Block 4, Room 4206 Email:

EL 511 VLSI Design

weste and harris topic 2.5.3

Definition of variables for Noise Margin

Some books may assume VOH to be the settled value

For our course, we will assume VOH and VOL to be the settled values

Some books may assume VOL to be the settled value

EL 511 VLSI Design

Pass transistor and Transmission Gate

Assumption: Output closely follows input

This is the approx. resistance of the transmission gate and is relatively constant.

EL 511 VLSI Design



For Resistive load NMOS Inverter

VOH = VDD 1 1 2VDD VDD VT 0 + VOL = VDD VT 0 + n RL n RL n RL 1 VIL = VT 0 + Assumption while calculating this value: n RL Vout (when Vin = VIL ) = VDD 1 2 n RL
Vin is some value < VT0 Assumption while calculating this: Vin is VDD (if this inverter was driven by similar previous stage inverter then we assume that previous inverters input was < VT0, due to which, the previous inverters output was VDD Indirectly, we can also say that VOL is assumed to be < VT0, considering that this inverter will feed similar next stage inverter 4
EL 511 VLSI Design

IR =

VDD Vout R

2 VDD Vout (when Vin = VIH ) = 3 n RL VIH = VT 0 + 8 VDD 3 n RL 1 n RL

Topics covered
From the DJVU file on \\daiictpdc
2.5.2 2.5.3 2.5.4

In Kang and Leblebici

Pg. 177-186

EL 511 VLSI Design

MOSFET Capacitance
Gate capacitance Cg Diffusion capacitance Cdb and Csb For a rough analysis
Cg = Cdb = Csb = ~2fF/micro-m of gate-width (W)

Area and perimeter of Source/Drain

Minimum width (W) of a drain/source region or (also the W of transistor) with a contact present is W = 4 Area of drain or source = 4 x 5 = W x 5 Perimeter of drain or source = 2(4 + 5) = 2(W + 5)

2 4 2 2

1 1 1

Switch-level RC models
Resistance at some operating point is defined as

In linear region, assuming Vds is small

RC Equivalent of NMOS and PMOS transistor

Not explicitly drawing the switch

EL 511 VLSI Design

Inverter RC equivalent circuit

To study the approximate propagation/delay times
Concept of pull-up and pull-down
Gate Cap of 2nd inverter acting as load

Neglecting the parasitic/diffusion capacitances, a unit-size inverter loaded with another unit-size inverter will lead to a time-constant (3RC) This is a figure of merit for manufacturing and design processes

Load = ONLY capacitive C defined in terms of smallest NMOS transistor R defined in terms of smallest NMOS transistor