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ILI9320

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 16.7M color Datasheet Preliminary

Version: V0.41 Document No.: ILI9320DS_V0.41.pdf

ILI TECHNOLOGY CORP.

4F, No. 2, Tech. 5th Rd., Hsinchu Science Park, Taiwan 300, R.O.C. Tel.886-3-5670095; Fax.886-3-5670096 http://www.ilitek.com

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color Table of Contents Section

ILI9320
Page

1. Introduction.................................................................................................................................................... 7 2. Features ........................................................................................................................................................ 7 3. Block Diagram ............................................................................................................................................... 9 4. Pin Descriptions .......................................................................................................................................... 10 5. Pad Arrangement and Coordination............................................................................................................ 15 6. Block Description ........................................................................................................................................ 22 7. System Interface ......................................................................................................................................... 25 7.1. 7.2. Interface Specifications .................................................................................................................. 25 Input Interfaces .............................................................................................................................. 26 7.2.1. 7.2.2. 7.2.3. 7.2.4. 7.3. 7.4. 7.5. i80/18-bit System Interface.................................................................................................. 27 i80/16-bit System Interface.................................................................................................. 28 i80/9-bit System Interface.................................................................................................... 29 i80/8-bit System Interface.................................................................................................... 29

Serial Peripheral Interface (SPI) .................................................................................................... 30 VSYNC Interface............................................................................................................................ 35 RGB Input Interface ....................................................................................................................... 39 7.5.1. 7.5.2. 7.5.3. 7.5.4. 7.5.5. 7.5.6. RGB Interface...................................................................................................................... 40 RGB Interface Timing .......................................................................................................... 41 Moving Picture Mode........................................................................................................... 43 6-bit RGB Interface.............................................................................................................. 44 16-bit RGB Interface............................................................................................................ 45 18-bit RGB Interface............................................................................................................ 45

7.6. 8.1. 8.2.

Interface Timing.............................................................................................................................. 48 Registers Access............................................................................................................................ 49 Instruction Descriptions.................................................................................................................. 52 8.2.1. 8.2.2. 8.2.3. 8.2.4. 8.2.5. 8.2.6. 8.2.7. 8.2.8. 8.2.9. Index (IR)............................................................................................................................. 54 Status Read (RS)................................................................................................................. 54 Start Oscillation (R00h)........................................................................................................ 54 Driver Output Control (R01h) .............................................................................................. 54 LCD Driving Wave Control (R02h) ...................................................................................... 56 Entry Mode (R03h) .............................................................................................................. 56 Resizing Control Register (R04h)........................................................................................ 58 Display Control 1 (R07h) ..................................................................................................... 59 Display Control 2 (R08h) ..................................................................................................... 60

8. Register Descriptions .................................................................................................................................. 49

8.2.10. Display Control 3 (R09h) ..................................................................................................... 61 8.2.11. Display Control 4 (R0Ah)..................................................................................................... 62 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
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a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color

ILI9320

8.2.12. RGB Display Interface Control 1 (R0Ch)............................................................................. 62 8.2.13. Frame Marker Position (R0Dh) ........................................................................................... 63 8.2.14. RGB Display Interface Control 2 (R0Fh) ............................................................................. 64 8.2.15. Power Control 1 (R10h)....................................................................................................... 64 8.2.16. Power Control 2 (R11h) ....................................................................................................... 66 8.2.17. Power Control 3 (R12h)....................................................................................................... 66 8.2.18. Power Control 4 (R13h)....................................................................................................... 67 8.2.19. GRAM Horizontal/Vertical Address Set (R20h, R21h) ........................................................ 67 8.2.20. Write Data to GRAM (R22h)................................................................................................ 68 8.2.21. Read Data from GRAM (R22h) ........................................................................................... 68 8.2.22. Power Control 7 (R29h)....................................................................................................... 70 8.2.23. Frame Rate and Color Control (R2Bh)................................................................................ 71 8.2.24. Gamma Control (R30h ~ R3Dh).......................................................................................... 72 8.2.25. Horizontal and Vertical RAM Address Position (R50h, R51h, R52h, R53h) ....................... 72 8.2.26. Gate Scan Control (R60h, R61h, R6Ah) ............................................................................. 73 8.2.27. Partial Image 1 Display Position (R80h).............................................................................. 76 8.2.28. Partial Image 1 RAM Start/End Address (R81h, R82h)....................................................... 76 8.2.29. Partial Image 2 Display Position (R83h).............................................................................. 76 8.2.30. Partial Image 2 RAM Start/End Address (R84h, R85h)....................................................... 76 8.2.31. Panel Interface Control 1 (R90h)......................................................................................... 76 8.2.32. Panel Interface Control 2 (R92h)......................................................................................... 77 8.2.33. Panel Interface Control 3 (R93h)......................................................................................... 78 8.2.34. Panel Interface Control 4 (R95h)......................................................................................... 78 8.2.35. Panel Interface Control 5 (R97h)......................................................................................... 79 8.2.36. Panel Interface Control 6 (R98h)......................................................................................... 79 9. GRAM Address Map & Read/Write ............................................................................................................. 80 10. Window Address Function........................................................................................................................... 86 11. Gamma Correction...................................................................................................................................... 88 12. Application................................................................................................................................................... 97 12.1. Configuration of Power Supply Circuit ........................................................................................... 97 12.2. Display ON/OFF Sequence ......................................................................................................... 100 12.3. Standby and Sleep Mode ............................................................................................................. 101 12.4. Power Supply Configuration ........................................................................................................ 102 12.5. Voltage Generation ...................................................................................................................... 103 12.6. Applied Voltage to the TFT panel................................................................................................. 104 12.7. Oscillator ...................................................................................................................................... 104 12.8. Frame Rate Adjustment ............................................................................................................... 105 12.9. Partial Display Function ............................................................................................................... 105 12.10. Resizing Function......................................................................................................................... 106 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
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........ Reset Timing Characteristics ........ or disclosed in whole or in part without prior written permission of ILI Technology Corp................6..6.........a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 13..................................................................................... and shall not be distributed......... 113 14........................ Electrical Characteristics........................6......... 110 13........ reproduced...............................4..41 ....... 109 13.............. 110 13. Clock Characteristics .................5................. AC Characteristics .......1.............................................................................................................................. 110 13................................2........................ 115 The information contained herein is the exclusive property of ILI Technology Corp............................................................. 112 13...................................2...............111 13.................................................................................... LCD Driver Output Characteristics....................................................3........ Absolute Maximum Ratings ........ Page 4 of 115 Version: 0............................................ 109 13................................. Revision History .........................111 13...... 110 13............................................ DC Characteristics .............................6.......................................... RGB Interface Timing Characteristics .............................................................................................................................................3..1...... Serial Data Transfer Interface Timing Characteristics......................... i80-System Interface Timing Characteristics .........

.......................................................................................... 58 FIGURE 28 DATA READ FROM GRAM THROUGH READ DATA REGISTER IN 18-/16-/9-/8-BIT INTERFACE MODE .......................... 90 The information contained herein is the exclusive property of ILI Technology Corp................................................................................... 70 FIGURE 30 GRAM ACCESS RANGE CONFIGURATION .................................. 29 FIGURE5 8-BIT SYSTEM INTERFACE DATA FORMAT ............. 32 FIGURE8 DATA TRANSMISSION THROUGH SERIAL PERIPHERAL INTERFACE (SPI) .......................................................................................... 30 FIGURE6 DATA TRANSFER SYNCHRONIZATION IN 8/9-BIT SYSTEM INTERFACE....................................................... 85 FIGURE 35 GRAM ACCESS WINDOW MAP ......................................................................................................41 .................................................................. 33 FIGURE9 DATA TRANSMISSION THROUGH SERIAL PERIPHERAL INTERFACE (SPI)................................ 27 FIGURE3 16-BIT SYSTEM INTERFACE DATA FORMAT ......................................................................... 80 FIGURE32 I80-SYSTEM INTERFACE WITH 18-/16-/9-BIT DATA BUS (SS=”0”......... reproduced..................................... 40 FIGURE16 TIMING CHART OF SIGNALS IN 18-/16-BIT RGB INTERFACE MODE ...................................................................................................................................................................... 26 FIGURE2 18-BIT SYSTEM INTERFACE DATA FORMAT ............................................... and shall not be distributed............................ TRI=”1” AND DFM=”10”).......................................................................................................... BGR=”0”) .......................................................................... BGR=”1”) .................................... 46 FIGURE20 GRAM ACCESS BETWEEN SYSTEM INTERFACE AND RGB INTERFACE .......... 38 FIGURE14 RGB INTERFACE DATA FORMAT ............... 49 FIGURE23 REGISTER SETTING WITH I80 SYSTEM INTERFACE ............................. 39 FIGURE15 GRAM ACCESS AREA BY RGB INTERFACE ...................................................................................... 50 FIGURE 24 REGISTER READ/WRITE TIMING OF I80 SYSTEM INTERFACE . Page 5 of 115 Version: 0.............. 89 FIGURE 38 GAMMA CURVE ADJUSTMENT .............................................................................................. 88 FIGURE 37 GRAYSCALE VOLTAGE ADJUSTMENT ................ 73 FIGURE31 GRAM READ/WRITE TIMING OF I80-SYSTEM INTERFACE ..................................... 36 FIGURE13 TRANSITION FLOW BETWEEN VSYNC AND INTERNAL CLOCK OPERATION MODES .................................................................................................. or disclosed in whole or in part without prior written permission of ILI Technology Corp.......... 57 FIGURE27 8-BIT MPU SYSTEM INTERFACE DATA FORMAT............................ 48 FIGURE22 REGISTER SETTING WITH SERIAL PERIPHERAL INTERFACE (SPI).................................................................................................................................................................................................................................................................................................................................................................................. 82 FIGURE33 I80-SYSTEM INTERFACE WITH 8-BIT DATA BUS (SS=”0”............. 83 FIGURE 34 I80-SYSTEM INTERFACE WITH 18-/9-BIT DATA BUS (SS=”1”.......................... 30 FIGURE 7 DATA FORMAT OF SPI INTERFACE ......................................................................................................... 41 FIGURE17 TIMING CHART OF SIGNALS IN 6-BIT RGB INTERFACE MODE ... 69 FIGURE 29 GRAM DATA READ BACK FLOW CHART ............................. 86 FIGURE 36 GRAYSCALE VOLTAGE GENERATION ................................................................................................................................................................................ 35 FIGURE12 OPERATION THROUGH VSYNC INTERFACE .. 42 FIGURE18 EXAMPLE OF UPDATE THE STILL AND MOVING PICTURE ....................................................... 56 FIGURE26 16-BIT MPU SYSTEM INTERFACE DATA FORMAT...................................................................................................... 34 FIGURE10 DATA TRANSMISSION THROUGH VSYNC INTERFACE)................................................................................................. BGR=”0”) ............................................................... 47 FIGURE21 RELATIONSHIP BETWEEN RGB I/F SIGNALS AND LCD DRIVING SIGNALS FOR PANEL .................................................................................................................................................. 43 FIGURE19 INTERNAL CLOCK OPERATION/RGB INTERFACE MODE SWITCHING ...............................................................................................................................................................a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color Figures ILI9320 FIGURE1 SYSTEM INTERFACE AND RGB INTERFACE CONNECTION ................................................... 51 FIGURE25 GRAM ACCESS DIRECTION SETTING ............................................................ 28 FIGURE4 9-BIT SYSTEM INTERFACE DATA FORMAT ............................. 35 FIGURE11 MOVING PICTURE DATA TRANSMISSION THROUGH VSYNC INTERFACE .............................................................

........................................................................................................................................................................................................................................................................... 104 FIGURE 48 PARTIAL DISPLAY EXAMPLE ....................................... 101 FIGURE 44 POWER SUPPLY ON/OFF SEQUENCE ................................... 96 FIGURE 41 POWER SUPPLY CIRCUIT BLOCK ..................................................................................................................................................................................................a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 FIGURE 39 RELATIONSHIP BETWEEN SOURCE OUTPUT AND VCOM .................................................... 104 FIGURE 47 OSCILLATION CONNECTION .. 102 FIGURE 45 VOLTAGE CONFIGURATION DIAGRAM ............................................................. 96 FIGURE 40 RELATIONSHIP BETWEEN GRAM DATA AND OUTPUT LEVEL............ 107 FIGURE 51 I80-SYSTEM BUS TIMING .................................................. 114 The information contained herein is the exclusive property of ILI Technology Corp............................................................................................................................ 112 FIGURE 52 SPI SYSTEM BUS TIMING .... 113 FIGURE53 RGB INTERFACE TIMING ........................................................................ 99 FIGURE 42 DISPLAY ON/OFF REGISTER SETTING SEQUENCE ....................................................... 106 FIGURE 49 DATA TRANSFER IN RESIZING ... 107 FIGURE 50 RESIZING EXAMPLE ......... Page 6 of 115 Version: 0.............................................. and shall not be distributed.41 .............................................................................................................. or disclosed in whole or in part without prior written permission of ILI Technology Corp...................................................................... reproduced.......................................................................................................................................................................... 103 FIGURE 46 VOLTAGE OUTPUT TO TFT LCD PANEL .................................................................................................................................................................................................................................................................. 100 FIGURE 43 STANDBY/SLEEP MODE REGISTER SETTING SEQUENCE...................

800 bytes RAM for graphic data of 240RGBx320 dots. PDA and PMP where long battery life is a major concern. The dithering image processing is implemented in ILI9320 to provide the 16 million colors display quality and the Multi-domain Vertical Alignment (MVA) wide view angle display is also supported in the ILI9320. a 320-channel gate driver. ILI9320 has four kinds of system interfaces which are i80-system MPU interface (8-/9-/16-/18-bit bus width). DB[17:0]). and shall not be distributed. ENABLE. comprising a 720-channel source driver. HSYNC. and an incorporated voltage follower circuit to generate voltage levels for driving an LCD. DB[17:0]). DB[17:0]) VSYNC interface (System interface + VSYNC) n-line liquid crystal AC drive: invert polarity at an interval of arbitrarily n lines (n: 1 ~ 64) Internal oscillator and hardware reset Resizing function (×1/2. VSYNC interface (system interface + VSYNC. Features Single chip solution for a liquid crystal QVGA TFT LCD display 240RGBx320-dot resolution capable with real 262. smart phone. The ILI9320 also supports a function to display in 8 colors and a sleep mode.144 display color Dithering image processing implemented to provide 16.800 bytes graphic RAM High-speed RAM burst write function System interfaces i80 system interface with 8-/ 9-/16-/18-bit bus width Serial Peripheral Interface (SPI) RGB interface with 6-/16-/18-bit bus width (VSYNC.41 . internal clock. In RGB interface and VSYNC interface mode. the combined use of high-speed RAM write function and widow address function enables to display a moving picture at a position specified by a user and still pictures in other areas on the screen simultaneously. Introduction ILI9320 is a 262. DOTCLK. and power supply circuit.65V I/O interface voltage. 2. ENABLE. which makes it possible to transfer display the refresh data only to minimize data transfers and power consumption. HSYNC.7-million color display quality Support MVA (Multi-domain Vertical Alignment) wide view display Incorporate 720-channel source driver and 320-channel gate driver Internal 172. serial data transfer interface (SPI) and RGB 6-/16-/18-bit interface (DOTCLK. ILI9320 can operate with 1.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 1. ×1/4) Reversible source/gate driver shift direction The information contained herein is the exclusive property of ILI Technology Corp. Page 7 of 115 Version: 0. reproduced. 172. VSYNC. or disclosed in whole or in part without prior written permission of ILI Technology Corp. allowing for precise power control by software and these features make the ILI9320 an ideal LCD driver for medium or small size portable products such as digital cellular phones.144-color one-chip SoC driver for a-TFT liquid crystal display with resolution of 240RGBx320 dots.

0 VCL – GND = -2.65V ~ 3.GND = 10V ~ 20V VGL – GND = -5V ~ -15V VGH – VGL ≦ 32V VCOM driver output voltage VCOMH = 3.0V Gate driver output voltage VGH .0V ~ (DDVDH-0. enabling partially driving an LCD panel at positions specified by user Incorporate step-up circuits for stepping up a liquid crystal drive voltage level up to 6 times (x6) Power saving functions 8-color mode standby mode sleep mode Low -power consumption architecture Low operating power supplies: IOVcc = 1. and shall not be distributed.5V ~ 6. or disclosed in whole or in part without prior written permission of ILI Technology Corp.144 colors Line-unit vertical scrolling function ILI9320 Partial drive function. reproduced.GND = 4.0V ~ -3.3 V (internal logic) Vci = 2.5V ~ 3.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color Window address function to specify a rectangular area for internal GRAM access Bit operation function for facilitating graphics data processing Bit-unit write data mask function Pixel-unit logical/conditional write function Abundant functions for color display control γ-correction function enabling display in 262.3 V (interface I/O) Vcc = 2.5)V ~ 0V VCOMH-VCOML ≦ 6.4V ~ 3.41 .0V a-TFT LCD storage capacitor: Cst only The information contained herein is the exclusive property of ILI Technology Corp.0V VCI – VCL ≦ 6.5)V VCOML = (VCL+0. Page 8 of 115 Version: 0.3 V (analog) LCD Voltage drive: Source/VCOM power supply voltage DVDH .

reproduced.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 3. Timing Controller LCD Gate Driver G[320:1] VCI VCI1 VCILVL AGND Charge-pump Power Circuit VCOM Generator VCOM C21+ C22+ VCL VLOUT2 VLOUT3 C23+ C21- C22- C23- VCOMR The information contained herein is the exclusive property of ILI Technology Corp. Block Diagram IOVCC IM[3:0] nRESET nCS nWR/SCL nRD RS SDI SDO DB[17:0] HSYNC VSYNC DOTCLK ENABLE TEST1 TEST2 TS[7:0] Index Register (IR) MPU I/F 18-bit 16-bit 9-bit 8-bit SPI I/F RGB I/F 18-bit 16-bit 6-bit VSYNC I/F 18 7 18 Control Register (CR) Address Counter (AC) LCD Source Driver S[720:1] Graphics Operation 18 V63 ~ 0 18 Read Latch 72 Write Latch 72 Grayscale Reference Voltage VREG1OUT VGS VCC VDD GND Regulator Graphics RAM (GRAM) OSC1 OSC2 RC-OSC. Page 9 of 115 Version: 0. and shall not be distributed. or disclosed in whole or in part without prior written permission of ILI Technology Corp.41 VLOUT1 VCOMH VCOML C11+ DDVDH C11- C12- C12+ C13+ C13- VGH VGL .

SPI interface output pin. IM2. Fix to either IOVcc or DGND level when not in use.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 4. Fix to either IOVcc or DGND level when not in use. or disclosed in whole or in part without prior written permission of ILI Technology Corp. A write strobe signal and enables an operation to write data when the signal is low. The data is outputted on the falling edge of the SCL signal. and shall not be distributed. IM0 pin is used for the device code ID setting. nRD I MPU IOVcc MPU IOVcc MPU IOVcc MPU IOVcc nRESET SDI SDO I I O DB[17:0] I/O MPU IOVcc The information contained herein is the exclusive property of ILI Technology Corp. reproduced. DB[8:1] DB[17:10] SDI. A register select signal. A reset pin. A chip select signal. Pin Descriptions Pin Name I/O Type Descriptions Input Interface Select the MPU system interface mode IM3 0 0 0 0 IM2 0 0 0 0 1 1 0 0 0 0 1 IM1 0 0 1 1 0 1 0 0 1 1 * IM0 0 1 0 1 ID * 0 1 0 1 * MPU-Interface Mode Setting invalid Setting invalid i80-system 16-bit interface i80-system 8-bit interface Serial Peripheral Interface (SPI) Setting invalid Setting invalid Setting invalid i80-system 18-bit interface i80-system 9-bit interface Setting invalid DB[17:0] DB[17:9] DB[17:10]. 18-bit I/F: DB[17:0] is used. A read strobe signal and enables an operation to read out data when the signal is low. IM0/ID 0 I IOVcc 0 1 1 1 1 1 nCS I MPU IOVcc RS I MPU IOVcc nWR/SCL I MPU IOVcc When the serial peripheral interface is selected. 9-bit I/F: DB[17:9] is used. SPI Mode: Synchronizing clock signal in SPI mode. IM1. Low: the ILI9320 is selected and accessible High: the ILI9320 is not selected and not accessible Fix to the DGND level when not in use. Page 10 of 115 Version: 0. SPI interface input pin.41 . Let SDO as floating when not used. 16-bit I/F: DB[17:10] and DB[8:1] is used. The data is latched on the rising edge of the SCL signal. Be sure to execute a power-on reset after supplying power. 16-bit RGB I/F: DB[17:13] and DB[11:1] are used. Initializes the ILI9320 with a low input. Low: select an index or status register High: select a control register Fix to either IOVcc or DGND level when not in use. 18-bit parallel bi-directional data bus for RGB interface operation 6-bit RGB I/F: DB[17:12] are used. SDO DB Pin in use IM3. An 18-bit parallel bi-directional data bus for MPU system interface mode 8-bit I/F: DB[17:10] is used.

. The VGS external level can be changed by connecting to an external resistor. A reference level to generate the VCOMH level either with an externally connected variable resistor or by setting the register of the ILI9320. resistor Charge-pump and Regulator Circuit Power A supply voltage to the analog circuit. S1. Page 11 of 115 Version: 0. … display red (R). HSPL = “0”: Active low. LCD Driving signals Source output voltage signals applied to liquid crystal. Connect to a stabilizing capacitor. use the SS bit.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color Pin Name I/O Type Descriptions 18-bit RGB I/F: DB[17:1] are used. Power AGND for the analog side: AGND = 0V. S2. ILI9320 ENABLE I MPU IOVcc Unused pins must be fixed either IOVcc or DGND level. or disclosed in whole or in part without prior written permission of ILI Technology Corp. Connect to a stabilizing capacitor.. display green (G). VGH: the level selecting gate lines VGL: the level not selecting gate lines A supply voltage to the common electrode of TFT panel. reproduced. . connect to The information contained herein is the exclusive property of ILI Technology Corp. SS = “1”. Gate line output signals. The low level of VCOM AC voltage. DOTCLK I MPU IOVcc VSYNC I MPU IOVcc HSYNC I MPU IOVcc MPU IOVcc Oscillation resistor FMARK OSC1 OSC2 O I O S720~S1 O LCD G320~G1 O LCD TFT common electrode Stabilizing capacitor Stabilizing capacitor Variable resistor or open VCOM VCOMH VCOML O O O VCOMR I VGS I Vci AGND I I AGND or Reference level for the grayscale voltage generating circuit. S6. . VSPL = “0”: Active low. To change the shift direction of signal outputs. leave this pin open. In case of COG. VCOM is AC voltage alternating signal between the VCOMH and VCOML levels. Fix to the IOVcc level when not in use. and S3. S9. The FMARK signal is used when writing RAM data in synchronization with frame. Connect to an external power supply supply of 2.. Fix to the IOVcc level when not in use Output a frame head pulse signal. Adjust the VCOML level with the VDV bits. display blue (B) (SS = 0). Fix to either IOVcc or DGND level when not in use. the data in the RAM address “h00000” is output from S720. The high level of VCOM AC voltage. VSPL = “1”: Active high. S5. and shall not be distributed. Low: Select (access enabled) High: Not select (access inhibited) The EPL bit inverts the polarity of the ENABLE signal. S4. Connect an external resistor for generating internal clock by internal R-C oscillation..3V. Data ENEABLE signal for RGB interface operation. HSPL = “1”: Active high.41 . the data in the RAM address “h00000” is output from S1. SS = “0”. Dot clock signal for RGB interface operation. halt the internal VCOMH adjusting circuit by setting the register and place the resister between VREG1OUT and AGND. DPL = “0”: Input data on the rising edge of DOTCLK DPL = “1”: Input data on the falling edge of DOTCLK Fix to the IOVcc level when not in use Frame synchronizing signal for RGB interface operation.5 ~ 3. S8. When using a variable resistor. S7. Line synchronizing signal for RGB interface operation. Leave the pin open when not in use. or an external clock signal is supplied through OSC1. When generating the VCOMH level by setting the register.

An internal reference voltage generated between Vci and AGND. IOVcc = 1. Place a stabilizing capacitor between AGND Capacitor connection pins for the step-up circuit 1. Output voltage from the step-up circuit 1. VGH VLOUT2 Stabilizing capacitor. DDVDH VLOUT1 Stabilizing capacitor. connect the VciLVL with Vci on the FPC to prevent noise. HSYNC. nRESET. In COG case. VREG1OUT I/O Stabilizing capacitor or power supply The voltage level is set with the VRH bits. RS. VLOUT2 and VLOUT3 voltages are set within the respective specification.0V Output voltage from the step-up circuit 2.0 ~ (DDVDH – 0. C21C22+. which is generated from Vci1 and DDVDH. VREG1OUT = 3. VGL VLOUT3 Stabilizing capacitor. VREG1OUT is (1) a source driver grayscale reference voltage. or disclosed in whole or in part without prior written permission of ILI Technology Corp.3V A supply voltage to the interface pins: IM[3:0]. The step-up factor is set by “BT” bits.65 ~ 3.5V ~ 3. VcomL driver power supply.15V Place a stabilizing capacitor between AGND and a shottkey diode between Vci. Output voltage from the step-up circuit 2. which is generated from Vci1 and DDVDH. Output voltage generated from the reference voltage. C13C21+. The amplitude between Vci and DGND is determined by the VC[2:0] bits. VCLC = 0 ~ –3. SDO. (2) VcomH level reference voltage.5V Place a stabilizing capacitor between AGND and a shottkey diode between Vci.5 ~ 6. Connect to a stabilizing capacitor.3V. VLOUT1= 4. Connect to VLOUT1 and DDVDH = 4. VSYNC. Connect to the external power supply. Power supply for the source driver and Vcom drive. The step-up factor is set by “BT” bits. Make sure to set the Vci1 voltage so that the VLOUT1. DOTCLK. VLOUT2= max. C11C12+. In case of COG. C12C13+. Page 12 of 115 Version: 0. SCL. C22C23+. nRD.0V Place a stabilizing capacitor between AGND. An internal reference voltage for the step-up circuit1. VciLVL must be at the same voltage level as Vci. which is generated from Vci1. The step-up factor is set by “BT” bits. The amplitude between Vci and DGND is determined by the VC[2:0] bits. to prevent noise. and shall not be distributed. -12. Vcc I Power supply Power supply Power IOVcc I VDD O The information contained herein is the exclusive property of ILI Technology Corp. reproduced. and (3) Vcom amplitude reference voltage. C23- I O I/O Descriptions GND on the FPC to prevent noise.3V. VciLVL=2. ENABLE. Digital core power pad. SDI.3V and Vcc ≧IOVcc.5)V. nWR. nCS.41 . DB[17:0]. connect to VLOUT2. Power Pads A supply voltage to the internal logic: Vcc = 2. Power supply for the gate driver.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color Pin Name I/O Type supply Power supply Stabilizing capacitor Vci1 Stabilizing capacitor Vci1 Stabilizing capacitor. Power supply for the gate driver.4~3. connect to VLOUT3. I/O Capacitor connection pins for the step-up circuit 2. connect to Vcc on the FPC if IOVcc=Vcc.5 ~ 6. VLOUT3= max. VCL Step-up capacitor Step-up capacitor ILI9320 VciLVL I VciOUT O Vci1 I VLOUT1 O DDVDH O VLOUT2 O VGH I VLOUT3 O VGL VCL C11+.

1 2 3 4 Item TFT Source Driver TFT Gate Driver TFT Display’s Capacitor Structure S1 ~ S720 Liquid Crystal Drive G1 ~ G320 Output VCOM Input Voltage Liquid Crystal Drive IOVcc Vcc Vci DDVDH Description 720 pins (240 x RGB) 320 pins Cst structure only (Common VCOM) V0 ~ V63 grayscales VGH . 5 TEST3 TEST4 TSC TS0~8 VPP1~3 O O O O O I I I I I - IOGND for the interface pins. Dummy pads. Dummy pad. Dummy pad. Connect to IOVcc. Connect to IOVcc. GND or leave this pin as open. GND or leave these pins as open. 2.41 .a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color Pin Name GND IOGND I/O I I Type Power supply Power supply Power Power Power Open Open IOGND IOVcc IOVcc AGND OPEN Power Supply Descriptions Connect them with the 1uF capacitor. Connect to IOVcc. GND or leave these pins as open. Dummy pad. Dummy pin. Test pins (internal pull low). GND or leave this pin as open. and shall not be distributed.30V 2. GND or leave this pin as open. Test pins. Dummy pin. Output the GND voltage level. These pins are internally shorted to IOVCC Dummy pin. Dummy pads. GND or leave these pins as open. Connect to GND or leave these pins as open. IOGND = 0V. When adjacent pins are needed to pull low. Dummy pad. Test pins. Connect to IOVcc.5V ~ 6.30V 4. Test pins (internal pull low). Dummy pad. Connect to IOVcc.65 ~ 3. Connect to IOVcc. GND or leave this pin as open. Connect to IOVcc. GND or leave this pin as open. Dummy pads. GND or leave this pin as open. Page 13 of 115 Version: 0. Must let these pads as open. Connect to IOVcc. GND or leave this pin as open. Dummy pad.50 ~ 3. Connect to IOVcc. Connect to IOVcc. Dummy pin. Liquid crystal power supply specifications Table 1 No. connect to GND on the FPC to prevent noise. Connect to IOVcc. V31T VTEST VREFC VREF VDDTEST VREFD VMON TESTA5 IOVCCDUM1~2 VCCDUM1 IOGNDDUM1~3 OSC1DUM1~4 OSC2DUM1~2 AGNDDUM1 AGNDDUM2~4 DUMMYR1~ 10 VGLDMY1~4 TESTO1~38 TEST1. Connect to IOVcc. GND or leave this pin as open.40 ~ 3. reproduced. tie these pins to IOGNDDUM1~3. Output the IOVcc voltage level. In case of COG. Connect to IOVcc.30V 2.VCOML: Amplitude = electronic volumes VCOMH=VCOMR: Adjusted with an external resistor 1.VGL VCOMH . GND or leave these pins as open. Connect to IOVcc. These pins are internally shorted to GND. Leave them open. These pins are internally shorted to GND. GND or leave these pins as open. Connect to IOVcc. ILI9320 V0T. Dummy pad. Output the GND voltage level. Dummy pad. GND or leave this pin as open. Test Pads Dummy pads. Connect to IOVcc.0V 5 6 The information contained herein is the exclusive property of ILI Technology Corp. or disclosed in whole or in part without prior written permission of ILI Technology Corp. Dummy pads. GND or leave these pins as open. Leave them open. GND or leave these pins as open. DGND for the logic side: DGND = 0V.

VGL Vci .a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color Voltages VGH VGL VCL VGH . x8 Vci1 x-3. x3 Vci1 x6.5V ~ -12. 6.41 .0V Max. reproduced.5V -1. or disclosed in whole or in part without prior written permission of ILI Technology Corp. x-5 Vci1 x-1 ILI9320 7 Internal Step-up Circuits The information contained herein is the exclusive property of ILI Technology Corp. 30V Max. x7.9V ~ -3. Page 14 of 115 Version: 0. and shall not be distributed.0V Vci1 x2. x-4.VCL VLOUT1 (DDVDH) VLOUT2 (VGH) VLOUT3 (VGL) VCL 10V ~ 15V -4.

1 ~ 298) Input Pads Pad 1 to 298.. Page 15 of 115 Version: 0. or disclosed in whole or in part without prior written permission of ILI Technology Corp. Pad Arrangement and Coordination (1-a) DUMMYR1 DUMMYR2 TESTO1 VCCDUM1 VPP1 VPP1 VPP1 VPP2 VPP2 VPP2 VPP2 VPP2 VPP3 VPP3 VPP3 TESTO2 IOGNDDUM1 TESTO3 TEST1 TEST2 TEST4 TEST5 TEST3 IM0/ID IM1 IM2 IM3 TESTO4 IOVCCDUM1 TESTO5 nRESET VSYNC HSYNC DOTCLK ENABLE DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 TESTO6 IOGNDDUM2 TESTO7 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 SDO SDI nRD nWR/SCL RS nCS TESTO8 IOVCCDUM2 TESTO9 FMARK TS8 TS7 TS6 TS5 TS4 TS3 TS2 TS1 TS0 TSC TESTO10 IOGNDDUM3 TESTO11 TESTO12 OSC1DUM1 OSC1DUM2 OSC1 OSC1DUM3 OSC1DUM4 OSC2 OSC2DUM1 OSC2DUM2 DUMMYR3 DUMMYR4 IOGND IOGND IOGND IOGND IOGND IOGND IOGND IOVCC IOVCC IOVCC IOVCC IOVCC IOVCC IOVCC VCC VCC VCC VCC VCC VCC VCC VCC VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD TESTO13 VREFD TESTO14 VREF TESTO15 VREFC TESTO16 VDDTEST AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND TESTO17 VTEST TESTO18 VGS TESTO19 V0T TESTO20 VMON TESTO21 V31T VCOM VCOM VCOM VCOM VCOM VCOM VCOMH VCOMH VCOMH VCOMH VCOMH VCOMH VCOML VCOML VCOML VCOML VCOML VCOML TESTO22 TESTO23 VREG1OUT TESTO24 TESTA5 TESTO25 VCOMR TESTO26 VCL VCL VCL VLOUT1 VLOUT1 VLOUT1 DDVDH DDVDH DDVDH DDVDH DDVDH DDVDH DDVDH VCIOUT VCIOUT VCIOUT VCI1 VCI1 VCI1 VCI1 VCI1 VCILVL VCI VCI VCI VCI VCI VCI VCI VCI C12C12C12C12C12C12+ C12+ C12+ C12+ C12+ C11C11C11C11C11C11+ C11+ C11+ C11+ C11+ AGNDDUM1 VLOUT3 VLOUT3 VGL VGL VGL VGL VGL VGL VGL VGL VGL VGL AGNDDUM2 AGNDDUM3 AGNDDUM4 VLOUT2 VLOUT2 VGH VGH VGH VGH TESTO27 C13C13C13TESTO28 C13+ C13+ C13+ TESTO29 C21C21C21C21+ C21+ C21+ C22C22C22C22+ C22+ C22+ C23C23C23C23+ C23+ C23+ TESTO30 DUMMYR5 DUMMYR6 Chip Size: 21680um x 1250um Chip thickness : 400 um (typ.. reproduced. G312 G314 G316 G318 G320 VGLDMY3 TESTO36 220um Alignment Marks Alignment Mark: 1-a. 1-b. 21um x 100um (No. ………………………. ……………………………………………………………………………………………….a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 5. 100um S712 S713 S714 S715 S716 S717 S718 S719 S720 TESTO34 220um TESTO33 VGLDMY2 G319 G317 G315 G313 G311 ………………………………………………………………………………………. Bump View ILI9320 G9 G7 G5 G3 G1 VGLDMY1 DUMMYR8 DUMMYR7 TESTO32 TESTO31 (1-b) The information contained herein is the exclusive property of ILI Technology Corp. TESTO38 TESTO37 DUMMYR10 DUMMYR9 VGLDMY4 G2 G4 G6 G8 G10 ……………………….. 299 ~ 1354) Gate: G1 ~ G320 Source: S1 ~ S720 2.41 ………………………………………………………………………………………. Coordinate Origin: Chip center Au bump height: 15um (typ.) Pad Location: Pad Center..) Au Bump Size: 1.. and shall not be distributed.. 50um x 80um (No. 30 40 30 ………………………………………………………………………………………………. TESTO35 S1 S2 S3 S4 S5 S6 S7 S8 S9 1 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 Face Up (Bump View) 9 0 1 0 0 1 1 0 1 2 0 30 40 30 1 3 0 1 4 0 Y 1 5 0 X 1 6 0 1 7 0 1 8 0 1 9 0 2 0 0 2 1 0 2 2 0 2 3 0 2 4 0 2 5 0 2 6 0 2 7 0 2 8 0 2 9 0 2 9 8 .

5 181 VCOMH 182 VCOMH 183 VCOML 184 VCOML 185 VCOML 186 VCOML 187 VCOML 188 VCOML 189 TESTO22 190 TESTO23 192 TESTO24 193 TESTA5 194 TESTO25 195 VCOMR 196 TESTO26 197 VCL 198 VCL 199 VCL 200 VLOUT1 201 VLOUT1 202 VLOUT1 203 DDVDH 204 DDVDH 205 DDVDH 206 DDVDH 207 DDVDH 208 DDVDH 209 DDVDH 210 VCIOUT 211 VCIOUT 212 VCIOUT 213 VCI1 214 VCI1 215 VCI1 216 VCI1 217 VCI1 218 VCILVL 219 VCI 220 VCI 221 VCI 222 VCI 223 VCI 224 VCI 225 VCI 226 VCI 227 C12228 C12229 C12230 C12231 C12232 C12+ 233 C12+ 234 C12+ 235 C12+ 236 C12+ 237 C11238 C11239 C11240 C11- 2205.0 -517.5 6335.5 -7105.0 -517.5 6615.0 -517.5 9625.0 -517.5 -3815.5 3745. 61 RS Name X Y No.5 -2625.0 -517.0 -517.5 3535.0 -517.5 385.5 5705.0 -517.5 -5075.5 9835.5 -3325.5 8505.0 -517.0 -517.0 -517.0 -517.0 -517.5 -105.0 -517.0 -517.5 9345.0 -517.0 -517.0 -517.5 -5845.0 -517.5 8295.5 5495.0 -517.0 -517.0 -517.5 1365.5 7315.0 511.5 8715.0 -517.0 -517.5 -9905.5 -5705.0 -517.5 121 VDD 122 VDD 123 VDD 124 VDD 125 VDD 127 VREFD 129 VREF 131 VREFC -1995.5 6195.0 -517.5 2625.5 -2485.0 -517.0 -517.5 875.5 128 TESTO14 -1505.5 -6825.0 -517.0 -517.0 -517.5 -2975.5 -9975.0 -517.5 -805.5 7455.5 2555.0 -517.5 -3885.0 -517.5 130 TESTO15 -1365.5 9065.5 6475.0 -517.5 7735.0 -517.5 132 TESTO16 -1225.5 -9625.5 -6195.0 -517.5 -4025.0 -517.0 -517.5 1015.5 2835.0 -517.0 -517.5 -6265.5 10650.0 -517.5 -9065.0 -517.0 -517.5 9485.5 -385.0 -517. Name X Y No.5 -4305.0 -517.0 -517.5 5075.5 3675.5 -4655.0 -517.5 4025.5 -8995.0 -517.0 -517.5 4515.0 -517.5 455.5 5565.0 -517.5 -2345.0 -517.5 -1295.5 6055.5 -7315.0 -517.5 2695.0 -517.5 -8925.0 -517.0 -517.0 -517.0 -517.5 7175.5 8435.0 -517.5 -7595.0 -517. Name X Y 241 C11242 C11+ 243 C11+ 244 C11+ 245 C11+ 246 C11+ 247 AGNDDUM1 248 VLOUT3 249 VLOUT3 250 VGL 251 VGL 252 VGL 253 VGL 254 VGL 255 VGL 256 VGL 257 VGL 258 VGL 259 VGL 260 AGNDDUM2 261 AGNDDUM3 262 AGNDDUM4 263 VLOUT2 264 VLOUT2 265 VGH 266 VGH 267 VGH 268 VGH 269 TESTO27 270 C13271 C13272 C13273 TESTO28 274 C13+ 275 C13+ 276 C13+ 277 TESTO29 278 C21279 C21280 C21281 C21+ 282 C21+ 283 C21+ 284 C22285 C22286 C22287 C22+ 288 C22+ 289 C22+ 290 C23291 C23292 C23293 C23+ 294 C23+ 295 C23+ 296 TESTO30 297 DUMMYR5 298 DUMMYR6 299 TESTO31 300 TESTO32 6405.0 -517.5 4655.0 -517.0 -517.0 -517.0 -517.5 -7525.5 -1855.0 -517.5 -6545.5 6265.5 -2905.5 735.0 -517.0 -517.0 -517.0 -517.0 -517.5 4935.0 -517.0 -517.5 -3255. reproduced.0 -517.5 7105.0 -517.5 9415.0 -517.0 -517.0 -517.5 -5915.0 -517.0 -517.0 -517.0 -517.0 -517.0 -517.5 1155.0 -517.5 -3605.5 -8715.5 The information contained herein is the exclusive property of ILI Technology Corp.5 -8155.5 -8575.5 -6685.5 10325.5 -8855.5 9905.5 -10255.5 -2695.5 -9275.0 -517.5 -4865.0 -517.5 245.5 9555.0 -517.5 5355.5 4725.0 -517.5 -4725.5 9135.0 -517.5 -3535.5 -4585.0 -517.0 -517.5 -7945.0 -517.5 1645.5 3115.5 9765.5 7665.0 -517.0 386.0 -517.0 -517. Name X Y No.0 -517.0 -517.5 126 TESTO13 -1645.5 -10115.0 -517.0 -517.5 -1925.5 -7665.41 .5 8785.5 -4235. and shall not be distributed.5 2065.0 -517.5 -5635.5 315.0 -517.5 -2555.0 -517.0 -517.0 -517.5 62 CS* 63 TESTO8 65 TESTO9 66 FMARK 67 TS8 68 TS7 69 TS6 70 TS5 71 TS4 72 TS3 73 TS2 74 TS1 75 TS0 76 TSC 77 TESTO10 79 TESTO11 80 TESTO12 81 OSC1DUM1 82 OSC1DUM2 83 OSC1 84 OSC1DUM3 85 OSC1DUM4 86 OSC2 87 OSC2DUM1 88 OSC2DUM2 89 DUMMYR3 90 DUMMYR4 91 IOGND 92 IOGND 93 IOGND 94 IOGND 95 IOGND 96 IOGND 97 IOGND 98 IOVCC 99 IOVCC 100 IOVCC 101 IOVCC 102 IOVCC 103 IOVCC 104 IOVCC 105 VCC 106 VCC 107 VCC 108 VCC 109 VCC 110 VCC 111 VCC 112 VCC 113 VDD 114 VDD 115 VDD 116 VDD 117 VDD 118 VDD 119 VDD 120 VDD 64 IOVCCDUM2 -5985.0 -517.0 -517.0 -517.5 1995.5 4235.0 -517.0 -517.0 -517.0 -517.5 -2835.0 -517.5 2275.5 -2205.0 -517.0 -517.0 -517. Name X 1 DUMMYR1 2 DUMMYR2 3 TESTO1 4 VCCDUM1 5 VPP1 6 VPP1 7 VPP1 8 VPP2 9 VPP2 10 VPP2 11 VPP2 12 VPP2 13 VPP3 14 VPP3 15 VPP3 16 TESTO2 17 IOGNDDUM1 18 TESTO3 19 TEST1 20 TEST2 21 TEST4 22 TEST5 23 TEST3 24 IM0/ID 25 IM1 26 IM2 27 IM3 28 TESTO4 29 IOVCCDUM1 30 TESTO5 31 RESET* 32 VSYNC 33 HSYNC 34 DOTCLK 35 ENABLE 36 DB17 37 DB16 38 DB15 39 DB14 40 DB13 41 DB12 42 DB11 43 DB10 44 DB9 45 DB8 46 TESTO6 47 IOGNDDUM2 48 TESTO7 49 DB7 50 DB6 51 DB5 52 DB4 53 DB3 54 DB2 55 DB1 56 DB0 57 SDO 58 SDI 59 RD* 60 WR*/SCL -10395.0 -517.5 -8015.5 -2275.0 -517.0 -517.5 -6055.0 -517.5 -7385.0 -517.0 -517.5 4375.0 -517.0 -517.0 -517.5 7805.5 -9695.0 -517.5 -8505.5 6755.0 -517.5 10670. Page 16 of 115 Version: 0.0 -517.5 -9415.0 -517.0 -517.5 8365.5 5985.0 -517.5 175.0 -517.0 -517.0 -517.0 -517.5 2415.0 -517.5 -8085.0 -517.0 -517.0 -517.5 -5775.5 -315.0 -517.5 -9555.5 -6475.5 -5355.5 -9485.5 -10185.0 -517.5 4865.0 -517.0 -517.0 -517.0 -517.5 945.0 -517.0 -517.5 -9135.5 -175.5 -6615.5 -2765.5 -875.0 -517.5 7035.5 -1715.0 -517.5 1225.0 -517.5 7595.0 -517.5 -4375.5 -7035.0 -517.5 2345.0 -517.0 -517.0 -517.5 525.5 -6755.5 2765.5 665.0 -517.0 -517.5 -10045.0 -517.0 -517.5 3255.5 -35.0 -517.5 -945.0 -517.5 -7805.0 -517.5 10395.0 -517.5 1435.5 -3045.5 -8225.5 4165.0 -517.5 9695.0 -517.5 -4095.0 -517.5 4445.5 -8435.0 -517.0 -517.0 -517.0 -517.5 -525.0 -517.0 -517.0 -517.0 -517.5 4795.0 -517.0 -517.0 -517.5 -7175.5 -5425.5 -6125.5 5005.0 -517.5 6545.0 -517.0 -517.5 -4515.5 3885.0 -517.5 -2135.0 -517.0 -517.5 6125.0 -517.0 -517.5 -3115.0 -517.5 1785.0 -517.5 2975.5 -9835.0 -517.0 -517.0 -517.5 -3395.0 -517.5 8015.0 -517.5 -9765.5 10255.0 -517.5 -5565.5 10045.0 -517.5 -9205.0 -517.5 2135.0 -517.5 9205.0 -517.0 -517.5 -4795.0 -517.5 8995.0 -517.5 -5285.5 -665.0 -517.5 6685.0 -517.0 -517.5 -7245.5 35.5 -245.5 -5145.5 5215.5 -8295.5 -7875.5 9975.5 -6335.0 -517.0 -517.0 -517.5 2485.5 -4445.5 7875.0 -517.0 -517.5 -735.5 1575.5 -3745.5 5635.0 -517.0 -517.0 -517.0 -517.5 3045.0 -517.0 -517.5 -8645.5 -6895.0 -517.0 -517.0 -517.0 -517.0 -517.0 -517.0 -517.0 -517.5 8155.5 8645.0 -517.0 -517.5 -6405.5 -5215.5 10185.5 -8365.5 7245.0 -517.5 1505.5 -3185.0 -517.0 -517.0 -517.0 -517.0 -517.5 3395.5 -1575.5 -2415.0 -517.5 6895.5 No.0 -517.5 3815.0 -517.0 -517.0 -517.5 4585.0 -517.5 1925.0 -517.5 -6965.0 -517.5 8855.0 -517.0 -517.5 -9345.5 5425.0 -517.0 -517.5 7945.0 -517.5 -595.0 -517.5 -7735.5 8085.0 -517.5 8225.0 -517.5 10115.5 -5495.5 -1785.0 -517.5 -7455.0 -517.5 5915.5 3465.5 8925.0 -517.0 -517.5 1715.0 -517.5 595.5 5845.0 -517.0 -517.0 -517.5 3185.5 3325.0 -517.0 -517.5 -4165.5 5285.0 -517.0 -517.0 -517.5 8575.5 -8785.0 -517.5 -3955.0 -517.5 5775.0 -517.0 -517.5 1085.5 3955.5 -455.0 -517.0 -517.5 -4935.0 -517.5 -1015.0 -517.0 -517.5 3605.0 -517.0 -517.0 -517.5 1295.5 9275.0 -517.5 191 VREG1OUT 2905.5 805.0 -517. or disclosed in whole or in part without prior written permission of ILI Technology Corp.0 -517.0 -517.5 4095.0 -517.0 -517.5 -10325.0 -517.5 7525.5 105.0 -517.0 -517.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 Y No.0 -517.5 78 IOGNDDUM3 -5005.0 -517.0 -517.0 -517.0 -517.5 7385.0 -517.5 133 VDDTEST -1155.5 -3465.5 -3675.5 6965.5 5145.5 1855.0 -517.0 -517.5 -2065.0 -517.0 -517.5 4305.0 -517.0 -517.0 -517.0 -517.5 -1435.5 134 AGND 135 AGND 136 AGND 137 AGND 138 AGND 139 AGND 140 AGND 141 AGND 142 AGND 143 AGND 144 AGND 145 GND 146 GND 147 GND 148 GND 149 GND 150 GND 151 GND 152 GND 153 GND 154 GND 155 GND 156 GND 157 GND 158 GND 159 GND 160 GND 161 TESTO17 162 VTEST 163 TESTO18 164 VGS 165 TESTO19 166 V0T 167 TESTO20 168 VMON 169 TESTO21 170 V31T 171 VCOM 172 VCOM 173 VCOM 174 VCOM 175 VCOM 176 VCOM 177 VCOMH 178 VCOMH 179 VCOMH 180 VCOMH -1085.0 -517.0 -517.5 6825.0 -517.

5 511.0 8510.0 9450.5 511.5 511.0 9470.0 8630.5 511.0 4690.0 6170.5 386.0 9130.5 386.5 386.0 7450.0 10010.5 511.0 9650.0 8450.0 6390.0 7790.5 386.0 7810.5 511.0 9890.0 5030.0 10410.5 511.0 5970.5 511.5 386.5 386.5 511.0 8950.5 511.0 8090.0 6790.0 9830.0 8830.0 6730.5 511.0 4470.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color No.5 386.5 511.0 Y 511.5 386.0 10470.5 511.0 4550.5 386.5 511.5 No.0 9090.5 386.5 386.5 No.5 511.5 511.0 9990.5 511.5 511.5 386.5 386.0 10230.0 5770.5 511.0 6150.5 511.5 511.5 386.0 5230. Name X 9430.5 511.5 386.5 386.0 9670.5 386.5 511.5 386.0 5370.0 4490.5 511.0 5130.0 7870.0 4930.5 386.0 4510.5 511.0 6890.0 5190.0 7130.5 511.0 6350.5 511.5 511.5 511.0 9010.5 386.0 6530.0 9970.0 10490.5 541 S646 542 S645 543 S644 544 S643 545 S642 546 S641 547 S640 548 S639 549 S638 550 S637 551 S636 552 S635 553 S634 554 S633 555 S632 556 S631 557 S630 558 S629 559 S628 560 S627 561 S626 562 S625 563 S624 564 S623 565 S622 566 S621 567 S620 568 S619 569 S618 570 S617 571 S616 572 S615 573 S614 574 S613 575 S612 576 S611 577 S610 578 S609 579 S608 580 S607 581 S606 582 S605 583 S604 584 S603 585 S602 586 S601 587 S600 588 S599 589 S598 590 S597 591 S596 592 S595 593 S594 594 S593 595 S592 596 S591 597 S590 598 S589 599 S588 600 S587 301 DUMMYR7 302 DUMMYR8 303 VGLDMY1 304 G1 305 G3 306 G5 307 G7 308 G9 309 G11 310 G13 311 G15 312 G17 313 G19 314 G21 315 G23 316 G25 317 G27 318 G29 319 G31 320 G33 321 G35 322 G37 323 G39 324 G41 325 G43 326 G45 327 G47 328 G49 329 G51 330 G53 331 G55 332 G57 333 G59 334 G61 335 G63 336 G65 337 G67 338 G69 339 G71 340 G73 341 G75 342 G77 343 G79 344 G81 345 G83 346 G85 347 G87 348 G89 349 G91 350 G93 351 G95 352 G97 353 G99 354 G101 355 G103 356 G105 357 G107 358 G109 359 G111 360 G113 361 G115 362 G117 363 G119 364 G121 365 G123 366 G125 367 G127 368 G129 369 G131 370 G133 371 G135 372 G137 373 G139 374 G141 375 G143 376 G145 377 G147 378 G149 379 G151 380 G153 381 G155 382 G157 383 G159 384 G161 385 G163 386 G165 387 G167 388 G169 389 G171 390 G173 391 G175 392 G177 393 G179 394 G181 395 G183 396 G185 397 G187 398 G189 399 G191 400 G193 401 G195 402 G197 403 G199 404 G201 405 G203 406 G205 407 G207 408 G209 409 G211 410 G213 411 G215 412 G217 413 G219 414 G221 415 G223 416 G225 417 G227 418 G229 419 G231 420 G233 421 G235 422 G237 423 G239 424 G241 425 G243 426 G245 427 G247 428 G249 429 G251 430 G253 431 G255 432 G257 433 G259 434 G261 435 G263 436 G265 437 G267 438 G269 439 G271 440 G273 441 G275 442 G277 443 G279 444 G281 445 G283 446 G285 447 G287 448 G289 449 G291 450 G293 451 G295 452 G297 453 G299 454 G301 455 G303 456 G305 457 G307 458 G309 459 G311 460 G313 461 G315 462 G317 463 G319 464 VGLDMY2 465 TESTO33 466 TESTO34 467 S720 468 S719 469 S718 470 S717 471 S716 472 S715 473 S714 474 S713 475 S712 476 S711 477 S710 478 S709 479 S708 480 S707 481 S706 482 S705 483 S704 484 S703 485 S702 486 S701 487 S700 488 S699 489 S698 490 S697 491 S696 492 S695 493 S694 494 S693 495 S692 496 S691 497 S690 498 S689 499 S688 500 S687 501 S686 502 S685 503 S684 504 S683 505 S682 506 S681 507 S680 508 S679 509 S678 510 S677 511 S676 512 S675 513 S674 514 S673 515 S672 516 S671 517 S670 518 S669 519 S668 520 S667 521 S666 522 S665 523 S664 524 S663 525 S662 526 S661 527 S660 528 S659 529 S658 530 S657 531 S656 532 S655 533 S654 534 S653 535 S652 536 S651 537 S650 538 S649 539 S648 540 S647 The information contained herein is the exclusive property of ILI Technology Corp.5 511.5 386.5 386.5 386.0 9330.0 9570.0 6310.0 9170.0 6950.0 4710.5 386.5 511. reproduced.5 386.5 511.5 386.5 386.5 386.5 386.5 511. or disclosed in whole or in part without prior written permission of ILI Technology Corp.5 386.0 Y 511.0 8650.0 5990.0 6330.0 Y 386.5 No.5 386.5 511.0 9610. Page 17 of 115 Version: 0.5 511.0 8390.0 10350.0 4450.0 4530.5 511.0 7490.5 386.0 9630.5 511.5 511.5 386.5 511.0 8150.0 6870.0 6770.0 5470.5 511.5 386.0 8190.0 10290.0 8870.5 386.5 386.5 386.0 7690.5 386.0 9350.5 511.5 386.0 9810.5 386.5 386.5 511.0 9710.0 4830.5 511.5 511.0 6230.0 6010.0 5210.5 511.5 511.0 6750.0 7110.5 386.5 511.0 5310.5 386.5 511.0 8030.0 8050.5 386.0 9530.0 7570.5 386.5 511.5 386.0 7890.0 5610.0 5430.5 386.5 386.0 4950.5 386.0 Y 511.5 511.0 6470.5 511.5 386.0 6610.5 511.0 7470.0 8310.5 511.5 511.0 5390.0 10390.0 7070.0 10210.5 511.5 386.0 7530.5 511.0 7930.5 386.0 6650.5 511.5 511.5 386.0 4890.5 386.0 7390.5 386.0 10530.5 386.5 511.0 8730.0 6670.5 511.5 386.0 9850.5 386.5 386.0 4650.0 10170.5 386.0 5330.5 511.5 511.5 386.0 5250.0 8130.0 7750.0 10150.5 386.0 4750.5 511.5 511.5 386.0 7510.0 10090.0 7010. and shall not be distributed.0 6110.5 511.5 386.0 5110.0 8710.0 10070.0 8690.5 511.0 8670.5 511.5 511.0 5690.5 511.0 10130.0 7350.5 511. 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ILI9320 Name X -370.5 511.0 -590.0 2270.5 386.0 -1210.0 4130.5 511.5 386.5 511.5 841 S346 842 S345 843 S344 844 S343 845 S342 846 S341 847 S340 848 S339 849 S338 850 S337 851 S336 852 S335 853 S334 854 S333 855 S332 856 S331 857 S330 858 S329 859 S328 860 S327 861 S326 862 S325 863 S324 864 S323 865 S322 866 S321 867 S320 868 S319 869 S318 870 S317 871 S316 872 S315 873 S314 874 S313 875 S312 876 S311 877 S310 878 S309 879 S308 880 S307 881 S306 882 S305 883 S304 884 S303 885 S302 886 S301 887 S300 888 S299 889 S298 890 S297 891 S296 892 S295 893 S294 894 S293 895 S292 896 S291 897 S290 898 S289 899 S288 900 S287 601 S586 602 S585 603 S584 604 S583 605 S582 606 S581 607 S580 608 S579 609 S578 610 S577 611 S576 612 S575 613 S574 614 S573 615 S572 616 S571 617 S570 618 S569 619 S568 620 S567 621 S566 622 S565 623 S564 624 S563 625 S562 626 S561 627 S560 628 S559 629 S558 630 S557 631 S556 632 S555 633 S554 634 S553 635 S552 636 S551 637 S550 638 S549 639 S548 640 S547 641 S546 642 S545 643 S544 644 S543 645 S542 646 S541 647 S540 648 S539 649 S538 650 S537 651 S536 652 S535 653 S534 654 S533 655 S532 656 S531 657 S530 658 S529 659 S720 660 S527 661 S526 662 S525 663 S524 664 S523 665 S522 666 S521 667 S520 668 S519 669 S518 670 S517 671 S516 672 S515 673 S514 674 S513 675 S512 676 S511 677 S510 678 S509 679 S508 680 S507 681 S506 682 S505 683 S504 684 S503 685 S502 686 S501 687 S500 688 S499 689 S498 690 S497 691 S496 692 S495 693 S494 694 S493 695 S492 696 S491 697 S490 698 S489 699 S488 700 S487 701 S486 702 S485 703 S484 704 S483 705 S482 706 S481 707 S480 708 S479 709 S478 710 S477 711 S476 712 S475 713 S474 714 S473 715 S472 716 S471 717 S470 718 S469 719 S468 720 S467 721 S466 722 S465 723 S464 724 S463 725 S462 726 S461 727 S460 728 S459 729 S458 730 S457 731 S456 732 S455 733 S454 734 S453 735 S452 736 S451 737 S450 738 S449 739 S448 740 S447 741 S446 742 S445 743 S444 744 S443 745 S442 746 S441 747 S440 748 S439 749 S438 750 S437 751 S436 752 S435 753 S434 754 S433 755 S432 756 S431 757 S430 758 S429 759 S428 760 S427 761 S426 762 S425 763 S424 764 S423 765 S422 766 S421 767 S420 768 S419 769 S418 770 S417 771 S416 772 S415 773 S414 774 S413 775 S412 776 S411 777 S410 778 S409 779 S408 780 S407 781 S406 782 S405 783 S404 784 S403 785 S402 786 S401 787 S400 788 S399 789 S398 790 S397 791 S396 792 S395 793 S394 794 S393 795 S392 796 S391 797 S390 798 S389 799 S388 800 S387 801 S386 802 S385 803 S384 804 S383 805 S382 806 S381 807 S380 808 S379 809 S378 810 S377 811 S376 812 S375 813 S374 814 S373 815 S372 816 S371 817 S370 818 S369 819 S368 820 S367 821 S366 822 S365 823 S364 824 S363 825 S362 826 S361 827 S360 828 S359 829 S358 830 S357 831 S356 832 S355 833 S354 834 S353 835 S352 836 S351 837 S350 838 S349 839 S348 840 S347 The information contained herein is the exclusive property of ILI Technology Corp.5 386.5 511.5 386.0 -1410.0 3810.5 386.5 511.5 386.0 430.5 511.0 2350.0 2090.0 550.5 386.5 511.0 4210.0 4270.0 4070.0 -1390.0 -1530.0 730.0 4330.5 No.0 1350.5 386.5 386.5 511.0 1750.5 386.5 511.0 -1470.0 2710.0 -410.0 3130.5 511.0 230.0 -1010.5 386.5 386.0 950.0 290.5 511.0 3570.5 No.0 2310.0 790.5 386.0 4050.5 511.0 510.0 1850.5 386.5 511.5 386.5 386.5 511.5 511.5 511.5 386.0 190.5 386.0 -570.0 -810.5 386.0 -30.0 -550.5 386.0 2370.5 511.0 -1350.5 511.0 1770.5 511.5 386.0 1270.5 386.5 386.5 511.5 511.0 4090.0 -1050.5 511.5 511.0 -470.5 386.0 -1430.0 -90.5 386.0 2750.0 10.0 2290.0 670.5 386.0 -630.5 511.5 511.5 386.5 511.5 511.5 386.0 1830.0 2890.0 1250.0 530.5 386.0 1050.0 -450.0 -930.5 386.0 4370.0 -710.0 -1450.0 3770.5 511.5 511.0 3710.0 3830.0 210.0 910.0 -130.5 511.5 511.5 511.5 511.0 -730.0 650.5 511.5 511. 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Name X 2030.0 -970.0 4030.5 511.5 386.0 -1510.0 4010.0 4230.0 -150.0 1970.0 390.0 4190.0 3250.5 386.5 511.5 386.0 1890.5 511.0 990.0 4350.5 511.5 511.0 2790.0 3970.5 511.5 386.0 70.5 386.5 511.5 511.0 -1190.5 511.5 511.5 511.5 386.0 3910.5 511.0 4310.5 386.5 386.5 386.0 1710.0 1330.5 511.0 1670.0 1450.0 2650.5 386.5 511.5 386.5 511.0 -830.0 3730.5 511.0 890.0 -310.0 2730.0 770.5 511.0 2850.0 4170.5 386.5 386.5 511.0 3530.0 3030.0 570.5 511.5 511.0 -1330.0 1950.0 3550.0 -510.0 3850.0 2690.5 386.5 386.0 3110.0 -70.0 350.5 511.0 490.0 -990.0 3870.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color No.0 -690.0 Y 386.5 386.0 3630.0 1730.0 1370.5 386.0 2110.5 386.0 1230.0 Y 386.0 2550.5 386.5 386.5 511.5 386.0 1190.0 250.5 511.0 -350.5 511. or disclosed in whole or in part without prior written permission of ILI Technology Corp.0 3310.0 310.0 2150.5 386.0 2590.5 386.0 330.5 386.5 386.5 511.0 -1250.0 -1070.5 386.0 -530.0 170.0 3390.0 870.5 386.0 -270.5 386.0 -1130.5 511.5 511.5 386.5 386.5 386.5 511.5 511.0 -770.0 1110.0 -1370.0 3450.5 511.5 511.5 386.5 511.0 3210.0 2970.0 1510.5 511. and shall not be distributed.0 1010.5 386.0 -870.5 511.5 511.0 30.0 3670.5 511.5 511.0 2990.0 3650.5 386.5 511.0 4390.0 4290.5 386.

0 -3210.5 511. Name X -5170. or disclosed in whole or in part without prior written permission of ILI Technology Corp.5 511.5 386.0 -7210.5 511.0 -6390.0 -7450.0 -5010.5 511.5 386.5 No.5 511.5 511.0 -4070.0 Y 386.0 -6210.0 -5850.5 386.0 -3590.0 -3570.5 511.0 -4730.0 -4790.0 -3270.0 -2170.0 -2130.0 -2630.0 -4130.5 511.0 -2090.5 386.0 -6930.0 -5030.0 -2010.5 511.5 511.5 511.5 386.41 .5 511.5 511.5 No.5 386.5 386.0 -2150.5 386.0 -4110.5 386.5 511.0 -2510.5 511.0 -7570.0 -7290.5 511.0 -7070.5 386.5 386.0 -7050.0 -4310.5 386.0 -4710.5 511.0 -3050.0 -4330.0 -3170.0 -1890.5 386.0 -5790.0 -3730.0 -4750.5 511.0 -2470.0 -6810.0 -2190.0 -5870.5 386.5 386.5 386.0 -6290.5 511.0 -6990.5 511.0 -5910.5 386.5 386.0 -2650.0 -6310.0 -5950.5 386.5 511.0 -4510.5 511.0 -5630.0 -3910.0 -2450.0 -5270.0 -3890.5 386.5 511.5 511.5 386.5 386.0 -2430.0 -7170.0 -6410.5 511.0 -2670.0 -5430.0 -4950.5 386.5 386.0 Y 386.0 -5410.0 -7590.5 386.5 386.5 511.0 -5070.5 386.5 511.5 511.5 386.0 -1650.5 511.5 511.0 -4690.0 -2110.0 -2410.5 386.5 511.5 386.5 386.5 511.5 511.0 -5250.5 386.0 -6890.5 511.0 -6570.0 -6270.5 386.5 511.0 -2350.5 386.5 386.0 -6530.0 -4350.5 511.5 386.5 386.0 -5930.0 -1590.5 511.5 386.0 -7150.5 386.0 -4870.5 386.5 511.5 386.0 -2270.5 386.0 -6350.0 -1670.5 511. and shall not be distributed.0 -4590.0 -2610.5 511.5 386.0 -6830.0 -6090.5 511.0 -2570.0 -3550.5 386.5 511.0 -5530.5 511.0 -1690. Name X -3970.0 -1850.5 511.0 -3070.0 -5810.0 -6170.0 -5710.5 386.5 511.0 -7190.0 -4010.5 511.0 -3390.5 386.0 -3830.5 386.5 No.0 -6230.5 386.0 -3530.0 -4450.5 386.0 -3950.5 511.0 -1710.0 -2730.0 -6450.5 511.0 -2910.5 511.0 -6670.5 511.0 -6150.0 -2370.0 -7370.0 -5110.5 386.0 -6850.0 -4210.0 Y 386.0 -2310.5 386.0 -3470.5 511.5 511.0 -1930.5 511.5 511.0 -2890.0 -7010.5 511.0 -3430.5 511.0 -4470.5 511.5 386.5 511.5 511.0 -3870.0 -6590.0 -2230.0 -3490.5 386.5 511.0 -2970.5 386.5 386.5 386.5 511.5 386.0 -6130.0 -3010.0 -6690.0 -3930.0 -3350.5 511.0 -6510.5 511.0 -5510.0 -2490.0 -4770. reproduced.5 386.5 386.0 -3250.5 386.0 -3290.5 386.5 511.0 -4910.5 511.0 -4430.0 -3190.0 -5390.0 -2290.0 -6250.0 961 S226 962 S225 963 S224 964 S223 965 S222 966 S221 967 S220 968 S219 969 S218 970 S217 971 S216 972 S215 973 S214 974 S213 975 S212 976 S211 977 S210 978 S209 979 S208 980 S207 981 S206 982 S205 983 S204 984 S203 985 S202 986 S201 987 S200 988 S199 989 S198 990 S197 991 S196 992 S195 993 S194 994 S193 995 S192 996 S191 997 S190 998 S189 999 S188 1000 S187 1001 S186 1002 S185 1003 S184 1004 S183 1005 S182 1006 S181 1007 S180 1008 S179 1009 S178 1010 S177 1011 S176 1012 S175 1013 S174 1014 S173 1015 S172 1016 S171 1017 S170 1018 S169 1019 S168 1020 S167 1021 S166 1022 S165 1023 S164 1024 S163 1025 S162 1026 S161 1027 S160 1028 S159 1029 S158 1030 S157 1031 S156 1032 S155 1033 S154 1034 S153 1035 S152 1036 S151 1037 S150 1038 S149 1039 S148 1040 S147 1041 S146 1042 S145 1043 S144 1044 S143 1045 S142 1046 S141 1047 S140 1048 S139 1049 S138 1050 S137 1051 S136 1052 S135 1053 S134 1054 S133 1055 S132 1056 S131 1057 S130 1058 S129 1059 S128 1060 S127 1061 S126 1062 S125 1063 S124 1064 S123 1065 S122 1066 S121 1067 S120 1068 S119 1069 S118 1070 S117 1071 S116 1072 S115 1073 S114 1074 S113 1075 S112 1076 S111 1077 S110 1078 S109 1079 S108 1080 S107 1081 S106 1082 S105 1083 S104 1084 S103 1085 S102 1086 S101 1087 S100 1088 S99 1089 S98 1090 S97 1091 S96 1092 S95 1093 S94 1094 S93 1095 S92 1096 S91 1097 S90 1098 S89 1099 S88 1100 S87 1101 S86 1102 S85 1103 S84 1104 S83 1105 S82 1106 S81 1107 S80 1108 S79 1109 S78 1110 S77 1111 S76 1112 S75 1113 S74 1114 S73 1115 S72 1116 S71 1117 S70 1118 S69 1119 S68 1120 S67 1121 S66 1122 S65 1123 S64 1124 S63 1125 S62 1126 S61 1127 S60 1128 S59 1129 S58 1130 S57 1131 S56 1132 S55 1133 S54 1134 S53 1135 S52 1136 S51 1137 S50 1138 S49 1139 S48 1140 S47 The information contained herein is the exclusive property of ILI Technology Corp.5 511.0 -6970.5 511.5 386.0 -5970.0 -5290.5 511.5 386.0 -3130.5 511.5 386.0 -7270.5 386.0 -4230.5 386.5 511.5 511.5 386.0 -3110.0 -5690.5 511.5 386.0 -2870.0 -5210.5 386.5 511.5 511.0 -7230.5 386.0 -3630.5 386.0 -5750.5 386.0 -3410.5 386.5 386.5 386.5 386.0 -5610.5 511.5 511.5 386.0 -6610.0 -5730.5 511.5 386.5 511.5 386.5 511.5 386.5 386.5 511.0 -3030.5 511.5 386.0 -2530.5 511.5 511.0 -3310.5 386.0 -3990.0 -5890.5 511.5 386.0 -6790.0 -1910.5 386.0 -4090.0 -4630.5 511.5 511.0 Y 386.0 -2690.5 386.0 -4670.0 -2390.0 -4390.0 -1950.5 511.5 386.5 386. Name X -2770.5 386.5 511.5 511.5 386.5 511.5 511.5 511.0 -4970.0 -7490.5 386.0 -4370.5 386.0 -7030.5 386.0 -6070.0 -2590.0 -2930.0 -2850.0 -3370.0 -4990.0 -6050.5 386.5 511.0 -4250.5 511.5 511.5 386.0 -5590.0 -6030.5 386.5 386.5 386.0 -6550.5 1141 S46 1142 S45 1143 S44 1144 S43 1145 S42 1146 S41 1147 S40 1148 S39 1149 S38 1150 S37 1151 S36 1152 S35 1153 S34 1154 S33 1155 S32 1156 S31 1157 S30 1158 S29 1159 S28 1160 S27 1161 S26 1162 S25 1163 S24 1164 S23 1165 S22 1166 S21 1167 S20 1168 S19 1169 S18 1170 S17 1171 S16 1172 S15 1173 S14 1174 S13 1175 S12 1176 S11 1177 S10 1178 S9 1179 S8 1180 S7 1181 S6 1182 S5 1183 S4 1184 S3 1185 S2 1186 S1 1187 TESTO35 1188 TESTO36 1189 VGLDMY3 1190 G320 1191 G318 1192 G316 1193 G314 1194 G312 1195 G310 1196 G308 1197 G306 1198 G304 1199 G302 1200 G300 No.5 386.5 386.0 -4830. Name 901 S286 902 S285 903 S284 904 S283 905 S282 906 S281 907 S280 908 S279 909 S278 910 S277 911 S276 912 S275 913 S274 914 S273 915 S272 916 S271 917 S270 918 S269 919 S268 920 S267 921 S266 922 S265 923 S264 924 S263 925 S262 926 S261 927 S260 928 S259 929 S258 930 S257 931 S256 932 S255 933 S254 934 S253 935 S252 936 S251 937 S250 938 S249 939 S248 940 S247 941 S246 942 S245 943 S244 944 S243 945 S242 946 S241 947 S240 948 S239 949 S238 950 S237 951 S236 952 S235 953 S234 954 S233 955 S232 956 S231 957 S230 958 S229 959 S228 960 S227 X -1570.5 386.5 386.0 -3330.0 -3510.5 511.0 -2210.0 -7410.0 -7130.0 -5370.5 No.5 511.0 -3750.0 -3650.5 511.0 -3710.5 511.5 386.0 -6650.5 511.0 -7430.5 511.0 -6430. Name X -6370.5 511.5 511.0 -4550.5 511.0 -4290.0 -1750.0 -4850.0 -4170.0 -5490.5 386.0 -1770. Page 19 of 115 Version: 0.5 511.0 -7550.5 386.5 511.5 386.0 -2550.5 511.5 386.5 511.5 386.5 386.0 -2050.5 386.5 386.5 511.0 -5670.5 386.0 -4810.5 386.0 -6910.0 -3770.0 -4930.5 386.5 511.5 386.0 -2250.5 511.5 511.0 -5230.5 511.0 -2990.5 511.5 511.0 -6870.0 -2710.5 511.0 -1830.0 -4190.0 -5570.5 511.5 386.0 -7110.0 -5830.0 -5330.0 -3090.0 -6010.0 -5470.5 511.0 -5990.0 -3450.0 -2070.5 386.5 386.0 -1630.5 511.0 -7470.5 386.5 386.5 386.5 386.5 386.0 -6490.0 -3850.0 -6630.0 -4490.0 -7090.0 -2950.5 511.5 386.0 -4530.5 511.5 511.5 386.5 386.0 -2330.0 -1990.0 -2030.5 511.5 386.0 -5190.0 -5650.5 511.5 511.0 -6710.0 -4270.0 -4150.0 -6110.0 -6750.5 511.0 -5770.5 511.5 511.0 -1810.0 -7530.0 -7350.0 -3810.5 386.5 386.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 Y 386.5 511.5 511.0 -3230.0 -4570.5 386.5 511.5 511.5 386.0 -1610.0 -3690.5 386.5 511.0 -5150.0 -5130.0 -1870.0 -5450.5 386.0 -1970.0 -4410.0 -3670.5 511.5 386.5 386.0 -7250.0 -4050.0 -2750.5 386.0 -6190.0 -4650.0 -4030.5 511.0 -2790.0 -5310.5 386.5 511.5 511.5 386.5 511.0 -2810.5 511.0 -6950.5 511.0 -1790.5 386.5 511.5 386.0 -6330.5 511.0 -2830.0 -5090.5 511.5 511.5 386.0 -6770.0 -5350.5 511.5 511.5 386.0 -6470.5 511.0 -3150.0 -7510.0 -4890.5 511.5 386.0 -3610.0 -7390.0 -6730.0 -5050.0 -5550.5 386.5 511.0 -3790.5 386.0 -4610.5 511.0 -1730.

5 1230 G240 -8190.0 386.5 1307 G86 -9730.0 511.0 511.5 1222 G256 -8030.0 386.5 1311 G78 -9810.0 511.0 10613.5 -10210.5 -10410.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 No.5 1318 G64 -9950.0 511.0 511.0 511.0 511.5 1275 G150 -9090.0 511.5 -10650.0 386.5 -10270.0 386.0 386.5 1305 G90 -9690.5 1248 G204 -8550.5 1247 G206 -8530.0 511.0 386.5 1256 G188 -8710.0 386. 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 Name G58 G56 G54 G52 G50 G48 G46 G44 G42 G40 G38 G36 G34 G32 G30 G28 G26 G24 G22 G20 G18 G16 G14 G12 G10 G8 G6 G4 G2 VGLDMY4 DUMMYR9 DUMMYR10 TESTO37 TESTO38 X Y 1201 G298 -7610. reproduced.5 -10490.0 386.5 -10350.5 -10310.5 1289 G122 -9370.0 511.0 386.0 511.0 511.5 1261 G178 -8810.5 1262 G176 -8830.5 1312 G76 -9830.0 386.0 511.0 511.5 1277 G146 -9130.0 386.5 -10230.0 386.5 1294 G112 -9470.5 1303 G94 -9650.5 1252 G196 -8630.0 386.0 386.5 1314 G72 -9870.5 1227 G246 -8130.5 -10170.0 386.5 -10250.0 511.0 386.5 1213 G274 -7850.5 1319 G62 -9970.0 386.5 1293 G114 -9450.0 511.0 -468.0 386.0 386.5 -10430.0 386.5 1238 G224 -8350.5 -10150.0 386.0 386.0 511.0 511.0 511.0 386.0 511.5 1276 G148 -9110.0 511.5 1304 G92 -9670.5 1231 G238 -8210.5 1301 G98 -9610.5 1297 G106 -9530.0 386.5 -10510.5 -10670.5 1299 G102 -9570.5 1220 G260 -7990.0 511.0 386.0 386.0 511.0 511.5 1278 G144 -9150.5 1310 G80 -9790.5 1290 G120 -9390.5 -10590.0 511.5 1269 G162 -8970.5 1229 G242 -8170.0 386.0 386.0 511.5 1253 G194 -8650.0 386.0 386.5 1265 G170 -8890.5 1245 G210 -8490.0 511.0 511.5 1205 G290 -7690.0 386.0 511.5 1235 G230 -8290.0 511.0 386.0 386.5 -10190.0 386.5 1226 G248 -8110.5 -10610.5 -10390.0 386.0 511.0 386.5 1270 G160 -8990.0 511.0 386.0 511.0 511.0 386.0 386.5 1295 G110 -9490.0 511.5 1316 G68 -9910.0 511.5 1202 G296 -7630.5 1306 G88 -9710.0 511.5 1243 G214 -8450.0 511.0 386.0 511. or disclosed in whole or in part without prior written permission of ILI Technology Corp.0 386.5 -10130.0 511.5 1291 G118 -9410.5 -10450.0 386.0 511.0 511.5 1292 G116 -9430.0 511.0 511.0 511.5 1225 G250 -8090.5 1250 G200 -8590.0 386.5 1215 G270 -7890.0 511.5 1315 G70 -9890.0 386.0 386.5 1287 G126 -9330.0 386.5 1281 G138 -9210.5 -10290.0 386.0 386.0 386.0 386.0 511.5 1296 G108 -9510.5 1236 G228 -8310.5 1317 G66 -9930.0 511.0 386. Name X Y No.5 1244 G212 -8470.0 386.0 386.5 -10070. Page 20 of 115 Version: 0.0 -468.5 -10570.0 511.5 1251 G198 -8610.5 -10550.0 386.0 386.0 511.5 1284 G132 -9270.0 511.0 511.5 1255 G190 -8690.0 386.5 1207 G286 -7730.0 386.5 1249 G202 -8570.5 1264 G172 -8870.0 386.5 1232 G236 -8230.5 1285 G130 -9290.5 1302 G96 -9630.0 511.0 386.5 1320 G60 -9990.5 1279 G142 -9170.0 386.5 1228 G244 -8150.0 386.0 511.0 511.5 1263 G174 -8850.0 511.0 386.5 1216 G268 -7910.41 .0 386.5 1219 G262 -7970.5 1298 G104 -9550.5 1217 G266 -7930.5 1271 G158 -9010.5 1218 G264 -7950.5 1274 G152 -9070. Name X Y No.5 1233 G234 -8250.0 386.5 1309 G82 -9770.0 511.5 1280 G140 -9190.0 386.5 1266 G168 -8910.5 -10330.0 511.0 511.5 1210 G280 -7790.5 1240 G220 -8390.5 1211 G278 -7810.5 1221 G258 -8010.5 -10370.5 1241 G218 -8410.5 -10530.5 1242 G216 -8430.5 -10090.5 1212 G276 -7830.5 -10030.5 1300 G100 -9590.5 1308 G84 -9750.5 -10470.5 1283 G134 -9250.0 511.0 386.5 1223 G254 -8050.0 511.5 1214 G272 -7870.0 386.0 386.5 1208 G284 -7750.0 386.0 511.5 1203 G294 -7650.0 The information contained herein is the exclusive property of ILI Technology Corp.0 511.0 511.5 1282 G136 -9230.5 1206 G288 -7710.0 386.5 1313 G74 -9850.0 386.0 511.5 -10010.5 1273 G154 -9050.0 511.0 386.0 386.5 -10630.5 1288 G124 -9350.5 1246 G208 -8510.5 1254 G192 -8670.5 1267 G166 -8930.5 -10110.0 511.0 511.0 386.0 511.5 1286 G128 -9310.5 1209 G282 -7770.5 1268 G164 -8950.5 1257 G186 -8730.0 386.5 1239 G222 -8370.5 1204 G292 -7670.5 Alignment mark 1-a 1-b X Y -10613.5 1260 G180 -8790.0 386.5 1237 G226 -8330. and shall not be distributed.0 511.5 1234 G232 -8270.0 511.0 511.0 386.0 511.0 511.5 1259 G182 -8770.0 511.5 1272 G156 -9030.5 1258 G184 -8750.0 511.5 -10050.5 1224 G252 -8070.0 511.

41 80 . 299 ~ 1354) 100 Unit: um 25 100 50 20 50 Pad Pump Pad Pump 70 I/O Pads (No. 1 ~ 298) The information contained herein is the exclusive property of ILI Technology Corp. reproduced. Page 21 of 115 Version: 0. and shall not be distributed.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 20 21 S1 ~ S720 G1 ~ G320 DUMMY DUMMYR TESTO VGLDMY (No. or disclosed in whole or in part without prior written permission of ILI Technology Corp.

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color

ILI9320

6. Block Description
MPU System Interface
ILI9320 supports three system high-speed interfaces: i80-system high-speed interfaces to 8-, 9-, 16-, 18-bit parallel ports and serial peripheral interface (SPI). The interface mode is selected by setting the IM[3:0] pins. ILI9320 has a 16-bit index register (IR), an 18-bit write-data register (WDR), and an 18-bit read-data register (RDR). The IR is the register to store index information from control registers and the internal GRAM. The WDR is the register to temporarily store data to be written to control registers and the internal GRAM. The RDR is the register to temporarily store data read from the GRAM. Data from the MPU to be written to the internal GRAM are first written to the WDR and then automatically written to the internal GRAM in internal operation. Data are read via the RDR from the internal GRAM. Therefore, invalid data are read out to the data bus when the ILI9320 read the first data from the internal GRAM. Valid data are read out after the ILI9320 performs the second read operation. Registers are written consecutively as the register execution time except starting oscillator takes 0 clock cycle. Registers selection by system interface (8-/9-/16-/18-bit bus width) Function Write an index to IR register Read an internal status Write to control registers or the internal GRAM by WDR register. Read from the internal GRAM by RDR register. Registers selection by the SPI system interface Function Write an index to IR register Read an internal status Write to control registers or the internal GRAM by WDR register. Read from the internal GRAM by RDR register. I80 nWR nRD 0 1 1 0 0 1 1 0

RS 0 0 1 1

R/W 0 1 0 1

RS 0 0 1 1

Parallel RGB Interface
ILI9320 supports the RGB interface and the VSYNC interface as the external interface for displaying a moving picture. When the RGB interface is selected, display operations are synchronized with externally supplied signals, VSYNC, HSYNC, and DOTCLK. In RGB interface mode, data (DB17-0) are written in synchronization with these signals according to the polarity of enable signal (ENABLE) to prevent flicker on display while updating display data. In VSYNC interface mode, the display operation is synchronized with the internal clock except frame synchronization, where the operation is synchronized with the VSYNC signal. Display data are written to the internal GRAM via the system interface. In this case, there are constraints in speed and method in writing data to the internal RAM. For details, see the “External Display Interface” section. The ILI9320 allows for switching between the external display interface and the system interface by instruction so that the optimum interface is The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
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ILI9320

selected for the kind of picture to be displayed on the screen (still and/or moving picture(s)). The RGB interface, by writing all display data to the internal RAM, allows for transferring data only when updating the frames of a moving picture, contributing to low power requirement for moving picture display.

Bit Operation
The ILI9320 supports a write data mask function for selectively writing data to the internal RAM in units of bits and a logical/compare operation to write data to the GRAM only when a condition is met as a result of comparing the data and the compare register bits. For details, see “Graphics Operation Functions”.

Address Counter (AC)
The address counter (AC) gives an address to the internal GRAM. When the index of the register for setting a RAM address in the AC is written to the IR, the address information is sent from the IR to the AC. As writing data to the internal GRAM, the address in the AC is automatically updated plus or minus 1. The window address function enables writing data only in the rectangular area arbitrarily set by users on the GRAM.

Graphics RAM (GRAM)
GRAM is graphics RAM storing bit-pattern data of 172,820 (240 x 320x 18/8) bytes with 18 bits per pixel.

Grayscale Voltage Generating Circuit
The grayscale voltage generating circuit generates a liquid crystal drive voltage according to grayscale data set in the γ-correction register to display in 262,144 colors. For details, see the “γ-Correction Register” section.

Timing Controller
The timing generator generates a timing signal for operation of internal circuits such as the internal GRAM. The timing for the display operation such as RAM read operation and the timing for the internal operation such as access from the MPU are generated in the way not to interfere each other.

Oscillator (OSC)
ILI9320 generates RC oscillation with an external oscillation resistor placed between the OSC1 and OSC2 pins. The oscillation frequency is changed according to the value of an external resistor. Adjust the oscillation frequency in accordance to the operating voltage or the frame frequency. An operating clock can be input externally. During standby mode, RC oscillation is halted to reduce power consumption. For details, see “Oscillator”.

LCD Driver Circuit
The LCD driver circuit of ILI9320 consists of a 720-output source driver (S1 ~ S720) and a 320-output gate driver (G1~G320). Display pattern data are latched when the 720th bit data are input. The latched data control The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
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ILI9320

the source driver and generate a drive waveform. The gate driver for scanning gate lines outputs either VGH or VGL level. The shift direction of 720 source outputs from the source driver is set with the SS bit and the shift direction of gate outputs from the gate driver is set with the GS bit. The scan mode by the gate driver is set with the SM bit. These bits allow setting an appropriate scan method for an LCD module.

LCD Driver Power Supply Circuit
The LCD drive power supply circuit generates the voltage levels VREG1OUT, VGH, VGL and Vcom for driving an LCD.

The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 24 of 115 Version: 0.41

DOTCLK and data bus DB[17:0]. there are some constraints of speed and method to write data to the internal RAM. the internal display timing is synchronized with the frame synchronization signal (VSYNC). When switching from one mode to another. refer to the sequences mentioned in the sections of RGB and VSYNC interfaces. In this case. Note 2) The RGB-I/F and the VSYNC-I/F are not available simultaneously. System Interface 7. the display data is written into the GRAM through the control signals of ENABLE. HSYNC. ILI9320 operates in one of the following 4 modes. or disclosed in whole or in part without prior written permission of ILI Technology Corp.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 7. and the RGB Input Interface for displaying a moving picture. Interface Specifications ILI9320 has the system interface to read/write the control registers and display graphics memory (GRAM). The information contained herein is the exclusive property of ILI Technology Corp. The VSYNC interface mode enables to display the moving picture display through the system interface. In RGB interface mode. All display data are stored in the GRAM to reduce the data transfer efforts and only the updating data is necessary to be transferred. The display mode can be switched by the control register. reproduced. Operation Mode Internal operating clock only (Displaying still pictures) RGB interface (1) (Displaying moving pictures) RGB interface (2) (Rewriting still pictures while displaying moving pictures) VSYNC interface (Displaying moving pictures) RAM Access Setting (RM) System interface (RM = 0) RGB interface (RM = 1) System interface (RM = 0) System interface (RM = 0) Display Operation Mode (DM[1:0]) Internal operating clock (DM[1:0] = 00) RGB interface (DM[1:0] = 01) RGB interface (DM[1:0] = 01) VSYNC interface (DM[1:0] = 01) Note 1) Registers are set only via the system interface.41 . VSYNC. User can select an optimum interface to display the moving or still picture with efficient data transfer. ILI9320 also has the RGB interface and VSYNC interface to transfer the display data without flicker the moving picture on the screen. and shall not be distributed. In VSYNC interface mode. Page 25 of 115 Version: 0. User can only update a sub-range of GRAM by using the window address function.1.

SDO (DB[1:0]) DB[17:0] DB[17:9] The information contained herein is the exclusive property of ILI Technology Corp. Input Interfaces The following are the system interfaces available with the ILI9320. reproduced. Page 26 of 115 Version: 0. The system interface is used for setting registers and GRAM access. IM3 0 0 0 0 0 0 1 1 1 1 1 IM2 0 0 0 0 1 1 0 0 0 0 1 IM1 0 0 1 1 0 1 0 0 1 1 * IM0/ID 0 1 0 1 ID * 0 1 0 1 * Interface Mode Setting invalid Setting invalid i80-system 16-bit interface i80-system 8-bit interface Serial Peripheral Interface (SPI) Setting invalid Setting invalid Setting invalid i80-system18-bit interface i80-system 9-bit interface Setting invalid DB Pin DB[17:10]. The interface is selected by setting the IM[3:0] pins.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 System Interface 18/16/6 nCS RS nWR nRD DB[17:0] System ILI9320 ENABLE VSYNC HSYNC DOTCLK RGB Interface Figure1 System Interface and RGB Interface connection 7. or disclosed in whole or in part without prior written permission of ILI Technology Corp. DB[8:1] DB[17:10] SDI.2. and shall not be distributed.41 .

or disclosed in whole or in part without prior written permission of ILI Technology Corp. System nCS A2 nWR nRD D[31:0] 18 nCS RS nWR nRD DB[17:0] 18-bit System Interface (262K colors) TRI=0. reproduced.1. Page 27 of 115 Version: 0. i80/18-bit System Interface The i80/18-bit system interface is selected by setting the IM[3:0] as “1010” levels.2.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 7.41 . DFM[1:0]=00 Input Data DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB 0 Write Data Register WD 17 WD 16 WD 15 WD 14 WD 13 WD 12 WD 11 WD 10 WD 9 WD 8 WD 7 WD 6 WD 5 WD 4 WD 3 WD 2 WD 1 WD 0 GRAM Data & RGB Mapping R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 Figure2 18-bit System Interface Data Format The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed.

536 colors 0 * DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 1st Transfer DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 80-system 16-bit interface (2 transfers/pixel) 262.41 . or disclosed in whole or in part without prior written permission of ILI Technology Corp. System nCS A1 nWR nRD D[15:0] 16 nCS RS nWR nRD DB[17:10]. 2nd transfer: 16 bits or 1st transfer: 16 bits. and shall not be distributed. The 262K or 65K color can be display through the 16-bit MPU interface. When the 262K color is displayed.144 colors 1 0 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 1st Transfer DB 10 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 2nd Transfer DB DB 17 16 R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 80-system 16-bit interface (2 transfers/pixel) 262.2. i80/16-bit System Interface The i80/16-bit system interface is selected by setting the IM[3:0] as “0010” levels.144 colors 1 1 1st Transfer DB DB 2 1 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 2nd Transfer DB 10 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 Figure3 16-bit System Interface Data Format The information contained herein is the exclusive property of ILI Technology Corp. Page 28 of 115 Version: 0. DB[8:1] TRI DFM 16-bit MPU System Interface Data Format system 16-bit interface (1 transfers/pixel) 65.2. two transfers (1st transfer: 2 bits. 2nd transfer: 2 bits) are necessary for the 16-bit CPU interface. reproduced.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 7.

the data is divided into upper byte (8 bits and LSB is not used) lower byte and the upper byte is transferred first. and the upper byte is transferred first. The information contained herein is the exclusive property of ILI Technology Corp. and the upper byte is transferred first. i80/8-bit System Interface The i80/8-bit system interface is selected by setting the IM[3:0] as “0011” and the DB17~DB10 pins are used to transfer the data.2. or disclosed in whole or in part without prior written permission of ILI Technology Corp. the data is divided into upper byte (8 bits and LSB is not used) lower byte and the upper byte is transferred first.3.4. The unused DB[8:0] pins must be tied to either Vcc or AGND. The display data is also divided in upper byte (8 bits) and lower byte. The unused DB[9:0] pins must be tied to either Vcc or AGND. The written data is expanded into 18 bits internally (see the figure below) and then written into GRAM. Page 29 of 115 Version: 0. reproduced. DFM[1:0]=00 1st Transfer (Upper bits) 2nd Transfer (Lower bits) Input Data DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 Write Data Register WD 17 WD 16 WD 15 WD 14 WD 13 WD 12 WD 11 WD 10 WD 9 WD 8 WD 7 WD 6 WD 5 WD 4 WD 3 WD 2 WD 1 WD 0 GRAM Data & RGB Mapping R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 Figure4 9-bit System Interface Data Format 7. When writing the 16-bit register. The display data is also divided in upper byte (9 bits) and lower byte. When writing the 16-bit register. System nCS A1 nWR nRD D[8:0] 9 nCS RS nWR nRD DB[17:9] 9-bit System Interface (262K colors) TRI=0.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 7. and shall not be distributed.2.41 . i80/9-bit System Interface The i80/9-bit system interface is selected by setting the IM[3:0] as “1011” and the DB17~DB9 pins are used to transfer the data.

reproduced. This synchronization function can effectively prevent display error if the upper/lower counters are periodically reset. and shall not be distributed.41 .a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color TRI DFM 8-bit MPU System Interface Data Format system 8-bit interface (2 transfers/pixel) 65.536 colors 0 * DB 17 DB 16 DB 15 ILI9320 1st Transfer DB 14 DB 13 DB 12 DB 11 DB 10 DB 17 DB 16 DB 15 2nd Transfer DB 14 DB 13 DB 12 DB 11 DB 10 R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 80-system 8-bit interface (3 transfers/pixel) 262.3. Serial Peripheral Interface (SPI) The Serial Peripheral Interface (SPI) is selected by setting the IM[3:0] pins as “010x” level. RS RD nWR Upper/ Lower DB[17:9] “00”h “00”h “00”h “00”h Upper Lower 8-/9-bit transfer synchronization Figure6 Data Transfer Synchronization in 8/9-bit System Interface 7. The chip select pin The information contained herein is the exclusive property of ILI Technology Corp.144 colors 1 1 DB 17 DB 16 1st Transfer DB 15 DB 14 DB 13 DB 12 DB 17 DB 16 2nd Transfer DB 15 DB 14 DB 13 DB 12 DB 17 DB 16 3rd Transfer DB 15 DB 14 DB 13 DB 12 R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 Figure5 8-bit System Interface Data Format Data transfer synchronization in 8/9-bit bus interface mode ILI9320 supports a data transfer synchronization function to reset upper and lower counters which count the transfers numbers of upper and lower byte in 8/9-bit interface mode. or disclosed in whole or in part without prior written permission of ILI Technology Corp. If a mismatch arises in the numbers of transfers between the upper and lower byte counters due to noise and so on. the “00”h register is written 4 times consecutively to reset the upper and lower counters so that data transfer will restart with a transfer of upper byte. Page 30 of 115 Version: 0.144 colors 1 0 1st Transfer DB DB 11 10 DB 17 DB 16 DB 15 2nd Transfer DB 14 DB 13 DB 12 DB 11 DB 10 DB 17 DB 16 DB 15 3rd Transfer DB 14 DB 13 DB 12 DB 11 DB 10 R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 80-system 8-bit interface (3 transfers/pixel) 262.

The seventh bit of start byte is RS bit.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 (nCS). The ID pin sets the least significant bit of the identification code. Data is written when the R/W bit is “0” and read back when the R/W bit is “1”.41 . The SPI interface operation enables from the falling edge of nCS and ends of data transfer on the rising edge of nCS. When the start byte is matched. or disclosed in whole or in part without prior written permission of ILI Technology Corp. After receiving the start byte. Start Byte Format Transferred bits Start byte format S Transfer start 1 0 Note: ID bit is selected by setting the IM0/ID pin. When RS = “0”. The start byte is transferred to start the SPI interface and the read/write operation and RS information are also included in the start byte. the serial transfer clock pin (SCL). the subsequent data is received by ILI9320. All the registers of the ILI9320 are 16-bit format and receive the first and the second byte datat as the upper and the lower eight bits of the 16-bit register respectively. RS and R/W Bit Function RS 0 0 1 1 R/W 0 1 0 1 Function Set an index register Read a status Write a register or GRAM data Read a register or GRAM data 2 1 3 4 Device ID code 1 1 5 0 6 ID 7 RS 1/0 8 R/W 1/0 The information contained herein is the exclusive property of ILI Technology Corp. The DB[17:0] pins. either register write operation or RAM read/write operation is executed. either index write operation or status read operation is executed. 5 bytes dummy read is necessary and the valid data starts from 6th byte of read back data. ILI9320 starts to transfer or receive the data in unit of byte and the data transfer starts from the MSB bit. When RS = “1”. which are not used. must be tied to either IOVcc or DGND. Page 31 of 115 Version: 0. reproduced. the serial data input pin (SDI) and the serial data output pin (SDO) are used in SPI mode. The eighth bit of the start byte is used to select either read or write operation (R/W bit). In SPI mode. and shall not be distributed.

or disclosed in whole or in part without prior written permission of ILI Technology Corp. reproduced. Page 32 of 115 Version: 0. and shall not be distributed.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 Serial Peripheral Interface for register access D 15 D 14 D 13 D 12 D 11 D 10 D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 SPI Input Data Register Data IB 15 IB 14 IB 13 IB 12 IB 11 IB 10 IB 9 IB 8 IB 7 IB 6 IB 5 IB 4 IB 3 IB 2 IB 1 IB 0 Serial Peripheral Interface 65K colors Input Data D 15 D 14 D 13 D 12 D 11 D 10 D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Write Data Register WD 17 WD 16 WD 15 WD 14 WD 13 WD 12 WD 11 WD 10 WD 9 WD 8 WD 7 WD 6 WD 5 WD 4 WD 3 WD 2 WD 1 WD 0 GRAM Data RGB mapping R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 Figure 7 Data Format of SPI Interface The information contained herein is the exclusive property of ILI Technology Corp.41 .

reproduced. registers read and GRAM read (b) Consecutive data transmission through SPI Start nCS (Input) 1 SCL (Input) SDI (Input) Start Byte Register 1 upper eight bits Register 1 lower eight bits Register 2 upper eight bits Register 1 execution time Register 2 lower eight bits 8 9 16 17 24 25 32 Note: The first byte after the start byte is always the upper eight bits . Figure8 Data transmission through serial peripheral interface (SPI) The information contained herein is the exclusive property of ILI Technology Corp.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 End (a) Basic data transmission through SPI Start nCS (Input) 1 SCL (Input) SDI (Input) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 0 1 1 1 0 ID RS RW D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Start Byte SDO (Output) Index register. and shall not be distributed.41 . (d) Status/registers read transmission Start nCS (Input) 1 SCL (Input) SDI (Input) SDO (Output) Start Byte Register 1 upper eight bits Register 1 lower eight bits 8 9 16 17 24 End Note: One byte of invalid dummy data read after the start byte . Page 33 of 115 Version: 0. or disclosed in whole or in part without prior written permission of ILI Technology Corp. (c) GRAM data read transmission Start nCS (Input) End SCL (Input) SDI (Input) SDO (Output) Start Byte RS=1. registers setting. and GRAM write D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Status. RW=1 Dummy read 1 Dummy read 2 Dummy read 3 Dummy read 4 Dummy read 5 RAM read upper byte RAM read lower byte Note: Five bytes of invalid dummy data read after the start byte .

Figure9 Data transmission through serial peripheral interface (SPI).41 .a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 End (e) Basic data transmission through SPI Start nCS (Input) 1 SCL (Input) SDI (Input) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 0 1 1 1 0 ID RS RW D23 D22 D21 D120 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 GRAM data write D23 D22 D21 D120 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 GRAM data read D8 D7 D6 D5 D4 D3 D2 D1 D0 Start Byte SDO (Output) D8 D7 D6 D5 D4 D3 D2 D1 D0 (f) GRAM data write transmission Start nCS (Input) End SCL (Input) SDI (Input) SDO (Output) Note: Five bytes of invalid dummy data read after the start byte. and shall not be distributed. TRI=”1” and DFM=”10”) The information contained herein is the exclusive property of ILI Technology Corp. or disclosed in whole or in part without prior written permission of ILI Technology Corp. RAM data transfer in SPI mode when TRI=1 and DFM[1:0]=10. reproduced. RW=1 Dummy read 1 Dummy read 2 Dummy read 3 Dummy read 4 Dummy read 5 RAM read 1st byte RAM read 2nd byte RAM read 3rd byte Note: Five bytes of invalid dummy data read after the start byte. Start Byte RAM data 1 1st transfer RAM data 1 2nd transfer RAM data 1 3rd transfer RAM data 2 1st transfer RAM data 2 2nd transfer RAM data 2 3rd transfer GRAM Data (1) execution time GRAM Data (2) execution time (g) GRAM data read transmission Start nCS (Input) End SCL (Input) SDI (Input) SDO (Output) Start Byte RS=1. Page 34 of 115 Version: 0.

or disclosed in whole or in part without prior written permission of ILI Technology Corp. When the VSYNC interface is selected to display a moving picture. the display operation is synchronized with the internal clock and VSYNC input and the frame rate is determined by the pulse rate of VSYNC signal. VSYNC Interface ILI9320 supports the VSYNC interface in synchronization with the frame-synchronizing signal VSYNC to display the moving picture with the i80 system interface. reproduced. Page 35 of 115 Version: 0.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 7.4. VSYNC MPU nCS RS nWR DB[17:0] Figure10 Data transmission through VSYNC interface) In the VSYNC mode.41 . and shall not be distributed. All display data are stored in GRAM to minimize total data transfer required for moving picture display. VSYNC Write data to RAM through system interface Display operation synchronized with internal clocks Rewriting screen data Rewriting screen data Figure11 Moving picture data transmission through VSYNC interface The information contained herein is the exclusive property of ILI Technology Corp. the minimum GRAM update speed is limited and the VSYNC interface is enabled by setting DM[1:0] = “10” and RM = “0”.

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color

ILI9320

VSYNC
Back porch (14 lines)

RAM Write Display operation

Display (320 lines)

Front porch (2 lines) Black period

Figure12 Operation through VSYNC Interface The VSYNC interface has the minimum speed limitation of writing data to the internal GRAM via the system interface, which are calculated from the following formula. Internal clock frequency (fosc.) [Hz] = FrameFrequency x (DisplayLine (NL) + FrontPorch (FP) + BackPorch (BP)) x ClockCyclePerLines (RTN) x FrequencyFluctuation.
320 x DisplayLines (NL) [(BackPorch(BP)+DisplayLines(NL) - margins] x 16 (clocks) x 1/fosc

Minimum RAM write speed (HZ)

Note: When the RAM write operation does not start from the falling edge of VSYNC, the time from the falling edge of VSYNC until the start of RAM write operation must also be taken into account. An example of minimum GRAM writing speed and internal clock frequency in VSYNC interface mode is as below. [Example] Display size: 240 RGB × 320 lines Lines: 320 lines (NL = 1000111) Back porch: 14 lines (BP = 1110) Front porch: 2 lines (FP = 0010) Frame frequency: 60 Hz Frequency fluctuation: 10% Internal oscillator clock (fosc.) [Hz] = 60 x [320+ 2 + 14] x 16 clocks x (1.1/0.9) ≒ 394KHz The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 36 of 115 Version: 0.41

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color

ILI9320

When calculate the internal clock frequency, the oscillator variation is needed to be taken into consideration. In the above example, the calculated internal clock frequency with ±10% margin variation is considered and ensures to complete the display operation within one VSYNC cycle. The causes of frequency variation come from fabrication process of LSI, room temperature, external resistors and VCI voltage variation. Minimum speed for RAM writing [Hz] > 240 x 320 x 394K / [ (14 + 320 – 2)lines x 16clocks] ≒ 5.7 MHz

The above theoretical value is calculated based on the premise that the ILI9320 starts to write data into the internal GRAM on the falling edge of VSYNC. There must at least be a margin of 2 lines between the physical display line and the GRAM line address where data writing operation is performed. The GRAM write speed of 5.7MHz or more will guarantee the completion of GRAM write operation before the ILI9320 starts to display the GRAM data on the screen and enable to rewrite the entire screen without flicker.

Notes in using the VSYNC interface 1. The minimum GRAM write speed must be satisfied and the frequency variation must be taken into consideration. 2. The display frame rate is determined by the VSYNC signal and the period of VSYNC must be longer than the scan period of an entire display. 3. When switching from the internal clock operation mode (DM[1:0] = “00”) to the VSYNC interface mode or inversely, the switching starts from the next VSYNC cycle, i.e. after completing the display of the frame. 4. The partial display, vertical scroll, and interlaced scan functions are not available in VSYNC interface mode and set the AM bit to “0” to transfer display data.

The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 37 of 115 Version: 0.41

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color

ILI9320

System Interface Mode to VSYNC interface mode System Interface

VSYNC interface mode to System Interface Mode Opeartion through VSYNC interface
Set DM[1:0]=00, RM=0 for system interface mode

Set HWM=1, AM=0

Set GRAM Address

Display operation in synchronization with internal clocks
Wait more than 1 frame

Display operation in synchronization with VSYNC DM[1:0], RM become enable after completion of displaying 1 frame Display operation in synchronization with internal clocks

Set DM[1:0]=10, RM=0 for VSYNC interface mode

Set index register to R22h

DM[1:0], RM become enable after completion of displaying 1 frame

System Interface

Wait more than 1 frame

Note: input VSYNC for more than 1 frame period after setting the DM, RM register. Display operation in synchronization with VSYNC

Write data to GRAM through VSYNC interface

Opeartion through VSYNC interface

Figure13 Transition flow between VSYNC and internal clock operation modes

The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 38 of 115 Version: 0.41

5. Page 39 of 115 Version: 0.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 7. and shall not be distributed. reproduced. RIM1 0 0 1 1 RIM0 0 1 0 1 RGB Interface 18-bit RGB Interface 16-bit RGB Interface 6-bit RGB Interface Setting prohibited DB pins DB[17:0] DB[17:13]. or disclosed in whole or in part without prior written permission of ILI Technology Corp. RGB Input Interface The RGB Interface mode is available for ILI9320 and the interface is selected by setting the RIM[1:0] bits as following table.41 . DB[11:1] DB[17:12] 18-bit RGB Interface (262K colors) Input Data DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB 0 Write Data Register WD 17 WD 16 WD 15 WD 14 WD 13 WD 12 WD 11 WD 10 WD 9 WD 8 WD 7 WD 6 WD 5 WD 4 WD 3 WD 2 WD 1 WD 0 GRAM Data & RGB Mapping R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 16-bit RGB Interface (65K colors) Input Data DB 17 DB 16 DB 15 DB 14 DB 13 DB 11 DB 10 DB 9 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 Write Data Register WD 17 WD 16 WD 15 WD 14 WD 13 WD 11 WD 10 WD 9 WD 8 WD 7 WD 6 WD 5 WD 4 WD 3 WD 2 WD 1 GRAM Data & RGB Mapping R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 6-bit RGB Interface (262K colors) 1st Transfer 2nd Transfer 3rd Transfer Input Data DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 Write Data Register WD 17 WD 16 WD 15 WD 14 WD 13 WD 12 WD 11 WD 10 WD 9 WD 8 WD 7 WD 6 WD 5 WD 4 WD 3 WD 2 WD 1 WD 0 GRAM Data & RGB Mapping R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 Figure14 RGB Interface Data Format The information contained herein is the exclusive property of ILI Technology Corp.

HSYNC and DOTCLK with frequency that can meet the resolution requirement of panel. Note 2: Input DOTCLK throughout the operation.5. and DOTCLK signals.1.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 7. and shall not be distributed. Note 3: Supply the VSYNC. or disclosed in whole or in part without prior written permission of ILI Technology Corp. Figure15 GRAM Access Area by RGB Interface The information contained herein is the exclusive property of ILI Technology Corp. HSYNC. The RGB interface transfers the updated data to GRAM with the high-speed write function and the update area is defined by the window address function. Page 40 of 115 Version: 0. The back porch and front porch are used to set the RGB interface timing. RGB Interface The display operation via the RGB interface is synchronized with the VSYNC. reproduced. VSYNC RAM data display area Moving picture display area HSYNC DOTCLK ENABLE DB[17:0] Back porch period (BP[3:0]) Display period (NL[4:0] Front porch period (FP[3:0]) Note 1: Front porch period continues until the next input of VSYNC.41 .

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 7. RGB Interface Timing The timing chart of 18-/16-bit RGB interface mode is shown as follows.2. Figure16 Timing Chart of Signals in 18-/16-bit RGB Interface Mode The information contained herein is the exclusive property of ILI Technology Corp.5. and shall not be distributed. 1 frame Back porch VSYNC VLW >= 1H Front porch HSYNC DOTCLK ENABLE DB[17:0] HLW >= 3 DOTCLK HSYNC // 1H // DOTCLK DTST >= HLW ENABLE // DB[17:0] Valid data VLW: VSYNC low period HLW: HSYNC low period DTST: data transfer startup time Note 1: Use the high speed write mode (HWM=1) to write data through the RGB interface.41 . reproduced. Page 41 of 115 Version: 0. or disclosed in whole or in part without prior written permission of ILI Technology Corp.

Page 42 of 115 Version: 0. and shall not be distributed. HSYNC and ENABLE to 3 multiples of DOTCLKs. set the cycles of VSYNC. Note 2) In 6-bit RGB interface mode. each dot of one pixel (R.41 . Note 3) In 6-bit RGB interface mode. reproduced. 1 frame Back porch VSYNC VLW >= 1H Front porch ILI9320 HSYNC DOTCLK ENABLE DB[17:12] HLW >= 3 DOTCLK HSYNC // 1H // DOTCLK DTST >= HLW ENABLE // R G B R G B DB[17:12] Valid data VLW: VSYNC low period HLW: HSYNC low period DTST: data transfer startup time Note 1: Use the high speed write mode (HWM=1) to write data through the RGB interface. G and B) is transferred in synchronization with DOTCLKs.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color The timing chart of 6-bit RGB interface mode is shown as follows. // B R G B Figure17 Timing chart of signals in 6-bit RGB interface mode The information contained herein is the exclusive property of ILI Technology Corp. or disclosed in whole or in part without prior written permission of ILI Technology Corp.

• When display the moving picture in RGB interface mode.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 7.3. The following figure illustrates the operation of the ILI9320 when displaying a moving picture via the RGB interface and rewriting the still picture RAM area via the system interface. and shall not be distributed. When restart RAM access in RGB interface mode. Page 43 of 115 Version: 0. there is no guarantee that data are written to the internal GRAM. If RAM accesses via two interfaces conflicts.5. Still Picture Area Moving Picture Area Update a frame Update a frame VSYNC ENABLE DOTCLK DB[17:0] Update moving picture area Update moving picture area Set IR to R22h Set RM=0 Set AD[15:0] Set IR to R22h Update display data in other than the moving picture area Set AD[15:0] Set RM=1 Set IR to R22h Figure18 Example of update the still and moving picture The information contained herein is the exclusive property of ILI Technology Corp. • Only the moving picture area of GRAM is updated. • The window address function defined the update area of GRAM. such as icons. Moving Picture Mode ILI9320 has the RGB interface to display moving picture and incorporates GRAM to store display data. When write data to the internal GRAM by the system interface. which has following merits in displaying a moving picture. the DB[17:0] can be switched as system interface to update still picture area and registers. or disclosed in whole or in part without prior written permission of ILI Technology Corp. RAM access via a system interface in RGB-I/F mode ILI9320 allows GRAM access via the system interface in RGB interface mode. reproduced. wait one read/write cycle and then set RM = “1” and the index register to R22h to start accessing RAM via the RGB interface. set ENABLE to terminate the RGB interface and switch to the system interface to update the registers (RM = “0”) and the still picture of GRAM. In RGB interface mode.41 . data are written to the internal GRAM in synchronization with DOTCLK and ENABLE signals.

HSYNC.5. The display operation is synchronized with VSYNC. which requires consecutive data transfer in light of minimizing effects from failed data transfer and enabling the system to return to a normal state. HSYNC ENABLE DOTCLK DB[17:12] st nd rd 1st 2nd 3rd 1st 2nd 3rd 1 2 3 1st 2nd 3rd Transfer synchronization The information contained herein is the exclusive property of ILI Technology Corp. Page 44 of 115 Version: 0. 6-bit RGB Interface The 6-bit RGB interface is selected by setting the RIM[1:0] bits to “10”. This function is expedient for moving picture display. and shall not be distributed. second. reproduced. on the falling edge of VSYNC) to restart data transfer in the correct order from the next frame. or disclosed in whole or in part without prior written permission of ILI Technology Corp. Registers can be set by the system interface (i80/SPI).4.e.41 . Note that internal display operation is performed in units of pixels (RGB: taking 3 inputs of DOTCLK). the counter is reset to the state of first data transfer at the start of the frame (i. RGB interface with 6-bit data bus 1st Transfer Input Data DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 17 DB 16 2nd Transfer DB 15 DB 14 DB 13 DB 12 DB 17 DB 16 3rd Transfer DB 15 DB 14 DB 13 DB 12 RGB Assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 Data transfer synchronization in 6-bit RGB interface mode ILI9320 has data transfer counters to count the first. third data transfers in 6-bit RGB interface mode. The transfer counter is always reset to the state of first data transfer on the falling edge of VSYNC. If a mismatch arises in the number of each data transfer.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 7. and DOTCLK signals. Accordingly. Unused pins (DB[11:0]) must be fixed at either IOVcc or DGND level. the number of DOTCLK inputs in one frame period must be a multiple of 3 to complete data transfer correctly. Otherwise it will affect the display of that frame as well as the next frame. Display data are transferred to the internal GRAM in synchronization with the display operation via 6-bit RGB data bus (DB[17:12]) according to the data enable signal (ENABLE).

Display data are transferred to the internal RAM in synchronization with the display operation via 16-bit RGB data bus (DB17-13. Display data are transferred to the internal RAM in synchronization with the display operation via 18-bit RGB data bus (DB[17:0]) according to the data enable signal (ENABLE). HSYNC.5. 18-bit RGB Interface The 18-bit RGB interface is selected by setting the RIM[1:0] bits to “00”.41 . The following are the functions not available in RGB Input Interface mode. 16-bit RGB Interface (65K colors) Input Data DB 17 DB 16 DB 15 DB 14 DB 13 DB 11 DB 10 DB 9 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 Write Data Register WD 17 WD 16 WD 15 WD 14 WD 13 WD 11 WD 10 WD 9 WD 8 WD 7 WD 6 WD 5 WD 4 WD 3 WD 2 WD 1 GRAM Data & RGB Mapping R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 7. HSYNC.5. 3. RGB interface with 18-bit data bus Input Data DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB 0 RGB Assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 Notes in using the RGB Input Interface 1. Registers are set only via the system interface.6. and DOTCLK signals. Page 45 of 115 Version: 0. HSYNC. The periods set with the NO[1:0] bits (gate output non-overlap period). reproduced.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 7. and DOTCLK signals must be supplied throughout a display operation period. STD[1:0] bits (source output delay period) and EQ[1:0] bits (equalization period) are not based on the internal clock but based on DOTCLK in The information contained herein is the exclusive property of ILI Technology Corp. The display operation is synchronized with VSYNC. or disclosed in whole or in part without prior written permission of ILI Technology Corp. The display operation is synchronized with VSYNC. DB11-1) according to the data enable signal (ENABLE). VSYNC. and shall not be distributed. Registers are set only via the system interface. and DOTCLK signals. 16-bit RGB Interface The 16-bit RGB interface is selected by setting the RIM[1:0] bits to “01”.5. Function Partial display Scroll function Interlaced scan Graphics operation function RGB interface Not available Not available Not available Not available I80 system interface Available Available Available Available 2.

In other words. ILI9320 4. DB[17:0]) to contain DOTCLK inputs of a multiple of 3 to complete data transfer in units of pixels. Internal clock operation to RGB I/F Internal clock operation HWM = 1. the front porch period continues until the next VSYNC input is detected after drawing one frame. In RGB interface mode. or disclosed in whole or in part without prior written permission of ILI Technology Corp. a RAM address (AD[15:0]) is set in the address counter every frame on the falling edge of VSYNC. and shall not be distributed. follow the sequence below. When switching from the internal operation mode to the RGB Input Interface mode. 5. DOTCLK) before setting DM[1. In 6-bit RGB interface mode.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color RGB interface mode.0] and RM to the RGB interface mode Figure19 Internal clock operation/RGB interface mode switching The information contained herein is the exclusive property of ILI Technology Corp. HSYNC. HSYNC. In RGB interface mode. reproduced. In 6-bit RGB interface mode. DOTCLK) Write data through RGB I/F RGB Interface Operation Note: Input RGB Interface signals (VSYNC.41 . which consists of RGB dots. set the cycle of each signal in 6-bit interface mode (VSYNC. or the other way around. it takes 3 DOTCLK inputs to transfer one pixel. 7. are transferred in units of 3 DOTCLK. 6. Accordingly. 8. data of one pixel. each of RGB dots is transferred in synchronization with a DOTCLK input. HSYNC. DOTCLK) * DM[1:0] and RM become enable after completion of display 1 frame Set AD[15:0] Wait for more than 1 frame Set RGB Interface mode DM[1:0]=01 and RM=1 Note Internal clock operation Set IR to R22h (GRAM data write) Display operation in synchronization with internal clock Wait for more than 1 frame RGB Interface (Display operation in synchronization with VSYNC. Page 46 of 115 Version: 0. ENABLE. Be sure to complete data transfer in units of 3 DOTCLK inputs in 6-bit RGB interface mode. AM=0 Internal clock operation * SPI interface can be used to set the registers and data * DM[1:0] and RM become enable after completion of display 1 frame RGB I/F to Internal clock operation RGB Interface Operation Set Internal Clock Operation mode DM[1:0]=00 and RM=0 RGB Interface (Display operation in synchronization with VSYNC. HSYNC.

and shall not be distributed.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 Write data through RGB interface to write data through system interface RGB Interface operation Set DM[1:0]=01. or disclosed in whole or in part without prior written permission of ILI Technology Corp.0] Set DM[1:0]=01. reproduced. Page 47 of 115 Version: 0.41 . RM=1 with RGB interface mode Set IR to R22h (GRAM data write) RGB Interface operation Set IR to R22h (GRAM data write) Write data to GRAM through system interface System Interface operation Figure20 GRAM access between system interface and RGB interface The information contained herein is the exclusive property of ILI Technology Corp.0] Set AD[15. RM=0 with RGB interface mode HWM=1/0 Write data through system interface to write data through RGB interface System Interface operation Write data to GRAM through system interface HWM=1/0 Set AD[15.

6. and shall not be distributed. reproduced.41 . Figure21 Relationship between RGB I/F signals and LCD Driving Signals for Panel The information contained herein is the exclusive property of ILI Technology Corp.. Interface Timing The following are diagrams of interfacing timing with LCD panel control signals in internal operation and RGB interface modes. or disclosed in whole or in part without prior written permission of ILI Technology Corp.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 7. Page 48 of 115 Version: 0. // VSYNC // HSYNC DOTCLK // ENABLE // // DB[17:0] 1 2 3 4 5 318 319 320 1 2 3 4 FLM G1 G2 G320 // 1 2 3 4 5 318 319 320 S[720:1] VCOM ….

16-. Graphics data processing 6.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 8. Power management Control 5. All the functional blocks of ILI9320 starts to work after receiving the correct instruction from the external microprocessor by the 18-. As the following figure shows. Set internal GRAM address (AC) 7. reproduced. the display data (GRAM) is most often updated. and in order since the ILI9320 can update internal GRAM address automatically as it writes data to the internal GRAM and minimize data transfer by using the window address function. or disclosed in whole or in part without prior written permission of ILI Technology Corp. Specify the index of register (IR) 2. The registers of the ILI9320 are categorized into the following groups. the way of assigning data to the 16 register bits (D[15:0]) varies for each interface. Register Descriptions 8. Page 49 of 115 Version: 0. 1. Display control 4. The register selection signal (RS). Internal grayscale γ-correction (R30 ~ R39) Normally. Registers Access ILI9320 adopts 18-bit bus interface architecture for high-performance microprocessor. Read a status 3. 8-bit interface.1. and shall not be distributed. Transfer data to/from the internal GRAM (R22) 8. there are fewer loads on the program in the microprocessor. The index register (IR) stores the register address to which the instructions and display data will be written. Serial Peripheral Interface for register access D 15 D 14 D 13 D 12 D 11 D 10 D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 SPI Input Data Register Data D 15 D 14 D 13 D 12 D 11 D 10 D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Figure22 Register Setting with Serial Peripheral Interface (SPI) The information contained herein is the exclusive property of ILI Technology Corp. the read/write signals (nRD/nWR) and data bus D17-0 are used to read/write the instructions and data of ILI9320.41 . 9-. Send registers in accordance with the following data transfer format.

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 i80/M68 system 18-bit data bus interface Data Bus (DB[17:0]) DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB 0 Register Bit (D[15:0]) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 i80/M68 system 16-bit data bus interface Data Bus (DB[17:10]).41 . reproduced. Page 50 of 115 Version: 0. (DB[8:1]) Register Bit (D[15:0]) DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 i80/M68 system 9-bit data bus interface Data Bus (DB[17:9]) DB 17 DB 16 DB 15 1st Transfer DB DB DB 14 13 12 DB 11 DB 10 DB 9 DB 17 DB 16 DB 15 2nd Transfer DB DB DB 14 13 12 DB 11 DB 10 DB 9 Register Bit (D[15:0]) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 i80/M68 system 8-bit data bus interface/Serial peripheral interface (2/3 transmission) Data Bus (DB[17:10]) DB 17 DB 16 DB 15 1st Transfer DB DB 14 13 DB 12 DB 11 DB 10 DB 17 DB 16 DB 15 2nd Transfer DB DB 14 13 DB 12 DB 11 DB 10 Register Bit (D[15:0]) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Figure23 Register setting with i80 System Interface The information contained herein is the exclusive property of ILI Technology Corp. or disclosed in whole or in part without prior written permission of ILI Technology Corp. and shall not be distributed.

41 . and shall not be distributed. Page 51 of 115 Version: 0.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 i80 18-/16-bit System Bus Interface Timing (a) Write to register nCS RS nRD nWR DB[17:0] Write register “index” Write register “data” (b) Read from register nCS RS nRD nWR DB[17:0] Write register “index” Read register “data” i80 9-/8-bit System Bus Interface Timing (a) Write to register nCS RS nRD nWR DB[17:10] “00h” Write register “index” Write register “high byte data” Write register “low byte data” (b) Read from register nCS RS nRD nWR DB[17:10] “00h” Write register “index” Read register “high byte data” Read register “low byte data” Figure 24 Register Read/Write Timing of i80 System Interface The information contained herein is the exclusive property of ILI Technology Corp. reproduced. or disclosed in whole or in part without prior written permission of ILI Technology Corp.

2. or disclosed in whole or in part without prior written permission of ILI Technology Corp. reproduced.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 D10 L2 0 SM 0 DACKE 0 0 FP2 PTS2 0 0 0 0 BT2 DC12 0 VDV2 0 0 D9 L1 1 0 BC0 HWM RCV1 BASEE FP1 PTS1 0 0 0 0 BT1 DC11 0 VDV1 0 0 D8 L0 0 SS EOR 0 RCV0 0 FP0 PTS0 0 RM FMP8 0 BT0 DC10 VCMR VDV0 0 AD16 D7 ID7 0 0 0 0 0 0 0 0 0 0 0 FMP7 0 APE 0 0 0 AD7 AD15 D6 ID6 0 0 0 0 0 0 0 0 0 0 0 FMP6 0 AP2 DC02 0 0 AD6 AD14 D5 ID5 0 1 0 0 I/D1 RCH1 GON 0 PTG1 0 DM1 FMP5 0 AP1 DC01 0 0 AD5 AD13 D4 ID4 0 0 0 0 I/D0 RCH0 DTE 0 PTG0 0 DM0 FMP4 VSPL AP0 DC00 PON 0 AD4 AD12 D3 ID3 0 0 0 0 AM 0 CL BP3 ISC3 FMARKOE 0 FMP3 HSPL 0 0 VRH3 0 AD3 AD11 D2 ID2 0 0 0 0 0 0 0 BP2 ISC2 FMI2 0 FMP2 0 DSTB VC2 VRH2 0 AD2 AD10 D1 ID1 0 1 0 0 0 RSZ1 D1 BP1 ISC1 FMI1 RIM1 FMP1 DPL SLP VC1 VRH1 0 AD1 AD9 D0 ID0 0 0 OSC 0 0 0 RSZ0 D0 BP0 ISC0 FMI0 RIM0 FMP0 EPL 0 VC0 VRH0 0 AD0 AD8 8. and shall not be distributed. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KP1[2] KP3[2] KP5[2] RP1[2] KN1[2] KN3[2] KN5[2] RN1[2] 0 0 KP1[1] KP3[1] KP5[1] RP1[1] KN1[1] KN3[1] KN5[1] RN1[1] 0 0 KP1[0] KP3[0] KP5[0] RP1[0] KN1[0] KN3[0] KN5[0] RN1[0] 0 EXT_R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCM4 0 0 0 0 VRP0[4] 0 0 0 0 VCM3 0 0 0 0 0 VRP0[3] 0 0 0 0 VCM2 0 KP0[2] KP2[2] KP4[2] RP0[2] KN0[2] KN2[2] KN4[2] RN0[2] VCM1 0 KP0[1] KP2[1] KP4[1] RP0[1] KN0[1] KN2[1] KN4[1] RN0[1] VCM0 0 KP0[0] KP2[0] KP4[0] RP0[0] KN0[0] KN2[0] KN4[0] RN0[0] 16M_EN Dither FR_SEL1 FR_SEL0 VRP1[4] VRP1[3] VRP1[2] VRP1[1] VRP1[0] VRP0[2] VRP0[1] VRP0[0] The information contained herein is the exclusive property of ILI Technology Corp. IR SR Registers Name Index Register Status Read R/W RS W R R W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D15 L7 1 0 0 TRI 0 0 0 0 0 0 0 0 0 0 0 0 0 D14 L6 0 0 0 DFM 0 0 0 0 0 0 0 0 0 0 0 0 0 D13 L5 0 0 0 0 0 PTDE1 0 0 0 ENC0 0 0 0 0 0 0 0 0 D12 L4 1 0 0 BGR 0 PTDE0 0 0 0 0 0 0 SAP 0 0 VDV4 0 0 D11 L3 0 0 0 0 0 0 FP3 0 0 0 0 0 BT3 0 0 VDV3 0 0 00h Driver Code Read 00h Start Oscillation 01h Driver Output Control 1 02h LCD Driving Control 03h Entry Mode 04h Resize Control 07h Display Control 1 08h Display Control 2 09h Display Control 3 0Ah Display Control 4 0Ch RGB Display Interface Control 1 0Dh Frame Maker Position 0Fh RGB Display Interface Control 2 10h Power Control 1 11h Power Control 2 12h Power Control 3 13h Power Control 4 20h Horizontal GRAM Address Set 21h Vertical GRAM Address Set 22h Write Data to GRAM 29h Power Control 7 2Bh Frame Rate and Color Control 30h Gamma Control 1 31h Gamma Control 2 32h Gamma Control 3 35h Gamma Control 4 36h Gamma Control 5 37h Gamma Control 6 38h Gamma Control 7 39h Gamma Control 8 3Ch Gamma Control 9 ENC2 ENC1 RAM write data (WD17-0) / read data (RD17-0) bits are transferred via different data bus lines according to the selected interfaces. Page 52 of 115 Version: 0.41 . Instruction Descriptions No.

Registers Name R/W RS W W W W W W W W W W W W W W W W W W W W 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D15 0 0 0 0 0 GS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D13 0 0 0 0 0 NL5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D12 0 0 0 0 NL4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D11 0 0 0 0 NL3 0 0 0 0 0 0 0 0 0 0 0 0 0 D10 0 0 0 0 NL2 0 0 0 0 0 0 0 0 0 NOWI2 0 0 0 ILI9320 D9 0 0 0 0 NL1 0 0 0 0 0 0 0 0 DIVI1 NOWI1 0 DIVE1 0 D8 0 0 VSA8 VEA8 NL0 0 VL8 D7 0 HSA7 HEA7 VSA7 VEA7 0 0 VL7 D6 0 HSA6 HEA6 VSA6 VEA6 0 0 VL6 D5 0 HSA5 HEA5 VSA5 VEA5 SCN5 0 VL5 D4 VRN0[4] HSA4 HEA4 VSA4 VEA4 SCN4 0 VL4 PTDP04 PTSA04 PTEA04 PTDP14 PTSA14 PTEA14 0 0 0 RTNE4 0 0 D3 VRN0[3] HSA3 HEA3 VSA3 VEA3 SCN3 0 VL3 PTDP03 PTSA03 PTEA03 PTDP13 PTSA13 PTEA13 RTNI3 0 0 RTNE3 0 0 D2 HSA2 HEA2 VSA2 VEA2 SCN2 NDL VL2 D1 HSA1 HEA1 VSA1 VEA1 SCN1 VLE VL1 D0 HSA0 HEA0 VSA0 VEA0 SCN0 REV VL0 VRN0[2] VRN0[1] VRN0[0] 3Dh Gamma Control 10 50h Horizontal Address Start Position 51h Horizontal Address End Position 52h Vertical Address Start Position 53h Vertical Address End Position 60h Driver Output Control 2 61h Base Image Display Control 6Ah Vertical Scroll Control 80h Partial Image 1 Display Position 81h Partial Image 1 Area (Start Line) 82h Partial Image 1 Area (End Line) 83h Partial Image 2 Display Position 84h Partial Image 2 Area (Start Line) 85h Partial Image 2 Area (End Line) 90h Panel Interface Control 1 92h Panel Interface Control 2 93h Panel Interface Control 3 95h Panel Interface Control 4 97h Panel Interface Control 5 98h Panel Interface Control 6 VRN1[4] VRN1[3] VRN1[2] VRN1[1] VRN1[0] PTDP08 PTDP07 PTDP06 PTDP05 PTSA08 PTSA07 PTSA06 PTSA05 PTEA08 PTEA07 PTEA06 PTEA05 PTDP18 PTDP17 PTDP16 PTDP15 PTSA18 PTSA17 PTSA16 PTSA15 PTEA18 PTEA17 PTEA16 PTEA15 DIVI00 NOWI0 0 DIVE0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RTNE5 0 0 PTDP02 PTDP01 PTDP00 PTSA02 PTSA01 PTSA00 PTEA02 PTEA01 PTEA00 PTDP12 PTDP11 PTDP10 PTSA12 PTSA11 PTSA10 PTEA12 PTEA11 PTEA10 RTNI2 0 MCPI2 RTNE2 0 MCPE2 RTNI1 0 MCPI1 RTNE1 0 MCPE1 RTNI0 0 MCPI0 RTNE0 0 MCPE0 NOWE3 NOWE2 NOWE1 NOWE0 The information contained herein is the exclusive property of ILI Technology Corp.41 .a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color No. reproduced. and shall not be distributed. or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 53 of 115 Version: 0.

When SS = 0. To assign R. The information contained herein is the exclusive property of ILI Technology Corp.2. L[7:0] Indicates the position of driving line which is driving the TFT panel currently. set SS = 1. G.4. or disclosed in whole or in part without prior written permission of ILI Technology Corp. Driver Output Control (R01h) R/W W RS 1 D15 0 D14 0 D13 0 D12 0 D11 0 D10 SM D9 0 D8 SS D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 SS: Select the shift direction of outputs from the source driver.1. 8. reproduced. In addition to the shift direction.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 D4 ID4 D3 ID3 D2 ID2 D1 ID1 D0 ID0 8.41 .3. Page 54 of 115 Version: 0.2. To assign R. SM: Sets the gate driver pin arrangement in combination with the GS bit (R60h) to select the optimal scan mode for the module. the shift direction of outputs is from S1 to S720 When SS = 1. 8. Wait at least 10ms to let the frequency of oscillator stable and then do the other function setting. B dots to the source driver pins. B dots to the source driver pins from S1 to S720.2. Index (IR) R/W W RS 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 ID7 D6 ID6 D5 ID5 The index register specifies the address of register (R00h ~ RFFh) or RAM which will be accessed. Start Oscillation (R00h) R/W W R RS 1 1 D15 1 D14 0 D13 0 D12 1 D11 0 D10 0 D9 1 D8 1 D7 0 D6 0 D5 1 D4 0 D3 0 D2 0 D1 0 D0 1 0 Set the OSC bit as ‘1’ to start the internal oscillator and as ‘0’ to stop the oscillator. set SS = 0. Status Read (RS) R/W R RS 0 D15 L7 D14 L6 D13 L5 D12 L4 D11 L3 D10 L2 D9 L1 D8 L0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 The SR bits represent the internal status of the ILI9320.2. The device code “9320”h is read out when read this register. 8. When changing SS or BGR bits. B dots to the source driver pins from S720 to S1.2. G. the settings for both SS and BGR bits are required to change the assignment of R. G. and shall not be distributed. the shift direction of outputs is from S720 to S1. RAM data must be rewritten.

…. G315. and shall not be distributed. G316. G2 G2 Even-number G320 to G2 G319 to G1 G319 1 1 G319. G317. G319. …. G4. or disclosed in whole or in part without prior written permission of ILI Technology Corp. …. G3. G4. G5. G5. G2. G318. reproduced. G316. G3. G319 G2. …. G318. G9. G315. G1 G319 to G1 Odd-number G1 to G319 G320 to G2 G317 G319 ILI9320 G1 TFT Panel G319 G2 Even-number G2 G318 G320 G1.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 SM GS G1 G3 Odd-number Scan Direction G2 G4 TFT Panel Even-number Gate Output Sequence 0 0 G1. G5. G317. G3. …. G320 1 0 G2 to G320 G320 ILI9320 Odd-number G1 TFT Panel G2 G320. G3. G78.G311 G313. G4. G2. G7. …. G318. G4. G319. G318.G312 G314.G316 G317. G6. G8. G8.41 . G10. G320 G1 to G319 Odd-number G2 to G320 G317 G319 ILI9320 G1 G3 TFT Panel G2 G4 Even-number G318 G320 0 1 G320. G6. Page 55 of 115 Version: 0. G6. G1 G320 ILI9320 The information contained herein is the exclusive property of ILI Technology Corp.

the address is updated in vertical writing direction.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 D4 0 8. the address is updated in horizontal writing direction. LCD Driving Wave Control (R02h) R/W W RS 1 D15 0 D14 0 D13 0 D12 0 D11 0 D10 1 D9 B/C D8 EOR D7 0 D6 0 D5 0 D3 0 D2 0 D1 0 D0 0 . Refer to the following figure for the details. Entry Mode (R03h) R/W W RS 1 D15 TRI D14 DFM D13 0 D12 BGR D11 0 D10 0 D9 HWM D8 0 D7 ORG D6 0 D5 I/D1 D4 I/D0 D3 AM D2 0 D1 0 D0 0 AM Control the GRAM update direction. specify the address to start write operation according to the GRAM address map within the window address area. I/D[1:0] = 00 Horizontal : decrement Vertical : decrement E I/D[1:0] = 01 Horizontal : increment Vertical : decrement E I/D[1:0] = 10 Horizontal : decrement Vertical : increment B I/D[1:0] = 11 Horizontal : increment Vertical : increment B AM = 0 Horizontal B B E E AM = 1 Vertical E E B B B B E E Figure25 GRAM Access Direction Setting ORG Moves the origin address according to the ID setting when a window address area is made.B/C 0 : Frame/Field inversion 1 : Line inversion EOR: EOR = 1 and B/C=1 to set the line inversion. When AM = “0”. 8. and shall not be distributed. ORG = “0”: The origin address is not moved.6. When AM = “1”. Page 56 of 115 Version: 0. I/D[1:0] Control the address counter (AC) to automatically increase or decrease by 1 when update one pixel display data. The information contained herein is the exclusive property of ILI Technology Corp. or disclosed in whole or in part without prior written permission of ILI Technology Corp. In this case. When a window area is set by registers R16h and R17h. only the addressed GRAM area is updated based on I/D[1:0] and AM bits setting.2.5.2. This function is enabled when writing data with the window address area using high-speed RAM write.41 . reproduced.

In RAM read operation.144 colors 1 0 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 1st Transfer DB 10 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 2nd Transfer DB DB 17 16 R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 80-system 16-bit interface (2 transfers/pixel) 262. or disclosed in whole or in part without prior written permission of ILI Technology Corp. BGR=”0”: Follow the RGB order to write the pixel data.536 colors 0 * DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 1st Transfer DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 80-system 16-bit interface (2 transfers/pixel) 262. See the following figures for details. 2. data are transferred to the internal RAM in 8-bit x 3 transfers mode via the 8-bit interface. BGR=”1”: Swap the RGB data to BGR in writing into GRAM. When ORG=1. ILI9320 Notes: 1. Page 57 of 115 Version: 0. only the origin address address”00000h” can be set in the RAM address set registers R20h. DFM Set the mode of transferring data to the internal RAM when TRI = “1”. make sure to set ORG=0. It is also possible to send data via the 16-bit interface or SPI in the transfer mode that realizes display in 262k colors in combination with DFM bits.41 .144 colors 1 1 1st Transfer DB DB 2 1 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 2nd Transfer DB 10 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 Figure26 16-bit MPU System Interface Data Format The information contained herein is the exclusive property of ILI Technology Corp. When not using these interface modes. TRI DFM 16-bit MPU System Interface Data Format system 16-bit interface (1 transfers/pixel) 65. reproduced. and R21h. BGR Swap the R and B order of written data. be sure to set TRI = “0”. TRI When TRI = “1”.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ORG = “1”: The original address “00000h” moves according to the I/D[1:0] setting. and shall not be distributed.

and shall not be distributed. By specifying the number of remainder pixels by RCH bits. RSZ[1:0] 00 01 10 11 RCH[1:0] 00 Resizing factor No resizing (x1) x 1/2 Setting prohibited x 1/4 Number of remainder Pixels in Horizontal Direction 0 pixel* The information contained herein is the exclusive property of ILI Technology Corp. Resizing Control Register (R04h) R/W W RS 1 D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 RCV1 D8 RCV0 D7 0 D6 0 D5 RCH1 D4 RCH0 D3 0 D2 0 D1 RSZ1 D0 RSZ0 RSZ[1:0] Sets the resizing factor. the data can be transferred without taking the reminder pixels into consideration.41 . the ILI9320 writes the data according to the resizing factor so that the original image is displayed in horizontal and vertical dimensions.144 colors 1 0 1st Transfer DB DB 11 10 DB 17 DB 16 DB 15 2nd Transfer DB 14 DB 13 DB 12 DB 11 DB 10 DB 17 DB 16 DB 15 3rd Transfer DB 14 DB 13 DB 12 DB 11 DB 10 R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 80-system 8-bit interface (3 transfers/pixel) 262. RCV[1:0] Sets the number of remainder pixels in vertical direction when resizing a picture.536 colors ILI9320 0 * DB 17 DB 16 DB 15 1st Transfer DB 14 DB 13 DB 12 DB 11 DB 10 DB 17 DB 16 DB 15 2nd Transfer DB 14 DB 13 DB 12 DB 11 DB 10 R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 80-system 8-bit interface (3 transfers/pixel) 262. When the RSZ bits are set for resizing. reproduced.2.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color TRI DFM 8-bit MPU System Interface Data Format system 8-bit interface (2 transfers/pixel) 65. RCH[1:0] Sets the number of remainder pixels in horizontal direction when resizing a picture.144 colors 1 1 DB 17 DB 16 1st Transfer DB 15 DB 14 DB 13 DB 12 DB 17 DB 16 2nd Transfer DB 15 DB 14 DB 13 DB 12 DB 17 DB 16 3rd Transfer DB 15 DB 14 DB 13 DB 12 R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 Figure27 8-bit MPU System Interface Data Format 8. See “Resizing function”. Make sure that RCH = 2’h0 when not using the resizing function (RSZ = 2’h0) or there are no remainder pixels. the data can be transferred without taking the reminder pixels into consideration. By specifying the number of remainder pixels by RCV bits. which are contracted according to the factor respectively. Make sure that RCV = 2’h0 when not using the resizing function (RSZ = 2’h0) or there are no remainder pixels. or disclosed in whole or in part without prior written permission of ILI Technology Corp.7. Page 58 of 115 Version: 0.

data write operation from the microcontroller is performed irrespective of the setting of D[1:0] bits. 4. VCOM Output GND GND Non-lit display Non-lit display Base image display ILI9320 internal operation Halt Operate Operate Operate Operate Note: 1. all source outputs becomes the GND level to reduce charging/discharging current. and D[1:0]=”00” to turn off the display panel. The non-lit display level from the source output pins is determined by instruction (PTS). When D1 = “0”. DTE setting. 3.144 8 GON and DTE Set the output level of gate driver G1 ~ G320 as follows The information contained herein is the exclusive property of ILI Technology Corp. the ILI9320 internal display operation is halted completely. i. The internal state of the ILI9320 in standby mode become the same as when D[1:0] = “00”. the 8-color display mode is selected.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color 01 10 11 RCV[1:0] 00 01 10 11 *1 pixel = 1RGB 1 pixel 2 pixel 3 pixel Number of remainder Pixels in Vertical Direction 0 pixel* 1 pixel 2 pixel 3 pixel ILI9320 8. When writing D1 = “0”. In combination with the GON. the ILI9320 continues internal display operation. and is turned off when writing D1 = “0”. When the display is turned off by setting D[1:0] = “00”.2. or disclosed in whole or in part without prior written permission of ILI Technology Corp.41 . Display Control 1 (R07h) R/W W RS 1 D15 0 D14 0 D13 PTDE1 D12 PTDE0 D11 0 D10 0 D9 BASEE D8 0 D7 0 D6 0 D5 GON D4 DTE D3 CL D2 0 D1 D1 D0 D0 D[1:0] Set D[1:0]=”11” to turn on the display panel. CL 0 1 Colors 262. This does not mean the D[1:0] setting is changed when setting the standby mode. the graphics display data is retained in the internal GRAM and the ILI9320 displays the data when writing D1 = “1”. and shall not be distributed. reproduced. 2. D1 0 0 1 1 1 D0 0 1 0 1 1 BASEE 0 1 0 0 1 Source.8. CL When CL = “1”. while no display is shown on the panel. When the display is turned off by setting D[1:0] = “01”. the D[1:0] setting controls display ON/OFF. A graphics display is turned on the panel when writing D1 = “1”. The D[1:0] setting is valid on both 1st and 2nd displays. Page 59 of 115 Version: 0. which is generated within the LCD while driving liquid crystal with AC voltage.e.

9.2.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color GON 0 0 1 1 BASEE DTE 0 1 0 1 G1 ~G320 Gate Output VGH VGH VGL Normal Display ILI9320 Base image display enable bit. The D[1:0] setting has higher priority over the BASEE setting. Only base image is displayed. or disclosed in whole or in part without prior written permission of ILI Technology Corp. PTDE1/0 = 1: turns on partial image. When BASEE = “0”. the base image is displayed. When setting the FP[3:0] and BP[3:0] value.41 . no base image is displayed. the following conditions shall be met: BP + FP ≤ 16 lines FP ≥ 2 lines BP ≥ 2 lines Set the BP[3:0] and FP[3:0] bits as below for each operation modes Operation Mode I80 System Interface Operation Mode RGB interface Operation VSYNC interface Operation BP BP ≥ 2 lines BP ≥ 2 lines BP ≥ 2 lines FP FP ≥ 2 lines FP ≥ 2 lines FP ≥ 2 lines BP+FP FP +BP ≤ 16 lines FP +BP ≤ 16 lines FP +BP = 16 lines FP[3:0] BP[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 Number of lines for Front Porch Number of lines for Back Porch Setting Prohibited Setting Prohibited 2 lines 3 lines 4 lines 5 lines 6 lines 7 lines 8 lines 9 lines Back Porch VSYNC Display Area Front Porch The information contained herein is the exclusive property of ILI Technology Corp. Set the base image display enable bit to 0 (BASEE = 0). PTDE[1:0] Partial image 2 and Partial image 1 enable bits PTDE1/0 = 0: turns off partial image. reproduced. Page 60 of 115 Version: 0. 8. The ILI9320 drives liquid crystal at non-lit display level or displays only partial images. Display Control 2 (R08h) R/W W RS 1 D15 0 D14 0 D13 0 D12 0 D11 FP3 D10 FP2 D9 FP1 D8 FP0 D7 0 D6 0 D5 0 D4 0 D3 BP3 D2 BP2 D1 BP1 D0 BP0 FP[3:0]/BP[3:0] The FP[3:0] and BP[3:0] bits specify the line number of front and back porch periods respectively. and shall not be distributed. When BASEE = “1”.

PTS[2:0] Source output level Grayscale amplifier Step-up clock frequency PTG0 0 1 0 1 Gate outputs in non-display area Normal scan Setting Disabled Interval scan Setting Disabled Source outputs in non-display area Set with the PTS[2:0] bits Set with the PTS[2:0] bits - Vcom output VcomH/VcomL VcomH/VcomL - The information contained herein is the exclusive property of ILI Technology Corp. The polarity is inverted every scan cycle. and shall not be distributed. the operation of amplifiers which generates the grayscales other than V0 and V63 are halted and the step-up clock frequency becomes half the normal frequency in non-display drive period in order to reduce power consumption. reproduced.10. or disclosed in whole or in part without prior written permission of ILI Technology Corp. Display Control 3 (R09h) R/W W RS 1 D15 0 D14 0 D13 0 D12 0 D11 0 D10 PTS2 D9 PTS1 D8 PTS0 D7 0 D6 0 D5 PTG1 D4 PTG0 D3 ISC3 D2 ISC2 D1 ISC1 D0 ISC0 ISC[3:0]: Specify the scan cycle interval of gate driver in non-display area when PTG[1:0]=”10” to select interval scan.41 . When PTS[2] = 1. ISC3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 ISC3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ISC3 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 ISC3 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Scan Cycle 0 frame 3 frame 5 frame 7 frame 9 frame 11 frame 13 frame 15 frame 17 frame 19 frame 21 frame 23 frame 25 frame 27 frame 29 frame 31 frame fFLM=60 Hz 50ms 84ms 117ms 150ms 184ms 217ms 251ms 284ms 317ms 351ms 384ms 418ms 451ms 484ms 518ms PTG[1:0] Set the scan mode in non-display area. Page 61 of 115 Version: 0.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color 1010 1011 1100 1101 1110 1111 10 lines 11 lines 12 lines 13 lines 14 lines Setting Prohibited ILI9320 8. PTG1 0 0 1 1 PTS[2:0] Set the source output level in non-display area drive period (front/back porch period and blank area between partial displays). Then scan cycle is set as odd number from 0~31 frame periods.2.

DM[1:0] Select the display operation mode. DC0) 1/2 frequency setting by DC1.2. DB[17:13] and DB[11:1] 6-bit RGB interface (3 transfers/pixel). DC0) Register Setting(DC1. ILI9320 starts to output FMARK signal in the output interval set by FMI[2:0] bits. DM1 0 0 1 DM0 0 1 0 Display Interface Internal system clock RGB interface VSYNC interface The information contained herein is the exclusive property of ILI Technology Corp. RIM1 0 0 1 1 RIM0 0 1 0 1 RGB Interface Mode 18-bit RGB interface (1 transfer/pixel). and shall not be distributed. DC0 Notes: 1.41 . Page 62 of 115 Version: 0. FMI[2:0] 000 001 011 101 Others Output Interval 1 frame 2 frame 4 frame 6 frame Setting disabled 8. DC0) Register Setting(DC1.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color Positive polarity V63 Setting Prohibited GND Hi-Z V63 Setting Prohibited GND Hi-Z Negative polarity V0 Setting Prohibited GND Hi-Z V0 Setting Prohibited GND Hi-Z in operation V63 to V0 V63 to V0 V63 to V0 V63 and V0 V63 and V0 V63 and V0 ILI9320 000 001 010 011 100 101 110 111 Register Setting(DC1. The gate output level in non-lit display area drive period is determined by PTG[1:0]. DB[17:0] 16-bit RGB interface (1 transfer/pixel). 8.2. reproduced. Display Control 4 (R0Ah) R/W W RS 1 D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 0 D7 0 D6 0 D5 0 D4 0 D3 FMARKOE D2 FMI2 D1 FMI1 D0 FMI0 FMI[2:0] Set the output interval of FMARK signal according to the display data rewrite cycle and data transfer rate. FMARKOE When FMARKOE=1. or disclosed in whole or in part without prior written permission of ILI Technology Corp. DC0 1/2 frequency setting by DC1.12. DB[17:12] Setting disabled Note1: Registers are set only by the system interface.11. DC0 1/2 frequency setting by DC1. RGB Display Interface Control 1 (R0Ch) R/W W RS 1 D15 ENC2 D14 ENC1 D13 ENC0 D12 0 D11 0 D10 0 D9 0 D8 RM D7 0 D6 0 D5 DM1 D4 DM0 D3 0 D2 0 D1 RIM1 D0 RIM0 RIM[1:0] Select the RGB interface data width. The power efficiency can be improved by halting grayscale amplifiers and slowing down the step-up clock frequency only in non-display drive period. 2. Note2: Be sure that one pixel (3 dots) data transfer finished when interface switch.

switching between the RGB interface operation mode and the VSYNC interface operation mode is prohibited. and shall not be distributed. Page 63 of 115 Version: 0. RM Select the interface to access the GRAM. Moving pictures VSYNC interface Note 1: Registers are set only via the system interface or SPI interface. When FMP[8:0]=0.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color 1 1 Setting disabled ILI9320 The DM[1:0] setting allows switching between internal clock operation mode and external display interface operation mode.2. Make sure the 9’h000 ≦ FMP ≦ BP+NL+FP FMP[8:0] 9’h000 9’h001 9’h002 FMARK Output Position 0th line 1st line 2nd line The information contained herein is the exclusive property of ILI Technology Corp. or disclosed in whole or in part without prior written permission of ILI Technology Corp. reproduced. ENC[2:0] Set the GRAM write cycle through the RGB interface ENC[2:0] 000 001 010 011 100 101 110 111 GRAM Write Cycle (Frame periods) 1 Frame 2 Frames 3 Frames 4 Frames 5 Frames 6 Frames 7 Frames 8 Frames 8. RM 0 1 Interface for RAM Access System interface/VSYNC interface RGB interface Display State Still pictures Moving pictures Operation Mode Internal clock operation RGB interface (1) RAM Access (RM) System interface (RM = 0) RGB interface (RM = 1) System interface (RM = 0) System interface (RM = 0) Display Operation Mode (DM[1:0] Internal clock operation (DM[1:0] = 00) RGB interface (DM[1:0] = 01) RGB interface (DM[1:0] = 01) VSYNC interface (DM[1:0] = 10) Rewrite still picture area while RGB interface Displaying moving pictures.13. Set RM to “1” when writing display data by the RGB interface.41 . However. Note 2: Refer to the flowcharts of “RGB Input Interface” section for the mode switch. a high-active pulse FMARK is output at the start of back porch period for one display line period (1H). Frame Marker Position (R0Dh) R/W W RS 1 D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 D7 D6 D5 D4 D3 D2 D1 D0 FMP8 FMP7 FMP6 FMP5 FMP4 FMP3 FMP2 FMP1 FMP0 EMP[8:0] Sets the output position of frame cycle (frame marker).

373rd line 374th line 375th line ILI9320 8. .a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color 9’h003 .2. Exit sleep mode (SLP = “0”) b. The information contained herein is the exclusive property of ILI Technology Corp.41 . or disclosed in whole or in part without prior written permission of ILI Technology Corp. VSPL = “0” Low active VSPL = “1” High active 8.14. In deep standby mode. Power Control 1 (R10h) R/W W RS 1 D15 0 D14 0 D13 0 D12 SAP D11 BT3 D10 BT2 D9 BT1 D8 BT0 D7 APE D6 AP2 D5 AP1 D4 AP0 D3 0 D2 DSTB D1 SLP D0 0 SLP: When SLP = 1. HSPL: Sets the signal polarity of the SYNC pin. . Page 64 of 115 Version: 0. the internal logic power supply is turned off to reduce power consumption.15. Start oscillation DSTB: When DSTB = 1. ILI9320 enters the sleep mode and the display operation stops except the RC oscillator to reduce the power consumption. reproduced. RGB Display Interface Control 2 (R0Fh) R/W W RS 1 D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 0 D7 0 D6 0 D5 0 D4 VSPL D3 HSPL D2 0 D1 EPL D0 DPL DPL: Sets the signal polarity of the DOTCLK pin. and shall not be distributed. DPL = “0” The data is input on the rising edge of DOTCLK DPL = “1” The data is input on the falling edge of DOTCLK EPL: Sets the signal polarity of the ENABLE pin. Disable data write operation when ENABLE = “1”. a. Disable data write operation when ENABLE = “0”. The GRAM data and instruction setting are not maintained when the ILI9320 enters the deep standby mode.2. . EPL = “0” The data DB17-0 is written when ENABLE = “0”. HSPL = “0” Low active HSPL = “1” High active VSPL: Sets the signal polarity of the VSYNC pin. . 9’h175 9’h176 9’h177 3rd line . the GRAM data and instructions cannot be updated except the following two instructions. the ILI9320 enters the deep standby mode. In the sleep mode. and they must be reset after exiting deep standby mode. EPL = “1” The data DB17-0 is written when ENABLE = “1”.

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 AP[2:0]: Adjusts the constant current in the operational amplifier circuit in the LCD power supply circuit. The larger constant current enhances the drivability of the LCD.Vci1 x 3 . VGH. When starting the charge-pump of LCD in the Power ON stage.75 1 0. To reduce power consumption.Vci1 x 4 .Vci1 x 3 .Vci1 Vci1 x 9 Vci1 x 3 . APE: Power supply enable bit.5 0.Vci1 VGH Vci1 x 6 Vci1 x 8 VGL . and shall not be distributed.Vci1 .Vci1 . SAP=1.Vci1 x 4 . but it also increases the current consumption.75 1 In Source driver amplifiers Halt 0. Source driver output is enabled. reproduced.Vci1 Vci1 x 7 DDVDH Vci1 x 2 Vci1 x 2 VCL . Select the optimal step-up factor for the operating voltage. set a smaller factor.62 0.Vci1 x 5 .Vci1 Vci1 x 10 Vci1 x 2 Vci1 x 3 Vci1 x 3 .Vci1 x 4 . BT[3:0]: Sets the factor used in the step-up circuits. BT[3:0] 4’h0 4’h1 4’h2 4’h3 4’h4 4’h5 4’h6 4’h7 4’h8 4’h9 4’hA 4’hB 4’hC 4’hD 4’hE 4’hF Vci1 x 3 .Vci1 x 5 .Vci1 x 4 .Vci1 .62 0. after starting up the LCD power supply circuit. Source driver output is disabled. make sure that SAP=0.Vci1 x 3 . or disclosed in whole or in part without prior written permission of ILI Technology Corp.Vci1 x 6 .5 0.71 1 In LCD drive power supply amplifiers Halt operational amplifiers and step-up circuits 0. Adjust the constant current taking the trade-off into account between the display quality and the current consumption. set AP[2:0] = “000” to halt the operational amplifier circuits and the step-up circuits to reduce current consumption.Vci1 x 4 .Vci1 x 7 . and set the SAP=1. VGL and VCL levels.71 1 SAP: Source Driver output control SAP=0. The information contained herein is the exclusive property of ILI Technology Corp. Connect capacitors to the capacitor connection pins when generating DDVDH. In no-display period. Set APE = “1” to start the generation of power supply according to the power supply startup sequence. Page 65 of 115 Version: 0.Vci1 x 6 .41 .Vci1 x 7 .Vci1 Vci1 x 6 Vci1 x 9 Vci1 x 12 Vci1 x 2 .Vci1 x 4 Notes: 1.Vci1 x 6 . AP[2:0] 000 001 010 011 100 101 110 111 0.

reproduced. and shall not be distributed.94 x Vci 0. DC1[2:0]: Selects the operating frequency of the step-up circuit 2.2.89 x Vci Setting disabled Setting disabled 0. VGH = 15.0V (max. Power Control 2 (R11h) R/W W RS 1 D15 0 D14 0 D13 0 D12 0 D11 0 D10 DC12 D9 DC11 D8 DC10 D7 0 D6 DC02 D5 DC01 D4 DC00 D3 0 D2 VC2 D1 VC1 D0 VC0 VC[2:0] Sets the ratio factor of VciLVL to generate the reference voltages VciOUT and Vci1.17.41 .6 ~ 1. which is a reference level for the VCOM level and the grayscale voltage level.0V (max. 8. The higher step-up operating frequency enhances the drivability of the step-up circuit and the quality of display but increases the current consumption.0V (max.5V (max) and VCL= -3. The information contained herein is the exclusive property of ILI Technology Corp. DC02 0 0 0 0 1 1 1 1 DC01 0 0 1 1 0 0 1 1 DC00 0 1 0 1 0 1 0 1 Step-up circuit1 step-up frequency (fDCDC1) Fosc Fosc / 2 Fosc / 4 Fosc / 8 Fosc / 16 Setting disabled Halt step-up circuit 1 Setting disabled DC12 0 0 0 0 1 1 1 1 DC11 0 0 1 1 0 0 1 1 DC10 0 1 0 1 0 1 0 1 Step-up circuit2 step-up frequency (fDCDC2) Fosc / 16 Fosc / 32 Fosc / 64 Fosc / 128 Fosc / 256 Setting disabled Halt step-up circuit 2 Setting disabled Note: Be sure fDCDC1≥fDCDC2 when setting DC0[2:0] and DC1[2:0]. VC2 0 0 0 0 1 1 1 1 VC1 0 0 1 1 0 0 1 1 VC0 0 1 0 1 0 1 0 1 VciOUT reference voltage Vci1 voltage 0. or disclosed in whole or in part without prior written permission of ILI Technology Corp. Make sure DDVDH = 6.9) of VciLVL applied to output the VREG1OUT level.16.) 8. The higher step-up operating frequency enhances the drivability of the step-up circuit and the quality of display but increases the current consumption.76 x Vci Setting disabled Setting disabled 1. Power Control 3 (R12h) R/W W RS 1 D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 VCMR D7 0 D6 0 D5 0 D4 PON D3 VRH3 D2 VRH2 D1 VRH1 D0 VRH0 VRH[3:0] Set the amplifying rate (1.2.0 x Vci DC0[2:0]: Selects the operating frequency of the step-up circuit 1. Adjust the frequency taking the trade-off between the display quality and the current consumption into account.). VGL = – 12.).a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 2. Page 66 of 115 Version: 0. Adjust the frequency taking the trade-off between the display quality and the current consumption into account.

24 x VREG1OUT .92 1 0 0 1 1 VREG1OUT x 0.89 1 0 0 1 0 VREG1OUT x 0. reproduced.96 1 0 1 0 1 VREG1OUT x 0. GRAM Horizontal/Vertical Address Set (R20h.85 VciLVL x 1.06 1 1 0 0 1 VREG1OUT x 1.19 1 1 1 1 0 VREG1OUT x 1.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color VRH3 0 0 0 0 0 0 0 0 VRH2 0 0 0 0 1 1 1 1 VRH1 0 0 1 1 0 0 1 1 VRH0 0 1 0 1 0 1 0 1 VREG1OUT Halt Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited VRH3 1 1 1 1 1 1 1 1 VRH2 0 0 0 0 1 1 1 1 VRH1 0 0 1 1 0 0 1 1 VRH0 0 1 0 1 0 1 0 1 ILI9320 VREG1OUT VciLVL x 1.70 VciLVL x 1.94 0 1 1 0 1 VREG1OUT x 0.16 1 1 1 0 1 VREG1OUT x 1. 8. PON=0 PON=1 VGL output is disable VGL output is enable VCMR: Selects either external resistor (VcomR) or internal electric volume (VCM) to set the electrical potential of VcomH (Vcom center voltage level). 8.2.98 0 1 1 1 1 VREG1OUT x 1.78 0 0 1 0 1 VREG1OUT x 0.04 1 1 0 0 0 VREG1OUT x 1. PON: Control ON/OFF of circuit3 (VGL) output.76 0 0 1 0 0 VREG1OUT x 0.09 1 1 0 1 0 VREG1OUT x 1. VDV4 VDV3 VDV2 VDV1 VDV0 VCOM amplitude 0 0 0 0 0 VREG1OUT x 0.88 0 1 0 1 0 VREG1OUT x 0.0.74 0 0 0 1 1 VREG1OUT x 0.87 1 0 0 0 1 VREG1OUT x 0.41 .65 VciLVL x 1.60 VciLVL x 1.18. VCMR = 0 Using the external variable resistor to adjust the VcomH voltage level VCMR = 1 Using the Internal electronic volume (VCM[4:0]) to adjust the VcomH voltage level.19.72 0 0 0 1 0 VREG1OUT x 0.70 0 0 0 0 1 VREG1OUT x 0.84 0 1 0 0 0 VREG1OUT x 0. or disclosed in whole or in part without prior written permission of ILI Technology Corp.99 1 0 1 1 0 VREG1OUT x 1.5)V.01 1 0 1 1 1 VREG1OUT x 1. R21h) R/W W W RS 1 1 D15 0 0 D14 0 0 D13 0 0 D12 0 0 D11 0 0 D10 0 0 D9 0 0 D8 0 AD16 D7 AD7 AD15 D6 AD6 AD14 D5 AD5 AD13 D4 AD4 AD12 D3 AD3 AD11 D2 AD2 AD10 D1 AD1 AD9 D0 AD0 AD8 AD[16:0] Set the initial value of address counter (AC).92 0 1 1 0 0 VREG1OUT x 0. The information contained herein is the exclusive property of ILI Technology Corp.21 1 1 1 1 1 VREG1OUT x 1.80 0 0 1 1 0 VREG1OUT x 0.75 VciLVL x 1.86 0 1 0 0 1 VREG1OUT x 0.90 Setting inhibited Make sure that VC and VRH setting restriction: VREG1OUT ≦ (DDVDH .11 1 1 1 1 1 VREG1OUT x 1.96 0 1 1 1 0 VREG1OUT x 0.24 Set VDV[4:0] to let Vcom amplitude less than 6V.82 0 0 1 1 1 VREG1OUT x 0. and shall not be distributed.00 VDV4 VDV3 VDV2 VDV1 VDV0 VCOM amplitude 1 0 0 0 0 VREG1OUT x 0.90 0 1 1 1 1 VREG1OUT x 0.2.80 VciLVL x 1. Page 67 of 115 Version: 0.14 1 1 1 0 0 VREG1OUT x 1.70 to 1. Power Control 4 (R13h) R/W W RS 1 D15 0 D14 0 D13 0 D12 D11 D10 VDV2 D9 VDV1 D8 VDV0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 VDV4 VDV3 VDV[4:0] Select the factor of VREG1OUT to set the amplitude of Vcom alternating voltage from 0.94 1 0 1 0 0 VREG1OUT x 0.

20. the address AD[16:0] is set to the address counter 8. Note2: When the internal clock operation or the VSYNC interface mode is selected (RM = “0”).41 . the DB[17:0] pin assignment differs for each interface. or disclosed in whole or in part without prior written permission of ILI Technology Corp.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 The address counter (AC) is automatically updated in accordance to the setting of the AM. This register is the GRAM access port. RD[17:0] Read 18-bit data from GRAM through the read data register (RDR). the address AD[16:0] is set to address counter when update register R21. GRAM Data Map 1st line GRAM Data 2nd line GRAM Data 3rd line GRAM Data 4th line GRAM Data 318th line GRAM Data 319th line GRAM Data 320th line GRAM Data Note1: When the RGB interface is selected (RM = “1”).21. Read Data from GRAM (R22h) R/W R RS 1 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 RAM Read Data (RD[17:0]. The information contained herein is the exclusive property of ILI Technology Corp.2. the address counter (AC) is increased/decreased automatically. The address counter is not automatically updated when read data from the internal GRAM. Page 68 of 115 Version: 0. AD[16:0] 17’h00000 ~ 17’h000EF 17’h00100 ~ 17’h001EF 17’h00200 ~ 17’h002EF 17’h00300 ~ 17’h003EF 17’h13D00 ~ 17’ h13DEF 17’h13E00 ~ 17’ h13EEF 17’h13F00 ~ 17’h13FEF every frame on the falling edge of VSYNC. When update the display data through this register. reproduced. I/D bits as data is written to the internal GRAM. Write Data to GRAM (R22h) R/W W RS 1 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 RAM write data (WD[17:0].2. and shall not be distributed. the DB[17:0] pin assignment differs for each interface. 8.

reproduced. Page 69 of 115 Version: 0. or disclosed in whole or in part without prior written permission of ILI Technology Corp.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 18-bit System Interface GRAM Data & RGB Mapping R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 Write Data Register RD 17 RD 16 RD 15 RD 14 RD 13 RD 12 RD 11 RD 10 RD 9 RD 8 RD 7 RD 6 RD 5 RD 4 RD 3 RD 2 RD 1 RD 0 Output Data DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB 0 16-bit System Interface GRAM Data & RGB Mapping R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 Write Data Register RD 17 RD 16 RD 15 RD 14 RD 13 RD 12 RD 11 RD 10 RD 9 RD 8 RD 7 RD 6 RD 5 RD 4 RD 3 RD 2 RD 1 RD 0 Output Data DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 9-bit System Interface GRAM Data & RGB Mapping R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 Write Data Register RD 17 RD 16 RD 15 RD 14 RD 13 RD 12 RD 11 RD 10 RD 9 RD 8 RD 7 RD 6 RD 5 RD 4 RD 3 RD 2 RD 1 RD 0 Output Data DB 17 DB 16 DB 15 DB 14 DB 13 1st Transfer DB 12 DB 11 DB 10 DB 9 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 2nd Transfer 8-bit System Interface / Serial Data Transfer Interface GRAM Data & RGB Mapping R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 Write Data Register RD 17 RD 16 RD 15 RD 14 RD 13 RD 12 RD 11 RD 10 RD 9 RD 8 RD 7 RD 6 RD 5 RD 4 RD 3 RD 2 RD 1 RD 0 Output Data DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 1st Transfer 2nd Transfer Figure 28 Data Read from GRAM through Read Data Register in 18-/16-/9-/8-bit Interface Mode The information contained herein is the exclusive property of ILI Technology Corp.41 . and shall not be distributed.

85 1 0 0 0 1 VREG1OUT x 0.88 1 0 1 0 0 VREG1OUT x 0. the VcomH voltage is generated based on the external reference voltage VCOMR.71 0 0 0 1 1 VREG1OUT x 0. and shall not be distributed. VCMR =1.89 The information contained herein is the exclusive property of ILI Technology Corp. or disclosed in whole or in part without prior written permission of ILI Technology Corp. VCMR =0.86 1 0 0 1 0 VREG1OUT x 0. VCM4 VCM3 VCM2 VCM1 VCM0 VCOMH 0 0 0 0 0 VREG1OUT x 0.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 Set I/D AM. VSA/VEA Set address M Dummy read (invalid data) GRAM -> Read data latch Read Output (data of address M) Read datalatch -> DB[17:0] Read Output (data of address M+1) Read datalatch -> DB[17:0] Set address N Dummy read (invalid data) GRAM -> Read data latch Read Output (data of address N) Read datalatch -> DB[17:0] Figure 29 GRAM Data Read Back Flow Chart 8.69 0 0 0 0 1 VREG1OUT x 0. HAS/HEA. Page 70 of 115 Version: 0.22. the VcomH voltage is generated based on the VCM[4:0] setting value. reproduced. Power Control 7 (R29h) R/W W RS 1 D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 0 D7 0 D6 0 D5 0 D4 D3 D2 D1 D0 VCM4 VCM3 VCM2 VCM1 VCM0 VCM[4:0] Set the internal VcomH voltage.87 1 0 0 1 1 VREG1OUT x 0.2.41 .70 0 0 0 1 0 VREG1OUT x 0.72 0 0 1 0 0 VREG1OUT x 0.73 VCM4 VCM3 VCM2 VCM1 VCM0 VCOMH 1 0 0 0 0 VREG1OUT x 0.

EXT_R 0 1 Resistor Selection Internal Resistor (default) External Resistor FR_SEL[1:0] Set the frame rate when the internal resistor is used for oscillator circuit.78 x 0.74 x 0. the 24-bit input data will be dithered into 18-bit and the display quality is close to 16.98 x 0.99 x 1.77 x 0.90 x 0. When the dithering function is enabled.83 x 0.93 x 0.82 x 0. Dither 0 1 Dither Function Disable (default) Enable The input data transfer format is as below (16M_EN=1.97 x 0. Frame Rate and Color Control (R2Bh) R/W W RS 1 D15 D14 D13 0 D12 D11 0 0 D10 0 D9 0 D8 0 D7 EXT_R D6 0 D5 D4 D3 0 D2 0 D1 0 D0 0 16M_EN Dither FR_SEL1 FR_SEL0 EXT_R External or internal resistor selection for oscillator circuit. FR_SEL1 FR_SEL0 0 0 0 1 1 0 1 1 Frame Rate (Hz) 90 (default) 80 110 100 16M_EN Select the color depth. Page 71 of 115 Version: 0.76 x 0. Dither=1).00 8.2.7 million colors. DB[8:1] The information contained herein is the exclusive property of ILI Technology Corp.84 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 ILI9320 VREG1OUT VREG1OUT VREG1OUT VREG1OUT VREG1OUT VREG1OUT VREG1OUT VREG1OUT VREG1OUT VREG1OUT VREG1OUT x 0. 18bit interface: 2 transfer mode 1st Transfer: DB[17:10].41 .92 x 0.96 x 0. and shall not be distributed. reproduced.23. or disclosed in whole or in part without prior written permission of ILI Technology Corp.81 x 0.94 x 0.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 VREG1OUT VREG1OUT VREG1OUT VREG1OUT VREG1OUT VREG1OUT VREG1OUT VREG1OUT VREG1OUT VREG1OUT VREG1OUT x 0. 16M_EN 0 1 Color Depth Selection 262K Color (default) 16M Color Dither Dithering function control.80 x 0.79 x 0.75 x 0.91 x 0.95 x 0.

8. R53h) R/W R50h R51h R52h R53h W W W W RS 1 1 1 1 D15 D14 D13 D12 D11 D10 D9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D8 0 0 D7 D6 D5 D4 D3 D2 D1 D0 HSA7 HSA6 HSA5 HSA4 HSA3 HSA2 HSA1 HSA0 HEA7 HEA6 HEA5 HEA4 HEA3 HEA2 HEA1 HEA0 0 VSA8 VSA7 VSA6 VSA5 VSA4 VSA3 VSA2 VSA1 VSA0 0 VEA8 VEA7 VEA6 VEA5 VEA4 VEA3 VEA2 VEA1 VEA0 HSA[7:0]/HEA[7:0] HSA[7:0] and HEA[7:0] represent the respective addresses at the start and end of the The information contained herein is the exclusive property of ILI Technology Corp. DB[8:1] 2nd Transfer: DB[17:10] 8 bit interface: 3 transfer mode (TRIREG =1. or disclosed in whole or in part without prior written permission of ILI Technology Corp.2.25. DFM=0) 1st Transfer: DB[17:10]. R52h.2. and shall not be distributed.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color 2nd Transfer: DB[17:10] 16 bit interface: 2 transfer mode (TRIREG =1. R51h. Page 72 of 115 Version: 0. Horizontal and Vertical RAM Address Position (R50h.41 . reproduced.24. DFM=1) 1st Transfer: DB[17:10] 2nd Transfer: DB[17:10] 3rd Transfer: DB[17:10] ILI9320 8. Gamma Control (R30h ~ R3Dh) R/W R30h R31h R32h R35h R36h R37h R38h R39h R3Ch R3Dh W W W W W W W W W W RS 1 1 1 1 1 1 1 1 1 1 D15 D14 D13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D12 0 0 0 0 D11 0 0 0 0 D10 KP1[2] KP3[2] KP5[2] RP1[2] D9 KP1[1] KP3[1] KP5[1] RP1[1] D8 KP1[0] KP3[0] KP5[0] RP1[0] D7 D6 D5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D4 0 0 0 0 D3 0 0 0 0 D2 KP0[2] KP2[2] KP4[2] RP0[2] D1 KP0[1] KP2[1] KP4[1] RP0[1] D0 KP0[0] KP2[0] KP4[0] RP0[0] VRP1[4] VRP1[3] VRP1[2] VRP1[1] VRP1[0] 0 0 0 0 0 0 0 0 0 KN1[2] KN3[2] KN5[2] RN1[2] KN1[1] KN3[1] KN5[1] RN1[1] KN1[0] KN3[0] KN5[0] RN1[0] 0 0 0 0 0 VRP0[4] VRP0[3] VRP0[2] VRP0[1] VRP0[0] 0 0 0 0 0 0 0 0 0 0 0 0 KN0[2] KN2[2] KN4[2] RN0[2] KN0[1] KN2[1] KN4[1] RN0[1] KN0[0] KN2[0] KN4[0] RN0[0] VRN1[4] VRN1[3] VRN1[2] VRN1[1] VRN1[0] 0 0 VRN0[4] VRN0[3] VRN0[2] VRN0[1] VRN0[0] KP5-0[2:0] : γfine adjustment register for positive polarity RP1-0[2:0] : γgradient adjustment register for positive polarity VRP1-0[4:0] : γamplitude adjustment register for positive polarity KN5-0[2:0] : γfine adjustment register for negative polarity RN1-0[2:0] : γgradient adjustment register for negative polarity VRN1-0[4:0] : γamplitude adjustment register for negative polarity For details “γ-Correction Function” section.

The HSA and HEA bits must be set before starting RAM write operation. reproduced.41 . see the High-Speed RAM Write Function section. By setting VSA and VEA bits. The VSA and VEA bits must be set before starting RAM write operation. Note2. it is possible to limit the area on the GRAM vertically for writing data. it is possible to limit the area on the GRAM horizontally for writing data. Gate Scan Control (R60h. and shall not be distributed. 8. In setting these bits. the dummy write operations should be inserted depending on the window address area. be sure “00”h ≤ HSA[7:0]< HEA[7:0] ≤ “EF”h. The window address range must be within the GRAM address space. HSA 0000h HEA VSA Window Address Area VEA GRAM Address Area 13FEFh Figure 30 GRAM Access Range Configuration “00”h ≤HAS[7:0] ≤HEA[7:0] ≤”EF”h “00”h ≤VSA[7:0] ≤VEA[7:0] ≤”13F”h Note1. Page 73 of 115 Version: 0. and “04”h≦HEA-HAS. VSA[8:0]/VEA[8:0] VSA[8:0] and VEA[8:0] represent the respective addresses at the start and end of the window address area in vertical direction. For details. R61h.26. Data are written to GRAM in four-words when operating in high speed mode.2. R6Ah) R/W R60h R61h R6Ah W W W RS 1 1 1 D15 GS 0 0 D14 0 0 0 D13 NL5 0 0 D12 NL4 0 0 D11 NL3 0 0 D10 NL2 0 0 D9 NL1 0 0 D8 NL0 0 VL8 D7 0 0 VL7 D6 0 0 VL6 D5 D4 D3 D2 D1 D0 SCN5 SCN4 SCN3 SCN2 SCN1 SCN0 0 VL5 0 VL4 0 VL3 NDL VL2 VLE VL1 REV VL0 SCN[5:0] The ILI9320 allows to specify the gate line from which the gate driver starts to scan by setting the The information contained herein is the exclusive property of ILI Technology Corp. By setting HSA and HEA bits. or disclosed in whole or in part without prior written permission of ILI Technology Corp. be sure “000”h ≤ VSA[8:0]< VEA[8:0] ≤ “13F”h.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 window address area in horizontal direction. In setting.

Page 74 of 115 Version: 0. and shall not be distributed.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color SCN[5:0] bits. or disclosed in whole or in part without prior written permission of ILI Technology Corp. The number of lines must be the same or more than the number of lines necessary for the size of the liquid crystal panel. The GRAM address mapping is not affected by the number of lines set by NL[5:0].41 . reproduced. Scanning Start Position ILI9320 SCN[5:0] 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h ~ 3Fh SM=0 GS=0 G1 G9 G17 G25 G33 G41 G49 G57 G65 G73 G81 G89 G97 G105 G113 G121 G129 G137 G145 G153 G161 G169 G177 G185 G193 G201 G209 G217 G225 G233 G241 G249 G257 G265 G273 G281 G289 G297 G305 G313 Setting disabled GS=1 G320 G312 G304 G296 G288 G280 G272 G264 G256 G248 G240 G232 G224 G216 G208 G200 G192 G184 G176 G168 G160 G152 G144 G136 G128 G120 G112 G104 G96 G88 G80 G72 G64 G56 G48 G40 G32 G24 G16 G8 Setting disabled SM=1 GS=0 G1 G17 G33 G49 G65 G81 G97 G113 G129 G145 G161 G177 G193 G209 G2 G18 G34 G50 G66 G82 G98 G114 G130 G146 G162 G178 G194 G114 G130 G146 G162 G178 G194 G210 G226 G242 G258 G274 G290 G306 Setting disabled GS=1 G320 G304 G288 G272 G256 G240 G224 G208 G192 G176 G160 G144 G128 G112 G96 G80 G64 G48 G32 G16 G319 G303 G287 G271 G255 G239 G223 G207 G191 G175 G159 G143 G127 G111 G95 G79 G63 G47 G31 G15 Setting disabled NL[5:0]: Sets the number of lines to drive the LCD at an interval of 8 lines. NL[5:0] LCD Drive Line The information contained herein is the exclusive property of ILI Technology Corp.

When VLE = 1. When GS = 1. . . . make sure to set VLE = “0”.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color 6’h1D 6’h1E 6’h1F 6’h20 6’h21 6’h22 6’h23 6’h24 6’h25 6’h26 6’h27 Others 240 lines 248 lines 256 lines 264 lines 272 lines 280 lines 288 lines 296 lines 304 lines 312 line 320 line Setting inhibited ILI9320 NDL: Sets the source driver output level in the non-display area. V63 V0 REV GRAM Data 18’h00000 . Page 75 of 115 Version: 0. The scan direction determined by GS = 0 can be reversed by setting GS = 1. . reproduced. In this case. . . . the scan direction is from G320 to G1 REV: Enables the grayscale inversion of the image by setting REV=1. NDL 0 1 Non-Display Area Positive Polarity Negative Polarity V63 V0 V0 V63 GS: Sets the direction of scan by the gate driver in the range determined by SCN[4:0] and NL[4:0]. V0 V63 V0 V63 . and shall not be distributed. . . which is the number of lines to shift the start line of the display from the first line of the physical display. Source Output in Display Area Positive polarity negative polarity V63 V0 . VLE 0 Base Image Display Fixed The information contained herein is the exclusive property of ILI Technology Corp. or disclosed in whole or in part without prior written permission of ILI Technology Corp. . . . 18’h3FFFF 0 1 VLE: Vertical scroll display enable bit. . Note that the partial image display position is not affected by the base image scrolling. VL[8:0] sets the amount of scrolling. the scan direction is from G1 to G320. When GS = 0. the ILI9320 starts displaying the base image from the line (of the physical display) determined by VL[8:0] bits.41 . 18’h3FFFF 18’h00000 . The vertical scrolling is not available in external display interface operation. .

8. R85h) R/W W W RS 1 1 D15 0 0 D14 0 0 D13 0 0 D12 0 0 D11 0 0 D10 0 0 D9 0 A1[8] A1[7] 0 PTE PTE A1[8] A1[7] A1[6] PTE A1[6] A1[5] PTE A1[5] A1[4] PTE A1[4] A1[3] PTE A1[3] A1[2] PTE A1[2] A1[1] PTE A1[1] A1[0] PTE A1[0] D8 D7 D6 PTS D5 PTS D4 PTS D3 PTS D2 PTS D1 PTS D0 PTS PTS PTS PTSA1[8:0] PTEA1[8:0]: Sets the start line address and the end line address of the RAM area storing the data of partial image 2 Make sure PTSA1[8:0] ≤ PTEA1[8:0]. 8.41 .29. Make sure PTSA0[8:0] ≤ PTEA0[8:0]. The display areas of the partial images 1 and 2 must not overlap each another. or disclosed in whole or in part without prior written permission of ILI Technology Corp. Partial Image 1 RAM Start/End Address (R81h.2.2.2. reproduced.2.30. Panel Interface Control 1 (R90h) R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 The information contained herein is the exclusive property of ILI Technology Corp. 8.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color 1 Enable Scrolling ILI9320 VL[8:0]: Sets the scrolling amount of base image. Partial Image 2 RAM Start/End Address (R84h. R82h) R/W W W RS 1 1 D15 0 0 D14 0 0 D13 0 0 D12 0 0 D11 0 0 D10 0 0 D9 0 A0[8] 0 PTE A0[8] A0[7] PTE A0[7] A0[6] PTE A0[6] A0[5] PTE A0[5] A0[4] PTE A0[4] A0[3] PTE A0[3] A0[2] PTE A0[2] A0[1] PTE A0[1] A0[0] PTE A0[0] D8 PTS D7 PTS D6 PTS D5 PTS D4 PTS D3 PTS D2 PTS D1 PTS D0 PTS PTSA0[8:0] PTEA0[8:0]: Sets the start line address and the end line address of the RAM area storing the data of partial image 1. Page 76 of 115 Version: 0.27. Partial Image 2 Display Position (R83h) R/W W RS 1 D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 A1[8] P1[7] P1[6] P1[5] P1[4] P1[3] P1[2] P1[1] P1[0] D8 D7 D6 PTD D5 PTD D4 PTD D3 PTD D2 PTD D1 PTD D0 PTD PTS PTD PTDP1[8:0]: Sets the display position of partial image 2 The display areas of the partial images 1 and 2 must not overlap each another. Make sure that VL[8:0] ≦ 320. 8.31.28. The base image is scrolled in vertical direction and displayed from the line determined by VL[8:0]. Partial Image 1 Display Position (R80h) R/W W RS 1 D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 P0[8] P0[7] P0[6] P0[5] P0[4] P0[3] P0[2] P0[1] P0[0] D8 PTD D7 PTD D6 PTD D5 PTD D4 PTD D3 PTD D2 PTD D1 PTD D0 PTD PTDP0[8:0]: Sets the display position of partial image 1. 8. and shall not be distributed.2.

In this mode. reproduced.32. ILI9320 display operation is synchronized with internal clock signal. RTNI[4:0] 00000~01111 10000 10001 10010 10011 10100 10101 10110 10111 Clocks/Line Setting Disabled 16 clocks 17 clocks 18 clocks 19 clocks 20 clocks 21 clocks 22 clocks 23 clocks RTNI[4:0] 11000 11001 11010 11011 11100 11101 11110 11111 Clocks/Line 24 clocks 25 clocks 26 clocks 27 clocks 28 clocks 29 clocks 30 clocks 31 clocks DIVI[1:0]: Sets the division ratio of internal clock frequency. DIVI1 0 0 1 1 DIVI0 0 1 0 1 Division Ratio 1 2 4 8 Internal Operation Clock Frequency fosc / 1 fosc / 2 fosc / 4 fosc / 8 Formula to calculate frame frequency Frame Rate = fosc.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color W 1 0 0 0 0 0 0 0 DIVI1 DIVI0 0 0 RTNI4 RTNI3 ILI9320 RTNI2 RTNI1 RTNI0 RTNI[4:0]: Sets 1H (line) clock number of internal clock operating mode. Back porch lines 8. Clock cycles per line : RTN bits Division ratio : DIV bits Lines : number of lines for driving the LCD panel.41 .2. FP: Front porch lines BP. or disclosed in whole or in part without prior written permission of ILI Technology Corp. and shall not be distributed. NOWI[2:0] 000 001 010 011 100 101 110 111 Gate Non-overlap Period 0 clocks 1 clocks 2 clocks 3 clocks 4 clocks 5 clocks 6 clocks 7 clocks The information contained herein is the exclusive property of ILI Technology Corp. Page 77 of 115 Version: 0. Clock cycles per line x division ratio x (Lines +BP+FP) fosc. : frequency if RC oscillation. Panel Interface Control 2 (R92h) R/W W RS 1 D15 0 D14 0 D13 0 D12 0 D11 0 D10 D9 D8 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 NOWI[2] NOWI[1] NOWI[0] NOWI[2:0]: Sets the gate output non-overlap period when ILI9320 display operation is synchronized with internal clock signal.

8. reproduced. RTNE[5:0] Clocks per line period (1H) RTNE[5:0] Clocks per line period (1H) RTNE[5:0] Clocks per line period (1H) RTNE[5:0] Clocks per line period (1H) 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh Setting Prohibited Setting Prohibited Setting Prohibited Setting Prohibited Setting Prohibited Setting Prohibited Setting Prohibited Setting Prohibited Setting Prohibited Setting Prohibited Setting Prohibited Setting Prohibited Setting Prohibited Setting Prohibited Setting Prohibited Setting Prohibited 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 16 clocks 17 clocks 18 clocks 19 clocks 20 clocks 21 clocks 22 clocks 23 clocks 24 clocks 25 clocks 26 clocks 27 clocks 28 clocks 29 clocks 30 clocks 31 clocks 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2ah 2bh 2ch 2dh 2eh 2fh 32 clocks 33 clocks 34 clocks 35 clocks 36 clocks 37 clocks 38 clocks 39 clocks 40 clocks 41 clocks 42 clocks 43 clocks 44 clocks 45 clocks 46 clocks 47 clocks 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3ah 3bh 3ch 3dh 3eh 3fh 48 clocks 49 clocks 50 clocks 51 clocks 52 clocks 53 clocks 54 clocks 55 clocks 56 clocks 57 clocks 58 clocks 59 clocks 60 clocks 61 clocks 62 clocks 63 clocks DIVE[1:0]: Sets the division ratio of DOTCLK when ILI9320 display operation is synchronized with RGB interface signals.2. from the reference point. Page 78 of 115 Version: 0. and shall not be distributed. The information contained herein is the exclusive property of ILI Technology Corp. or disclosed in whole or in part without prior written permission of ILI Technology Corp.34.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 Note: The gate output non-overlap period is defined by the number of frequency-divided internal clocks. from the reference point. 8. Panel Interface Control 4 (R95h) R/W W RS 1 D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 D8 D7 0 D6 0 D5 D4 D3 D2 D1 D0 DIVE1 DIVE0 RTNE5 RTNE4 RTNE3 RTNE2 RTNE1 RTNE0 RTNE[5:0]: Sets 1H (line) clock number of RGB interface mode. the frequency of which is determined by instruction (DIVI). ILI9320 display operation is synchronized with RGB interface signals. the frequency of which is determined by instruction (DIVI[1:0]). In this mode.41 . MCPI[2:0] 000 001 010 011 100 101 110 111 Source Output Position Setting inhibited 1 clocks 2 clocks 3 clocks 4 clocks 5 clocks 6 clocks 7 clocks Note: The gate output non-overlap period is defined by the number of frequency-divided internal clocks.2. Panel Interface Control 3 (R93h) R/W W RS 1 D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 D1 D0 MCPI2 MCPI1 MCPI0 MCPI[2:0]: Sets the source output position when ILI9320 display operation is synchronized with internal clock signal. DIVE (division ratio) x RTNE (DOTCLKs) ≤ DOTCLKs in 1H period.33.

NOWE[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 Gate Non-overlap Period 0 clocks 1 clocks 2 clocks 3 clocks 4 clocks 5 clocks 6 clocks 7 clocks NOWE[3:0] 1000 1001 1010 1011 1100 1101 1110 1111 Gate Non-overlap Period 8 clocks 9 clocks 10 clocks 11 clocks 12 clocks 13 clocks 14 clocks 15 clocks Note: 1 clock = (number of data transfer/pixel) x DIVE (division ratio) [DOTCLK] 8. Panel Interface Control 5 (R97h) R/W W RS 1 D15 0 D14 0 D13 0 D12 0 D11 D10 D9 D8 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 NOWE3 NOWE2 NOWE1 NOWE0 NOWE[2:0]: Sets the gate output non-overlap period when the ILI9320 display operation is synchronized with RGB interface signals. MCPE[2:0] 000 001 010 011 100 101 110 111 Source Output Position 0 clocks 1 clocks 2 clocks 3 clocks 4 clocks 5 clocks 6 clocks 7 clocks Note: 1 clock = (number of data transfer/pixel) x DIVE (division ratio) [DOTCLK] The information contained herein is the exclusive property of ILI Technology Corp.8 μs 1. or disclosed in whole or in part without prior written permission of ILI Technology Corp.6 μs 3.8 μs 1.2 μs DIVE[1:0] 00 01 10 11 Division Ratio Setting Prohibited 1/4 1/8 1/16 18/16-bit RGB Interface Setting Prohibited 4 8 16 DOTCLKS DOTCLKS DOTCLKS DOTCLK=5MHz 0.2. Panel Interface Control 6 (R98h) R/W W RS 1 D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 D1 D0 MCPE2 MCPE1 MCPE0 MCPE[2:0]: Sets the source output position when the ILI9320 display operation is synchronized with RGB interface signals.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 DOTCLK=5MHz 0.36. and shall not be distributed.6 μs 3.35. reproduced.41 . Page 79 of 115 Version: 0.2 μs 6-bit x 3 Transfers RGB Interface Setting Prohibited 12 24 48 DOTCLKS DOTCLKS DOTCLKS 8.2.

Page 80 of 115 Version: 0. i80 18-/16-bit System Bus Interface Timing (a) Write to GRAM nCS RS nRD nWR DB[17:0] Write “0022h” to index register Write GRAM “data” Nth pixel Write GRAM “data” (N+1)th pixel Write GRAM “data” (N+2)th pixel Write GRAM “data” (N+3)th pixel (b) Read from GRAM nCS RS nRD nWR DB[17:0] Write “0022h” to index register Dummy Read 1st Read “data” Nth pixel 2nd Read “data” (N+1)th pixel 3rd Read “data” (N+2)th pixel i80 9-/8-bit System Bus Interface Timing (a) Write to GRAM nCS RS nRD nWR DB[17:9] “00h” “22h” 1st write high byte 1st write low byte 2nd write high byte 2nd write low byte 3rd write high byte 3rd write low byte Nth pixel (N+1)th pixel (N+2)th pixel (b) Read from GRAM nCS RS nRD nWR DB[17:9] “00h” “22h” Dummy Read 1 Dummy Read 2 1st read high byte 1st read low byte 2nd read high byte 2nd read low byte Nth pixel (N+1)th pixel Figure31 GRAM Read/Write Timing of i80-System Interface The information contained herein is the exclusive property of ILI Technology Corp. GRAM Address Map & Read/Write ILI9320 has an internal graphics RAM (GRAM) of 87.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 9. and shall not be distributed. or disclosed in whole or in part without prior written permission of ILI Technology Corp. SPI and RGB interfaces. The GRAM can be accessed through the i80 system. reproduced.41 .120 bytes to store the display data and one pixel is constructed of 18 bits.

Page 81 of 115 Version: 0.41 . “13601h” “13701h” “13801h” “13901h” “13A01h” “13B01h” “13C01h” “13D01h” “13E01h” “13F01h” S7…S9 DB17…0 “00002h” “00102h” “00202h” “00302h” “00402h” “00502h” “00602h” “00702h” “00802h” “00902h” . . “136EDh” “137EDh” “138EDh” “139EDh” “13AEDh” “13BEDh” “13CEDh” “13DEDh” “13EEDh” “13FEDh” S523…S525 DB17…0 “000EEh” “001EEh” “002EEh” “003EEh” “004EEh” “005EEh” “006EEh” “007EEh” “008EEh” “009EEh” . . . . . and shall not be distributed. G311 G312 G313 G314 G315 G316 G317 G318 G319 G320 GS=1 G320 G319 G318 G317 G316 G315 G314 G313 G312 G311 . reproduced. “13602h” “13702h” “13802h” “13902h” “13A02h” “13B02h” “13C02h” “13D02h” “13E02h” “13F02h” S10…S12 DB17…0 “00003h” “00103h” “00203h” “00303h” “00403h” “00503h” “00603h” “00703h” “00803h” “00903h” . “13603h” “13703h” “13803h” “13903h” “13A03h” “13B03h” “13C03h” “13D03h” “13E03h” “13F03h” … … … … … … … … … … … … … … … … … … … … … … … S517…S519 DB17…0 “000ECh” “001ECh” “002ECh” “003ECh” “004ECh” “005ECh” “006ECh” “007ECh” “008ECh” “009ECh” . . G10 G9 G8 G7 G6 G5 G4 G3 G2 G1 S1…S3 DB17…0 “00000h” “00100h” “00200h” “00300h” “00400h” “00500h” “00600h” “00700h” “00800h” “00900h” . “136EEh” “137EEh” “138EEh” “139EEh” “13AEEh” “13BEEh” “13CEEh” “13DEEh” “13EEEh” “13FEEh” S526…S720 DB17…0 “000EFh” “001EFh” “002EFh” “003EFh” “004EFh” “005EFh” “006EFh” “007EFh” “008EFh” “009EFh” . . . . .a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 GRAM address map table of SS=0. “13600h” “13700h” “13800h” “13900h” “13A00h” “13B00h” “13C00h” “13D00h” “13E00h” “13F00h” S4…S6 DB17…0 “00001h” “00101h” “00201h” “00301h” “00401h” “00501h” “00601h” “00701h” “00801h” “00901h” . BGR=0 SS=0. . “136ECh” “137ECh” “138ECh” “139ECh” “13AECh” “13BECh” “13CECh” “13DECh” “13EECh” “13FECh” S520…S522 DB17…0 “000EDh” “001EDh” “002EDh” “003EDh” “004EDh” “005EDh” “006EDh” “007EDh” “008EDh” “009EDh” . “136EFh” “137EFh” “138EFh” “139EFh” “13AEFh” “13BEFh” “13CEFh” “13DEFh” “13EEFh” “13FEFh” The information contained herein is the exclusive property of ILI Technology Corp. . . or disclosed in whole or in part without prior written permission of ILI Technology Corp. . . . . BGR=0 GS=0 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 . . . .

or disclosed in whole or in part without prior written permission of ILI Technology Corp.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 i80/M68 system 18-bit data bus interface GRAM Data DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB 0 RGB Assignment Source Output Pin R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 S (3n+1) S (3n+2) S (3n+3) N=0 to 175 i80/M68 system 16-bit data bus interface GRAM Data DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 RGB Assignment Source Output Pin R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 S (3n+1) S (3n+2) S (3n+3) N=0 to 175 i80/M68 system 9-bit data bus interface 1st Transfer GRAM Data DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 DB 17 DB 16 DB 15 2nd Transfer DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 RGB Assignment Source Output Pin R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 S (3n+1) S (3n+2) S (3n+3) N=0 to 175 GRAM Data and display data of 18-/16-/9-bit system interface (SS=”0". Page 82 of 115 Version: 0. BGR=”0”) The information contained herein is the exclusive property of ILI Technology Corp.41 . BGR=”0") Figure32 i80-System Interface with 18-/16-/9-bit Data Bus (SS=”0”. and shall not be distributed. reproduced.

Page 83 of 115 Version: 0. DFM[1:0]=”10) 1st Transfer GRAM Data DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 17 DB 16 2nd Transfer DB 15 DB 14 DB 13 DB 12 DB 17 DB 16 3rd Transfer DB 15 DB 14 DB 13 DB 12 RGB Assignment Source Output Pin R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 S (3n+1) S (3n+2) S (3n+3) N=0 to 175 i80/M68 system 8-bit interface (SS=”0". or disclosed in whole or in part without prior written permission of ILI Technology Corp. BGR=”0") Figure33 i80-System Interface with 8-bit Data Bus (SS=”0”. and shall not be distributed.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 i80/M68 system 8-bit interface / SPI Interface (2 transfers/pixel) 1st transfer 2nd transfer DB 12 DB 11 DB 10 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 GRAM Data DB 17 DB 16 DB 15 DB 14 DB 13 RGB Assignment Source Output Pin R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 S (3n+1) S (3n+2) S (3n+3) N=0 to 175 i80/M68 system 8-bit interface (3 transfers/pixel. DFM[1:0]=”00") 1st Transfer 2nd Transfer DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 17 DB 16 DB 15 3rd Transfer DB 14 DB 13 DB 12 DB 11 DB 10 GRAM Data DB 11 DB 10 RGB Assignment Source Output Pin R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 S (3n+1) S (3n+2) S (3n+3) N=0 to 175 i80/M68 system 8-bit interface (3 transfers/pixel. TRI=”1".41 . reproduced. TRI=”1". BGR=”0”) The information contained herein is the exclusive property of ILI Technology Corp.

. . “13603h” “13703h” “13803h” “13903h” “13A03h” “13B03h” “13C03h” “13D03h” “13E03h” “13F03h” … … … … … … … … … … … … … … … … … … … … … … … S12…S10 DB17…0 “000ECh” “001ECh” “002ECh” “003ECh” “004ECh” “005ECh” “006ECh” “007ECh” “008ECh” “009ECh” . reproduced. . . . “136ECh” “137ECh” “138ECh” “139ECh” “13AECh” “13BECh” “13CECh” “13DECh” “13EECh” “13FECh” S9…S7 DB17…0 “000EDh” “001EDh” “002EDh” “003EDh” “004EDh” “005EDh” “006EDh” “007EDh” “008EDh” “009EDh” . .41 . “13602h” “13702h” “13802h” “13902h” “13A02h” “13B02h” “13C02h” “13D02h” “13E02h” “13F02h” S711…S709 DB17…0 “00003h” “00103h” “00203h” “00303h” “00403h” “00503h” “00603h” “00703h” “00803h” “00903h” . . . . “13600h” “13700h” “13800h” “13900h” “13A00h” “13B00h” “13C00h” “13D00h” “13E00h” “13F00h” S717…S715 DB17…0 “00001h” “00101h” “00201h” “00301h” “00401h” “00501h” “00601h” “00701h” “00801h” “00901h” . G10 G9 G8 G7 G6 G5 G4 G3 G2 G1 S720…S718 DB17…0 “00000h” “00100h” “00200h” “00300h” “00400h” “00500h” “00600h” “00700h” “00800h” “00900h” . Page 84 of 115 Version: 0. . . . and shall not be distributed. BGR=0 GS=0 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 . “136EFh” “137EFh” “138EFh” “139EFh” “13AEFh” “13BEFh” “13CEFh” “13DEFh” “13EEFh” “13FEFh” The information contained herein is the exclusive property of ILI Technology Corp. “136EDh” “137EDh” “138EDh” “139EDh” “13AEDh” “13BEDh” “13CEDh” “13DEDh” “13EEDh” “13FEDh” S6…S4 DB17…0 “000EEh” “001EEh” “002EEh” “003EEh” “004EEh” “005EEh” “006EEh” “007EEh” “008EEh” “009EEh” . . . . “136EEh” “137EEh” “138EEh” “139EEh” “13AEEh” “13BEEh” “13CEEh” “13DEEh” “13EEEh” “13FEEh” S3…S1 DB17…0 “000EFh” “001EFh” “002EFh” “003EFh” “004EFh” “005EFh” “006EFh” “007EFh” “008EFh” “009EFh” . “13601h” “13701h” “13801h” “13901h” “13A01h” “13B01h” “13C01h” “13D01h” “13E01h” “13F01h” S714…S712 DB17…0 “00002h” “00102h” “00202h” “00302h” “00402h” “00502h” “00602h” “00702h” “00802h” “00902h” . . . . . or disclosed in whole or in part without prior written permission of ILI Technology Corp. . BGR=1 SS=0.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 GRAM address map table of SS=1. G311 G312 G313 G314 G315 G316 G317 G318 G319 G320 GS=1 G320 G319 G318 G317 G316 G315 G314 G313 G312 G311 .

reproduced.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 i80/M68 system 18-bit data bus interface GRAM Data DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB 0 RGB Assignment Source Output Pin R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 S (528-3n) S (527-3n) S (526-3n) N=0 to 175 i80/M68 system 9-bit data bus interface 1st Transfer GRAM Data DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 DB 17 DB 16 DB 15 2nd Transfer DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 RGB Assignment Source Output Pin R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 S (528-3n) S (527-3n) S (526-3n) N=0 to 175 GRAM Data and display data of 18-/9-bit system interface (SS=”1". and shall not be distributed. BGR=”1”) The information contained herein is the exclusive property of ILI Technology Corp. Page 85 of 115 Version: 0.41 . BGR=”1") Figure 34 i80-System Interface with 18-/9-bit Data Bus (SS=”1”. or disclosed in whole or in part without prior written permission of ILI Technology Corp.

the GRAM address bits (RAM address set register) must be an address within the window address area. I/D = 1 (increment) AM = 0 (horizontal writing) Figure 35 GRAM Access Window Map The information contained herein is the exclusive property of ILI Technology Corp. VSA[8:0] = 4Fh. and shall not be distributed. end: VEA[8:0] bits). The window address area must be made within the GRAM address map area. or disclosed in whole or in part without prior written permission of ILI Technology Corp. The AM bit sets the transition direction of RAM address (either increment or decrement). [Window address setting area] (Horizontal direction) 00H ≤ HSA[7:0] ≤ HEA[7:0] ≤ “EF”H (Vertical direction) 00H ≤ VSA[8:0] ≤ VEA[8:0]≤ “13F”H [RAM address. These bits enable the ILI9320 to write data including image data consecutively not taking data wrap positions into account.41 . VSA[8:0] = 20h. AD (an address within a window address area)]] (RAM address) HSA[7:0] ≤ AD[7:0] ≤ HEA[7:0] VSA[8:0] ≤ AD[15:8] ≤ VEA[8:0] GRAM Address Map “00000”h “000EF”h Window Address Area 2010h 2110h 203Fh 213Fh 4F10h 4F3Fh “13F00”h “13FEF”h Window address setting area HSA[7:0] = 10h. HSA[7:0] = 3Fh.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 10. The window address area is made by setting the horizontal address register (start: HSA[7:0]. Also. Page 86 of 115 Version: 0. Window Address Function The window address function enables writing display data consecutively in a rectangular area (a window address area) made on the internal RAM. end: HEA[7:0] bits) and the vertical address register (start: VSA[8:0]. reproduced.

reproduced.41 . and shall not be distributed. or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 87 of 115 Version: 0.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 The information contained herein is the exclusive property of ILI Technology Corp.

to make ILI9320 available with liquid crystal panels of various characteristics.. Page 88 of 115 Version: 0. amplitude adjustment and fine-adjustment registers for positive and negative polarities.144 colors for the LCD panel.... Gamma Correction ILI9320 incorporates the γ-correction function to display 262.. The γ-correction is performed with 3 groups of registers determining eight reference grayscale levels. Gradient Adjustment Register VREG1OUT PRP/N0 PRP/N1 Fine Adjustment Registers (6 x 3 bits) PKP/N5 PKP/N4 PKP/N3 PKP/N2 PKP/N1 PKP/N0 Amplitude Adjustment Register VRP/N0 VRP/N1 VgP0/VgN0 V0 8 to 1 selection VgP1/VgN1 V1 V2 ….41 . V43 …. reproduced. 8 to 1 selection VgP8/VgN8 …. which are gradient adjustment..a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 11.... or disclosed in whole or in part without prior written permission of ILI Technology Corp.. and shall not be distributed. V61 V62 V63 8 to 1 selection VgP43/VgN43 8 to 1 selection VgP55/VgN55 8 to 1 selection VgP62/VgN62 VgP63/VgN63 VGS Figure 36 Grayscale Voltage Generation The information contained herein is the exclusive property of ILI Technology Corp. V55 V56 …. V7 V8 8 to 1 selection VgP20/VgN20 V20 ….

or disclosed in whole or in part without prior written permission of ILI Technology Corp. reproduced.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color VREG1OUT VROP0 0 ~ 30R 5R RP0 RP1 RP2 RP3 RP4 RP5 RP6 RP7 ILI9320 VRN0[4:0] VgN0 1uF/10V VRP0[4:0] VgP0 VRON0 0 ~ 30R 5R RN0 RN1 RN2 RN3 RN4 RN5 RN6 RN7 4R { VP1 VP2 VP3 VP4 VP5 VP6 VP7 VP8 PRP0[2:0] PKP0[2:0] VgP1 4R { VN1 VN2 VN3 VN4 VN5 VN6 VN7 VN8 PRN0[2:0] PKN0[2:0] 8 to 1 Selection 8 to 1 Selection VgN1 VRCP0 0 ~ 28R 1R 1R 1R 1R { { { { { 5R 8R RP8 RP9 RP10 RP11 RP12 RP13 RP14 RP15 RP16 RP17 RP18 RP19 RP20 RP21 RP22 RP23 RP24 RP25 RP26 RP27 RP28 RP29 RP30 RP31 RP32 RP33 RP34 RP35 RP36 RP37 RP38 VP9 VP10 VP11 VP12 VP13 VP14 VP15 VP16 VP17 VP18 VP19 VP20 VP21 VP22 VP23 VP24 VP25 VP26 VP27 VP28 VP29 VP30 VP31 VP32 VP33 VP34 VP35 VP36 VP37 VP38 VP39 VP40 PRP1[2:0] PKP1[2:0] VRCP0 0 ~ 28R VgP8 1R PKP2[2:0] VgP20 1R PKP3[2:0] VgP43 1R PKP4[2:0] VgP55 1R { { { { { 5R 8R RN8 RN9 RN10 RN11 RN12 RN13 RN14 RN15 RN16 RN17 RN18 RN19 RN20 RN21 RN22 RN23 RN24 RN25 RN26 RN27 RN28 RN29 RN30 RN31 RN32 RN33 RN34 RN35 RN36 RN37 RN38 VN9 VN10 VN11 VN12 VN13 VN14 VN15 VN16 VN17 VN18 VN19 VN20 VN21 VN22 VN23 VN24 VN25 VN26 VN27 VN28 VN29 VN30 VN31 VN32 VN33 VN34 VN35 VN36 VN37 VN38 VN39 VN40 PKN1[2:0] 8 to 1 Selection 8 to 1 Selection VgN8 PKN2[2:0] 8 to 1 Selection 8 to 1 Selection VgN20 PKN3[2:0] 8 to 1 Selection 8 to 1 Selection VgN43 PKN4[2:0] 8 to 1 Selection 8 to 1 Selection VgN55 VRCP1 0 ~ 28R RP39 RP40 RP41 RP42 RP43 RP44 RP45 RP46 4R VP41 VP42 VP43 VP44 VP45 VP46 VP47 VP48 VP49 PKP5[2:0] VRCN1 0 ~ 28R RN39 RN40 RN41 RN42 RN43 RN44 RN45 RN46 PRN1[2:0] VN41 VN42 VN43 VN44 VN45 VN46 VN47 VN48 VN49 PKN5[2:0] 8 to 1 Selection VgP62 4R 8 to 1 Selection VgN62 VgP63 VgN63 VROP1 0 ~ 31R RP47 VRP1[4:0] VRON1 0 ~ 31R RN47 VRN1[4:0] VGS Figure 37 Grayscale Voltage Adjustment The information contained herein is the exclusive property of ILI Technology Corp.41 . Page 89 of 115 Version: 0. and shall not be distributed.

fine adjustment registers adjust the reference voltage levels. VRCN0 Variable resistor VRCP1. PRP1[2:0]/PRN1[2:0]. in respective 8-to-1 selectors. or disclosed in whole or in part without prior written permission of ILI Technology Corp. Gradient adjustment registers ILI9320 The gradient adjustment registers are used to adjust the gradient of the curve representing the relationship between the grayscale and the grayscale reference voltage level. 2. the resistance values of variable resistors in the middle of the ladder resistor are adjusted by registers PRP0[2:0]/PRN0[2:0].41 . VRON1 8-to-1 selector (voltage level of grayscale 1) 8-to-1 selector (voltage level of grayscale 8) 8-to-1 selector (voltage level of grayscale 20) 8-to-1 selector (voltage level of grayscale 43) 8-to-1 selector (voltage level of grayscale 55) 8-to-1 selector (voltage level of grayscale 62) The information contained herein is the exclusive property of ILI Technology Corp. Fine adjustment registers The fine adjustment registers are used to fine-adjust grayscale voltage levels. allowing asymmetric drive. Page 90 of 115 Version: 0. the fine adjustment registers consist of positive and negative polarity registers. reproduced.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color 1. 8 levels for each register generated from the ladder resistor. VRCN1 Variable resistor VROP0. To adjust the amplitude. To fine-adjust grayscale voltage levels. The registers consist of positive and negative polarity registers. are used to adjust the amplitude of grayscale voltages. Same as the gradient registers. VRP0[4:0]/VRN0[4:0]. Grayscale voltage Grayscale voltage Gradient adjustment Amplitude adjustment Grayscale voltage Fine adjustment Figure 38 Gamma Curve Adjustment Register Groups Gradient adjustment Amplitude adjustment Fine adjustment Positive Polarity PRP0 [2:0] PRP1 [2:0] VRP0 [4:0] VRP1 [4:0] KP0 [2:0] KP1 [2:0] KP2 [2:0] KP3 [2:0] KP4 [2:0] KP5 [2:0] Negative Polarity PRN0 [2:0] PRN1 [2:0] VRN0 [4:0] VRN1 [4:0] KN0 [2:0] KN1 [2:0] KN2 [2:0] KN3 [2:0] KN4 [2:0] KN5 [2:0] Description Variable resistor VRCP0. 3. the resistance values of variable resistors at the top and bottom of the ladder resistor are adjusted. To adjust the gradient. VRON0 Variable resistor VROP1. and shall not be distributed. Same with other registers. Amplitude adjustment registers The amplitude adjustment registers. VRP1[4:0]/VRN1[4:0]. the amplitude adjustment registers consist of positive and negative polarity registers.

This unit has pins to connect a volume resistor externally to compensate differences in various characteristics of panels.41 . Fine adjustment registers and selected voltage Register Selected Voltage KP(N)[2:0] VgP(N)1 VgP(N)8 VgP(N)20 VgP(N)43 000 VP(N)1 VP(N)9 VP(N)17 VP(N)25 001 VP(N)2 VP(N)10 VP(N)18 VP(N)26 010 VP(N)3 VP(N)11 VP(N)19 VP(N)27 011 VP(N)4 VP(N)12 VP(N)20 VP(N)28 100 VP(N)5 VP(N)13 VP(N)21 VP(N)29 101 VP(N)6 VP(N)14 VP(N)22 VP(N)30 110 VP(N)7 VP(N)15 VP(N)23 VP(N)31 111 VP(N)8 VP(N)16 VP(N)24 VP(N)32 VgP(N)55 VP(N)33 VP(N)34 VP(N)35 VP(N)36 VP(N)37 VP(N)38 VP(N)39 VP(N)40 VgP(N)62 VP(N)41 VP(N)42 VP(N)43 VP(N)44 VP(N)45 VP(N)46 VP(N)47 VP(N)48 The information contained herein is the exclusive property of ILI Technology Corp. The resistance values of these variable resistors are set by gradient adjustment registers and amplitude adjustment registers as follows.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 Ladder resistors and 8-to-1 selector Block configuration The reference voltage generating block consists of two ladder resistor units including variable resistors and 8-to-1 selectors. amplitude adjustment (1) (VROP(N)0). Gradient adjustment PRP(N)0/1[2:0] VRCP(N)0 Register Resistance 000 0R 001 4R 010 8R 011 12R 100 16R 101 20R 110 24R 111 28R Amplitude adjustment (1) VRP(N)0[4:0] VROP(N)0 Register Resistance 0000 0R 0001 2R 0010 4R : : : : 1101 26R 1111 28R 1111 30R Amplitude adjustment (2) VRP(N)1[4:0] VROP(N)1 Register Resistance 00000 0R 00001 1R 00010 2R : : : : 11101 29R 11110 30R 11111 31R 8-to-1 selectors The 8-to-1 selector selects one of eight voltage levels generated from the ladder resistor unit according to the fine adjustment register and output the selected voltage level as a reference grayscale voltage (VgP(N)1~6). reproduced. Each 8-to-1 selector selects one of the 8 voltage levels generated from the ladder resistor unit to output as a grayscale reference voltage. or disclosed in whole or in part without prior written permission of ILI Technology Corp. The table below shows the setting in the fine adjustment register and the selected voltage levels for respective reference grayscale voltages. Both variable resistors and 8-to-1 selectors are controlled according to the γ-correction registers. Page 91 of 115 Version: 0. and shall not be distributed. and the amplitude adjustment (2) (VROP(N)1). Variable resistors ILI9320 uses variable resistors of the following three purposes: gradient adjustment (VRCP(N)0/VRCP(N)1).

41 . and shall not be distributed. reproduced. Formulae for calculating voltage (Positive polarity) Reference Voltage VgP0 Fine Adjustment Value –––– KP0[2:0]=000 KP0[2:0]=001 KP0[2:0]=010 KP0[2:0]=011 KP0[2:0]=100 KP0[2:0]=101 KP0[2:0]=110 KP0[2:0]=111 KP1[2:0]=000 KP1[2:0]=001 KP1[2:0]=010 KP1[2:0]=011 KP1[2:0]=100 KP1[2:0]=101 KP1[2:0]=110 KP1[2:0]=111 KP2[2:0]=000 KP2[2:0]=001 KP2[2:0]=010 KP2[2:0]=011 KP2[2:0]=100 KP2[2:0]=101 KP2[2:0]=110 KP2[2:0]=111 KP3[2:0]=000 KP3[2:0]=001 KP3[2:0]=010 KP3[2:0]=011 KP3[2:0]=100 KP3[2:0]=101 KP3[2:0]=110 KP3[2:0]=111 KP4[2:0]=000 KP4[2:0]=001 KP4[2:0]=010 KP4[2:0]=011 KP4[2:0]=100 KP4[2:0]=101 KP4[2:0]=110 KP4[2:0]=111 KP5[2:0]=000 KP5[2:0]=001 KP5[2:0]=010 KP5[2:0]=011 KP5[2:0]=100 KP5[2:0]=101 KP5[2:0]=110 KP5[2:0]=111 Formula VREG1OUT –VD*VROP0/sumRP VREG1OUT –VD*(VROP0+5R)/sumRP VREG1OUT –VD*(VROP0+9R)/sumRP VREG1OUT –VD*(VROP0+13R)/sumRP VREG1OUT –VD*(VROP0+17R)/sumRP VREG1OUT –VD*(VROP0+21R)/sumRP VREG1OUT –VD*(VROP0+25R)/sumRP VREG1OUT –VD*(VROP0+29R)/sumRP VREG1OUT –VD*(VROP0+33R)/sumRP VREG1OUT –VD*(VROP0+33R+VRCP0)/sumRP VREG1OUT –VD*(VROP0+34R+VRCP0)/sumRP VREG1OUT –VD*(VROP0+35R+VRCP0)/sumRP VREG1OUT –VD*(VROP0+36R+VRCP0)/sumRP VREG1OUT –VD*(VROP0+37R+VRCP0)/sumRP VREG1OUT –VD*(VROP0+38R+VRCP0)/sumRP VREG1OUT –VD*(VROP0+39R+VRCP0)/sumRP VREG1OUT –VD*(VROP0+40R+VRCP0)/sumRP VREG1OUT –VD*(VROP0+45R+VRCP0)/sumRP VREG1OUT –VD*(VROP0+46R+VRCP0)/sumRP VREG1OUT –VD*(VROP0+47R+VRCP0)/sumRP VREG1OUT –VD*(VROP0+48R+VRCP0)/sumRP VREG1OUT –VD*(VROP0+49R+VRCP0)/sumRP VREG1OUT –VD*(VROP0+50R+VRCP0)/sumRP VREG1OUT –VD*(VROP0+51R+VRCP0)/sumRP VREG1OUT –VD*(VROP0+52R+VRCP0)/sumRP VREG1OUT –VD*(VROP0+68R+VRCP0)/sumRP VREG1OUT –VD*(VROP0+69R+VRCP0)/sumRP VREG1OUT –VD*(VROP0+70R+VRCP0)/sumRP VREG1OUT –VD*(VROP0+71R+VRCP0)/sumRP VREG1OUT –VD*(VROP0+72R+VRCP0)/sumRP VREG1OUT –VD*(VROP0+73R+VRCP0)/sumRP VREG1OUT –VD*(VROP0+74R+VRCP0)/sumRP VREG1OUT –VD*(VROP0+75R+VRCP0)/sumRP VREG1OUT –VD*(VROP0+80R+VRCP0)/sumRP VREG1OUT –VD*(VROP0+81R+VRCP0)/sumRP VREG1OUT –VD*(VROP0+82R+VRCP0)/sumRP VREG1OUT –VD*(VROP0+83R+VRCP0)/sumRP VREG1OUT –VD*(VROP0+84R+VRCP0)/sumRP VREG1OUT –VD*(VROP0+85R+VRCP0)/sumRP VREG1OUT –VD*(VROP0+86R+VRCP0)/sumRP VREG1OUT –VD*(VROP0+87R+VRCP0)/sumRP VREG1OUT –VD*(VROP0+87R+VRCP0+VRCP1)/sumRP VREG1OUT –VD*(VROP0+91R+VRCP0+VRCP1)/sumRP VREG1OUT –VD*(VROP0+95R+VRCP0+VRCP1)/sumRP VREG1OUT –VD*(VROP0+99R+VRCP0+VRCP1)/sumRP VREG1OUT –VD*(VROP0+103R+VRCP0+VRCP1)/sumRP VREG1OUT –VD*(VROP0+107R+VRCP0+VRCP1)/sumRP VREG1OUT –VD*(VROP0+111R+VRCP0+VRCP1)/sumRP VREG1OUT –VD*(VROP0+115R+VRCP0+VRCP1)/sumRP Vout VP0 VP1 VP2 VP3 VP4 VP5 VP6 VP7 VP8 VP9 VP10 VP11 VP12 VP13 VP14 VP15 VP16 VP17 VP18 VP19 VP20 VP21 VP22 VP23 VP24 VP25 VP26 VP27 VP28 VP29 VP30 VP31 VP32 VP33 VP34 VP35 VP36 VP37 VP38 VP39 VP40 VP41 VP42 VP43 VP44 VP45 VP46 VP47 VP48 VgP1 VgP8 VgP20 VgP43 VgP55 VgP62 The information contained herein is the exclusive property of ILI Technology Corp. or disclosed in whole or in part without prior written permission of ILI Technology Corp.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 The grayscale voltage levels for V0~V63 grayscales are calculated from the following formulae. Page 92 of 115 Version: 0.

and shall not be distributed.41 . Page 93 of 115 Version: 0. DDVDH – V0 > 0.1V V55 – AGND > 1. reproduced.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color VgP63 –––– ILI9320 VP49 VREG1OUT –VD*(VROP0+120R+VRCP0+VRCP1)/sumRP Sum of positive resistor sumRP = 128R + VROP0 + VROP1 + VRCP0 + VRCP1 Sum of negative resistor sumRN = 128R + VRON0 + VRON1 + VRCN0 + VRCN1 Voltage difference VD = (VREG1OUT – VGS) Formulae for calculating voltage (Positive polarity) Grayscale Voltage V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 V23 V24 V25 V26 V27 V28 V29 V30 V31 Formula VgP0 VgP1 V3+(V1–V3)*(8/24) V8+(V1–V8)*(450/800) V8+(V3–V8)*(16/24) V8+(V3–V8)*(12/24) V8+(V3–V8)*(8/24) V8+(V3–V8)*(4/24) VgP8 V20+(V8–V20)*(22/24) V20+(V8–V20)*(20/24) V20+(V8–V20)*(18/24) V20+(V8–V20)*(16/24) V20+(V8–V20)*(14/24) V20+(V8–V20)*(12/24) V20+(V8–V20)*(10/24) V20+(V8–V20)*(8/24) V20+(V8–V20)*(6/24) V20+(V8–V20)*(4/24) V20+(V8–V20)*(2/24) VgP20 V43+(V20–V43)*(22/23) V43+(V20–V43)*(21/23) V43+(V20–V43)*(20/23) V43+(V20–V43)*(19/23) V43+(V20–V43)*(18/23) V43+(V20–V43)*(17/23) V43+(V20–V43)*(16/23) V43+(V20–V43)*(15/23) V43+(V20–V43)*(14/23) V43+(V20–V43)*(13/23) V43+(V20–V43)*(12/23) Grayscale Voltage V32 V33 V34 V35 V36 V37 V38 V39 V40 V41 V42 V43 V44 V45 V46 V47 V48 V49 V50 V51 V52 V53 V54 V55 V56 V57 V58 V59 V60 V61 V62 V63 Formula V43+(V20–V43)*(11/23) V43+(V20–V43)*(10/23) V43+(V20–V43)*(9/23) V43+(V20–V43)*(8/23) V43+(V20–V43)*(7/23) V43+(V20–V43)*(6/23) V43+(V20–V43)*(5/23) V43+(V20–V43)*(4/23) V43+(V20–V43)*(3/23) V43+(V20–V43)*(2/23) V43+(V20–V43)*(1/23) VgP43 V55+(V43–V55)*(22/24) V55+(V43–V55)*(20/24) V55+(V43–V55)*(18/24) V55+(V43–V55)*(16/24) V55+(V43–V55)*(14/24) V55+(V43–V55)*(12/24) V55+(V43–V55)*(10/24) V55+(V43–V55)*(8/24) V55+(V43–V55)*(6/24) V55+(V43–V55)*(4/24) V55+(V43–V55)*(2/24) VgP55 V60+(V55–V60)*(20/24) V60+(V55–V60)*(16/24) V60+(V55–V60)*(12/24) V60+(V55–V60)*(8/24) V62+(V55–V62)*(350/800) V62+(V60–V62)*(16/24) VgP62 VgP63 Note: The following condition shall be always retained.5V DDVDH – V8 > 1. or disclosed in whole or in part without prior written permission of ILI Technology Corp.1V The information contained herein is the exclusive property of ILI Technology Corp.

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color Formulae for calculating voltage (Negative polarity) Reference Voltage VgN0 Fine Adjustment Value –––– KN0[2:0]=000 KN0[2:0]=001 KN0[2:0]=010 KN0[2:0]=011 KN0[2:0]=100 KN0[2:0]=101 KN0[2:0]=110 KN0[2:0]=111 KN1[2:0]=000 KN1[2:0]=001 KN1[2:0]=010 KN1[2:0]=011 KN1[2:0]=100 KN1[2:0]=101 KN1[2:0]=110 KN1[2:0]=111 KN2[2:0]=000 KN2[2:0]=001 KN2[2:0]=010 KN2[2:0]=011 KN2[2:0]=100 KN2[2:0]=101 KN2[2:0]=110 KN2[2:0]=111 KN3[2:0]=000 KN3[2:0]=001 KN3[2:0]=010 KN3[2:0]=011 KN3[2:0]=100 KN3[2:0]=101 KN3[2:0]=110 KN3[2:0]=111 KN4[2:0]=000 KN4[2:0]=001 KN4[2:0]=010 KN4[2:0]=011 KN4[2:0]=100 KN4[2:0]=101 KN4[2:0]=110 KN4[2:0]=111 KN5[2:0]=000 KN5[2:0]=001 KN5[2:0]=010 KN5[2:0]=011 KN5[2:0]=100 KN5[2:0]=101 KN5[2:0]=110 KN5[2:0]=111 –––– Formula ILI9320 Vout VN0 VN1 VN2 VN3 VN4 VN5 VN6 VN7 VN8 VN9 VN10 VN11 VN12 VN13 VN14 VN15 VN16 VN17 VN18 VN19 VN20 VN21 VN22 VN23 VN24 VN25 VN26 VN27 VN28 VN29 VN30 VN31 VN32 VN33 VN34 VN35 VN36 VN37 VN38 VN39 VN40 VN41 VN42 VN43 VN44 VN45 VN46 VN47 VN48 VN49 VgN1 VgN8 VgN20 VgN43 VgN55 VgN62 VgN63 VREG1OUT –VD*VRON0/sumRN VREG1OUT –VD*(VRON0+5R)/sumRN VREG1OUT –VD*(VRON0+9R)/sumRN VREG1OUT –VD*(VRON0+13R)/sumRN VREG1OUT –VD*(VRON0+17R)/sumRN VREG1OUT –VD*(VRON0+21R)/sumRN VREG1OUT –VD*(VRON0+25R)/sumRN VREG1OUT –VD*(VRON0+29R)/sumRN VREG1OUT –VD*(VRON0+33R)/sumRN VREG1OUT –VD*(VRON0+33R+VRCN0)/sumRN VREG1OUT –VD*(VRON0+34R+VRCN0)/sumRN VREG1OUT –VD*(VRON0+35R+VRCN0)/sumRN VREG1OUT –VD*(VRON0+36R+VRCN0)/sumRN VREG1OUT –VD*(VRON0+37R+VRCN0)/sumRN VREG1OUT –VD*(VRON0+38R+VRCN0)/sumRN VREG1OUT –VD*(VRON0+39R+VRCN0)/sumRN VREG1OUT –VD*(VRON0+40R+VRCN0)/sumRN VREG1OUT –VD*(VRON0+45R+VRCN0)/sumRN VREG1OUT –VD*(VRON0+46R+VRCN0)/sumRN VREG1OUT –VD*(VRON0+47R+VRCN0)/sumRN VREG1OUT –VD*(VRON0+48R+VRCN0)/sumRN VREG1OUT –VD*(VRON0+49R+VRCN0)/sumRN VREG1OUT –VD*(VRON0+50R+VRCN0)/sumRN VREG1OUT –VD*(VRON0+51R+VRCN0)/sumRN VREG1OUT –VD*(VRON0+52R+VRCN0)/sumRN VREG1OUT –VD*(VRON0+68R+VRCN0)/sumRN VREG1OUT –VD*(VRON0+69R+VRCN0)/sumRN VREG1OUT –VD*(VRON0+70R+VRCN0)/sumRN VREG1OUT –VD*(VRON0+71R+VRCN0)/sumRN VREG1OUT –VD*(VRON0+72R+VRCN0)/sumRN VREG1OUT –VD*(VRON0+73R+VRCN0)/sumRN VREG1OUT –VD*(VRON0+74R+VRCN0)/sumRN VREG1OUT –VD*(VRON0+75R+VRCN0)/sumRN VREG1OUT –VD*(VRON0+80R+VRCN0)/sumRN VREG1OUT –VD*(VRON0+81R+VRCN0)/sumRN VREG1OUT –VD*(VRON0+82R+VRCN0)/sumRN VREG1OUT –VD*(VRON0+83R+VRCN0)/sumRN VREG1OUT –VD*(VRON0+84R+VRCN0)/sumRN VREG1OUT –VD*(VRON0+85R+VRCN0)/sumRN VREG1OUT –VD*(VRON0+86R+VRCN0)/sumRN VREG1OUT –VD*(VRON0+87R+VRCN0)/sumRN VREG1OUT –VD*(VRON0+87R+VRCN0+VRCN1)/sumRN VREG1OUT –VD*(VRON0+91R+VRCN0+VRCN1)/sumRN VREG1OUT –VD*(VRON0+95R+VRCN0+VRCN1)/sumRN VREG1OUT –VD*(VRON0+99R+VRCN0+VRCN1)/sumRN VREG1OUT –VD*(VRON0+103R+VRCN0+VRCN1)/sumRN VREG1OUT –VD*(VRON0+107R+VRCN0+VRCN1)/sumRN VREG1OUT –VD*(VRON0+111R+VRCN0+VRCN1)/sumRN VREG1OUT –VD*(VRON0+115R+VRCN0+VRCN1)/sumRN VREG1OUT –VD*(VRON0+120R+VRCN0+VRCN1)/sumRN Sum of positive resistor sumRP = 128R + VROP0 + VROP1 + VRCP0 + VRCP1 The information contained herein is the exclusive property of ILI Technology Corp. or disclosed in whole or in part without prior written permission of ILI Technology Corp. reproduced.41 . Page 94 of 115 Version: 0. and shall not be distributed.

41 . and shall not be distributed. Page 95 of 115 Version: 0.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color Sum of negative resistor sumRN = 128R + VRON0 + VRON1 + VRCN0 + VRCN1 Voltage difference VD = (VREG1OUT – VGS) Grayscale Voltage V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 V23 V24 V25 V26 V27 V28 V29 V30 V31 Formula VgN0 VgN1 V3+(V1–V3)*(8/24) V8+(V1–V8)*(450/800) V8+(V3–V8)*(16/24) V8+(V3–V8)*(12/24) V8+(V3–V8)*(8/24) V8+(V3–V8)*(4/24) VgN8 V20+(V8–V20)*(22/24) V20+(V8–V20)*(20/24) V20+(V8–V20)*(18/24) V20+(V8–V20)*(16/24) V20+(V8–V20)*(14/24) V20+(V8–V20)*(12/24) V20+(V8–V20)*(10/24) V20+(V8–V20)*(8/24) V20+(V8–V20)*(6/24) V20+(V8–V20)*(4/24) V20+(V8–V20)*(2/24) VgN20 V43+(V20–V43)*(22/23) V43+(V20–V43)*(21/23) V43+(V20–V43)*(20/23) V43+(V20–V43)*(19/23) V43+(V20–V43)*(18/23) V43+(V20–V43)*(17/23) V43+(V20–V43)*(16/23) V43+(V20–V43)*(15/23) V43+(V20–V43)*(14/23) V43+(V20–V43)*(13/23) V43+(V20–V43)*(12/23) Grayscale Voltage V32 V33 V34 V35 V36 V37 V38 V39 V40 V41 V42 V43 V44 V45 V46 V47 V48 V49 V50 V51 V52 V53 V54 V55 V56 V57 V58 V59 V60 V61 V62 V63 ILI9320 Formula V43+(V20–V43)*(11/23) V43+(V20–V43)*(10/23) V43+(V20–V43)*(9/23) V43+(V20–V43)*(8/23) V43+(V20–V43)*(7/23) V43+(V20–V43)*(6/23) V43+(V20–V43)*(5/23) V43+(V20–V43)*(4/23) V43+(V20–V43)*(3/23) V43+(V20–V43)*(2/23) V43+(V20–V43)*(1/23) VgN43 V55+(V43–V55)*(22/24) V55+(V43–V55)*(20/24) V55+(V43–V55)*(18/24) V55+(V43–V55)*(16/24) V55+(V43–V55)*(14/24) V55+(V43–V55)*(12/24) V55+(V43–V55)*(10/24) V55+(V43–V55)*(8/24) V55+(V43–V55)*(6/24) V55+(V43–V55)*(4/24) V55+(V43–V55)*(2/24) VgN55 V60+(V55–V60)*(20/24) V60+(V55–V60)*(16/24) V60+(V55–V60)*(12/24) V60+(V55–V60)*(8/24) V62+(V55–V62)*(350/800) V62+(V60–V62)*(16/24) VgN62 VgN63 Relationship between RAM data and voltage output levels (REV = “0”) The information contained herein is the exclusive property of ILI Technology Corp. reproduced. or disclosed in whole or in part without prior written permission of ILI Technology Corp.

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 Source Driver Output (S[384:1]) VCOM Negative polarity Postive polarity Figure 39 Relationship between Source Output and VCOM V0 Negative Polarity Source Output Levels Positive Polarity V63 000000 GRAM Data 111111 Figure 40 Relationship between GRAM Data and Output Level The information contained herein is the exclusive property of ILI Technology Corp. reproduced. or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 96 of 115 Version: 0.41 . and shall not be distributed.

41 .1.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 12. and shall not be distributed. reproduced. Page 97 of 115 Version: 0. Application 12. Configuration of Power Supply Circuit The information contained herein is the exclusive property of ILI Technology Corp. or disclosed in whole or in part without prior written permission of ILI Technology Corp.

………………………………………………………………………………………………...a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 (1-a) VPP1 VPP2 VPP3 < 25 ohm < 25 ohm < 25 ohm DUMMYR1 DUMMYR2 TESTO1 VCCDUM1 VPP1 VPP1 VPP1 VPP2 VPP2 VPP2 VPP2 VPP2 VPP3 VPP3 VPP3 TESTO2 IOGNDDUM1 TESTO3 TEST1 TEST2 TEST4 TEST5 TEST3 IM0/ID IM1 IM2 IM3 TESTO4 IOVCCDUM1 TESTO5 nRESET VSYNC HSYNC DOTCLK ENABLE DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 TESTO6 IOGNDDUM2 TESTO7 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 SDO SDI nRD nWR/SCL RS nCS TESTO8 IOVCCDUM2 TESTO9 FMARK TS8 TS7 TS6 TS5 TS4 TS3 TS2 TS1 TS0 TSC TESTO10 IOGNDDUM3 TESTO11 TESTO12 TESTO38 TESTO37 DUMMYR10 DUMMYR9 VGLDMY4 G2 G4 G6 G8 G10 IOVCC IM1 IM3 nRESET HSYNC ENABLE DB16 DB14 DB12 DB10 DB8 DB7 DB5 DB3 DB1 SDO nRD RS FLM IM0 IM2 < 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm VSYNC DOTCLK DB17 DB15 DB13 DB11 DB9 ………………………..3V 1uF/6. TESTO35 S1 S2 S3 S4 S5 S6 S7 S8 S9 1 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 Face Up (Bump View) 1 1 0 1 2 0 1 3 0 1 4 0 1 5 0 1 6 0 1 7 0 1 8 0 1 9 0 2 0 0 2 1 0 2 2 0 2 3 0 2 4 0 2 5 0 2 6 0 2 7 0 2 8 0 2 9 0 2 9 8 Y X Version: 0.. or disclosed in whole or in part without prior written permission of ILI Technology Corp.3V < 5 ohm < 100 ohm S712 S713 S714 S715 S716 S717 S718 S719 S720 TESTO34 VCC < 5 ohm 220um 1uF/10V < 15 ohm TESTO33 VGLDMY2 G319 G317 G315 G313 G311 < 15 ohm 1uF/10V < 15 ohm ……………………………………………………………………………………….3V < 5 ohm < 5 ohm < 5 ohm GND GND GND GND GND GND GND GND GND GND TESTO17 VTEST TESTO18 VGS TESTO19 V0T TESTO20 VMON TESTO21 V31T VCOM VCOM VCOM VCOM VCOM VCOM VCOMH VCOMH VCOMH VCOMH VCOMH VCOMH VCOML VCOML VCOML VCOML VCOML VCOML TESTO22 TESTO23 VREG1OUT TESTO24 TESTA5 TESTO25 VCOMR TESTO26 VCL VCL VCL VLOUT1 VLOUT1 VLOUT1 DDVDH DDVDH DDVDH DDVDH DDVDH DDVDH DDVDH VCIOUT VCIOUT VCIOUT VCI1 VCI1 VCI1 VCI1 VCI1 VCILVL VCI VCI VCI VCI VCI VCI VCI VCI C12C12C12C12C12C12+ C12+ C12+ C12+ C12+ C11C11C11C11C11C11+ C11+ C11+ C11+ C11+ AGNDDUM1 VLOUT3 VLOUT3 VGL VGL VGL VGL VGL VGL VGL VGL VGL VGL AGNDDUM2 AGNDDUM3 AGNDDUM4 VLOUT2 VLOUT2 VGH VGH VGH VGH TESTO27 C13C13C13TESTO28 C13+ C13+ C13+ TESTO29 C21C21C21C21+ C21+ C21+ C22C22C22C22+ C22+ C22+ C23C23C23C23+ C23+ C23+ TESTO30 DUMMYR5 DUMMYR6 < 100 ohm < 10 ohm 1uF/6. ……………………….3V 1uF/6. and shall not be distributed.. reproduced.. G312 G314 G316 G318 G320 VGLDMY3 TESTO36 DB6 DB4 DB2 DB0 SDI nWR nCS 220um 150K ohm < 100 ohm < 100 ohm OSC1DUM1 OSC1DUM2 OSC1 OSC1DUM3 OSC1DUM4 OSC2 OSC2DUM1 OSC2DUM2 DUMMYR3 DUMMYR4 IOGND IOGND IOGND IOGND IOGND IOGND IOGND IOVCC IOVCC IOVCC IOVCC IOVCC IOVCC IOVCC VCC VCC VCC VCC VCC VCC VCC VCC VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD TESTO13 VREFD TESTO14 VREF TESTO15 VREFC TESTO16 VDDTEST AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND GND GND GND GND GND GND < 10 ohm IOVCC < 10 ohm VCC < 5 ohm 1uF/6. (1-b) G9 G7 G5 G3 G1 VGLDMY1 DUMMYR8 DUMMYR7 TESTO32 TESTO31 Page 98 of 115 ………………………………………………………………………………………. < 15 ohm 1uF/25V < 10 ohm Vci 1uF/25V 1uF/10V < 20 ohm < 20 ohm < 20 ohm 1uF/10V < 20 ohm < 20 ohm 1uF/10V 1uF/10V < 20 ohm < 20 ohm < 20 ohm < 20 ohm The information contained herein is the exclusive property of ILI Technology Corp.3V < 5 ohm 1uF/6.41 .3V < 10 ohm < 10 ohm < 50 ohm < 50 ohm < 25 ohm 1uF/6.3V 1uF/6. ……………………………………………………………………………………………….

(Vci – VGH). Page 99 of 115 Version: 0. and shall not be distributed. C22+/- VGH. C21+/-.41 . VCOMH. Capacity 1 µF (B characteristics) VCOML. VDD. or disclosed in whole or in part without prior written permission of ILI Technology Corp. C11+/-. VCL. C12+/DDVDH.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color Figure 41 Power Supply Circuit Block ILI9320 The following table shows specifications of external elements connected to the ILI9320’s power supply circuit. VR ≥30V (Recommended diode: HSC226) Variable resistor > 200 kΩ VREG1OUT. reproduced. (Vci – DDVDH) VCOMR The information contained herein is the exclusive property of ILI Technology Corp. Pin connection VCI1. VGL (AGND – VGL). Items Recommended Specification 6V 10V 25V Schottky diode VF<0.4V/20mA at 25°C.

and shall not be distributed.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 12. Display ON/OFF Sequence Display Off Flow Set EQ = 0 Display On Flow Power Setting Display OFF GON = 1 DTE = 1 D[1:0] = 10 Set SAP[2:0] Display On GON = 0 DTE = 0 D[1:0] = 01 Wait for 2 frames or more Wait for 2 frames or more Display OFF GON = 1 DTE = 0 D[1:0] = 10 Display On GON = 1 DTE = 0 D[1:0] = 01 Wait for 2 frames or more Display On GON = 1 DTE = 0 D[1:0] = 11 Display OFF GON = 0 DTE = 0 D[1:0] = 00 Wait for 2 frames or more Display Supply Off SAP[2:0] = 000 AP[2:0] = 000 PON = 0 VCOMG=0 Display On GON = 1 DTE = 1 D[1:0] = 11 Display Off Display ON Figure 42 Display On/Off Register Setting Sequence The information contained herein is the exclusive property of ILI Technology Corp. or disclosed in whole or in part without prior written permission of ILI Technology Corp.41 . reproduced.2. Page 100 of 115 Version: 0.

and shall not be distributed. reproduced.41 . Standby and Sleep Mode Standby Display Off Sequence Sleep Display Off Sequence Set Standby (STB = 1) Set Sleep (SLP = 1) Start Oscillation Release from Sleep (SLP = 0) Release from Sleep Wait for 10 ms Release from standby Power Supply Seeting Release from Standby (STB = 0) Display On Sequence Power Supply Seeting Display On Sequence Figure 43 Standby/Sleep Mode Register Setting Sequence The information contained herein is the exclusive property of ILI Technology Corp. Page 101 of 115 Version: 0.3.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 12. or disclosed in whole or in part without prior written permission of ILI Technology Corp.

VCI. VRH[3:0].4. PON=0. VCI. The setting time for oscillators. VCI Simultaneously Display OFF Setting Display OFF Sequence 1ms or more Power On Reset and Display OFF 10ms or more Oscillator Stabilizing time LCD Power Supply ON Sequence Registers setting before power supply startup Registers setting for power supply startup (1) 40ms or more Step-up circuit stabilizing time Registers setting for power supply startup (2) Operational Amplifier stabilizing time DTE = 0 D[1:0] = 00 GON = 0 PON = 0 VCOMG = 0 Display OFF Power supply initial setting Set VC[2:0].a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 12. and shall not be distributed.0]. reproduced. IOVCC) VCI IOVCC VCC GND VCC or VCI Power supply operation setting (2) Set BT[2:0] DK=0 VCOMG=1 IOVCC VCC. IOVCC. IOVCC) VCC IOVCC VCI GND VCI or Normal Display Display ON Setting DTE=1 D[1:0]=11 GON=1 VCC IOVCC VCC. Power Supply ON (VCC. or disclosed in whole or in part without prior written permission of ILI Technology Corp. VCI Simultaneously Power OFF Sequence Set the other registers Display ON Sequence Set SAP[2:0] Display ON Power ON Sequence DTE=1 D[1:0]=11 GON=1 Figure 44 Power Supply ON/OFF Sequence The information contained herein is the exclusive property of ILI Technology Corp. step-up circuits and operational amplifiers depends on external resistance and capacitance. VCM[4. Page 102 of 115 Version: 0.41 . follow the sequence below. Power Supply Configuration When supplying and cutting off power. IOVCC. DC0[2:0] PON = 1 Set AP[2:0] Power Supply OFF (VCC. DK=1 Power Supply Halt Setting SAP[2:0] = 000 AP[2:0] = 000 PON = 0 VCOMG = 0 Power supply operation setting (1) BT[2:0] = 000 Set DC1[2:0]. VDV[4:0].

In this case.5) ~ -1V ) VCOMG BT VCL VGL VCL (0 ~ -3.3V) VC REGP.5V) VGAM1OUT (3. The voltage levels in the following relationships (DDVDH – VREG1OUT ) > 0.5V) DDVDH VRH VCM/VcomR VLCD (4. and VCL output voltage levels are lower than their theoretical levels (ideal voltage levels) due to current consumption at respective outputs. and shall not be distributed. VCI1 VDV VCOMH (3. Voltage Generation The pattern diagram for setting the voltages and the waveforms of the voltages of the ILI9320 are as follows. The information contained herein is the exclusive property of ILI Technology Corp.5)V ) Vci VciLVL (2. VGH.5.5 ~ 5. current consumption is large. check the voltage before use.3V) VGL (-4.5)V ) VCOML (VCL+0. (VCOML1 – VCL) > 0.5V) Figure 45 Voltage Configuration Diagram Note: The DDVDH. (VCOML2 – VCL) > 0.0 ~ -16.5 ~ 3. or disclosed in whole or in part without prior written permission of ILI Technology Corp. When the alternating cycles of VCOM are set high (e.g. VGL. the polarity inverts every line cycle).5V. BT VGH VGH (+9 ~ 16.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 12.41 . reproduced.0 ~ (VLCD-0.0 ~ (VLCD-0.5V.5V are the actual voltage levels. Page 103 of 115 Version: 0.

wiring distance. For example. placing a Rosc resistor of larger resistance value or lower the supply voltage level will generate a lower oscillation frequency. External Input Clock Example. See the “Notes to Electrical Characteristics” section for the relationship between resistance value of Rosc resistor and oscillation frequency. Page 104 of 115 Version: 0. The oscillation frequency varies with resistance value of external resistor.7. Internal RC Oscillator Example External Clock OSC1 Damping Resistor (2K ohm) OSC1 Rosc Rosc shall be placed as close to OSC1 and AGND as possible.41 . and operating supply voltage. Applied Voltage to the TFT panel VGH Gate Output VCOM Source output VGL Figure 46 Voltage Output to TFT LCD Panel 12.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 12. AGND AGND Figure 47 Oscillation Connection The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed. reproduced.6. Oscillator ILI9320 generates oscillation with the ILI9320’s internal RC oscillators by placing an external resistor between the OSC1 and OSC2 pins. or disclosed in whole or in part without prior written permission of ILI Technology Corp.

9. Partial Display Function The ILI9320 allows selectively driving two partial images on the screen at arbitrary positions set in the screen drive position registers. To switch frame frequencies between when displaying a moving picture and when displaying a still picture. RTN bits) without changing the oscillation frequency. : frequency if RC oscillation.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 12. The following example shows the setting for partial display function: Base Image Display Setting BASEE NL[5:0] 0 6’h27 The information contained herein is the exclusive property of ILI Technology Corp.56kHz. Formula to calculate frame frequency Formula rate = fosc. Clock cycles per line : RTN bits Division ratio : DIV bits Lines : number of lines for driving the LCD panel. Clock cycles per line x division ratio x (Lines +BP+FP) fosc. Adjust the external resistor of the RC oscillator to 322. reproduced. and shall not be distributed. the RC oscillation frequency is 322. 12. By doing so. Back porch lines Example of Calculation: when maximum frame frequency = 60 Hz Number of lines to drive the LCD: 320 lines 1H period: 16 clock cycle (RTNI[4:0] = “00000”) Operational clock division ratio: 1/1 fosc = 60 Hz × (0 + 16) clock × 1/1 × (320 + 16) lines = 322. The frame frequency for driving LCDs can be adjusted by registers (using the DIV.56 (kHz) In this case. FP: Front porch lines BP. Page 105 of 115 Version: 0.8. it becomes possible to set a low frame frequency when displaying a still picture for saving power consumption and to set a high frame frequency when displaying a moving picture. The frame frequency is adjusted by register using the 1H period adjustment bits (RTN bits) and the operation clock division bits (DIV bits).56kHz. Frame Rate Adjustment The ILI9320 has a frame frequency adjustment function. Relationship between Liquid Crystal Drive Duty and Frame Frequency The relationship between the liquid crystal drive duty and the frame frequency is calculated from the following formula. or disclosed in whole or in part without prior written permission of ILI Technology Corp. set a high oscillation frequency in advance.41 .

41 . The The information contained herein is the exclusive property of ILI Technology Corp. or disclosed in whole or in part without prior written permission of ILI Technology Corp. x1/4).a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color Partial Image 1 Display Setting PTDE0 PTSA0[8:0] PTEA0[8:0] PTDP0[8:0] 1 9’h000 9’h00F 9’h080 Partial Image 2 Display Setting PTDE1 PTSA1[8:0] PTEA1[8:0] PTDP1[8:0] 1 9’h020 9’h02F 9’h0C0 ILI9320 PTSA0=9'h000 GRAM MAP Partial Image 1 GRAM Area LCD Panel 0 (1st line) 1 (2nd line) 2 (3rd line) PTEA0=9'h00F PTSA1=9'h020 Partial Image 2 GRAM Area PTEA1=9'h02F Partial Image 1 Display Area PTDP0=9'h080 PTDP1=9'h0C0 Partial Image 1 Display Area 319 (320th line) Figure 48 Partial Display Example 12. which is performed when writing image data to GRAM. Page 106 of 115 Version: 0.10. and shall not be distributed. reproduced. Resizing Function ILI9320 supports resizing function (x1/2.

1) (5.4) (4.1) (4.2) (5.3) (6. Original Image Data 0 0 1 2 3 4 5 6 (0.2) (1.3) (1.2) (6.5) (5.3) 4 (0.0) (0.6) (2.6) (2.6) (4.0) (3.5) (3.2) (2.2) (0. x1/4) of image.2) 3 (0.3) (3.1) (1.6) (3.0) (2.4) (0.6) (6.6) (1.0) ? resizing Figure 49 Data transfer in resizing Original Data 240 Panel Display 120 RSZ=2'h1 320 160 Write to GRAM Figure 50 Resizing Example Resized Image Resolution 1/2 (RSZ=2’h1) 1/4 (RSZ=2’h3) 320 × 240 160 × 120 176 × 144 88 × 72 160 × 120 80× 60 88 × 72 44× 36 60× 80 30 × 40 66 × 66 33 × 33 Original Image Size (X × Y) 640 × 480 352 × 288 320 × 240 176 × 144 120 × 160 132 × 132 The information contained herein is the exclusive property of ILI Technology Corp.0) (6.0) (4.0) (1.5) (2.4) (3.0) (6.1) (3. or disclosed in whole or in part without prior written permission of ILI Technology Corp.2) (3.4) 6 (0. The resizing function allows the system to transfer the original-size image data into the GRAM with resized image data.6) (2. and shall not be distributed.41 .0) (5.2) (6.1) 2 (0.4) (2.5) (4.2) (2.4) (5.0) (4.6) (5.4) (6.5) 1 (0.3) (5.0) GRAM Data 5 (0.5) (6. reproduced.2) (4.6) (0.3) (4. Page 107 of 115 Version: 0.4) (6.4) (1.2) (4.4) (2.1) (6.3) (2.6) (4.1) (2.6) (6.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 resizing function is enabled by setting a window address area and the RSZ bit which represents the resizing factor (x1/2.4) (4.5) (1.

reproduced. Y0) dx Y Original Image Size dy (X0+dx-1. X GRAM Address dx= (X-H)/N. or disclosed in whole or in part without prior written permission of ILI Technology Corp. and shall not be distributed. H=X mod N dy= (Y-V)/N. V=Y mod N (X0. The following example show the resizing setting. y0) x0 x0+dx-1 y0 y0+dy-1 The information contained herein is the exclusive property of ILI Technology Corp. Page 108 of 115 Version: 0. the GRAM window address area must fit the size of resized image. Y0+dy-1) Original image data number in horizontal direction Original image data number in Vertical direction Resizing Ration Resizing Setting Remainder pixels in horizontal direction Remainder pixels in vertical direction GRAM writing start address RSZ RCH RCV AD HSA GRAM window setting HEA VSA VEA X Y 1/N N-1 H V (x0.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 The RSZ bit sets the resizing factor of an image.41 . When setting a window address area in the internal GRAM.

3 ~ + 4. the ILI9320 may be permanently damaged.3 ~ + 6. 5.AGND V Power supply voltage (1) AGND .3 ~ + 18. Electrical Characteristics 13. (High) (VCC = VCC) ≥ DGND (Low). Absolute Maximum Ratings The absolute maximum rating is listed on following table. Make sure (High) DDVDH ≥ VCL (Low). 4. To use the ILI9320 within the following electrical characteristics limit is strongly recommended for normal operation. Make sure (High) VCI ≥ DGND (Low).3 ~ VCC+ 0. the ILI9320 will malfunction and cause poor reliability. This temperature specifications apply to the TCP package Value -0. Make sure (High) DDVDH ≥ ASSD (Low). 9 8. 5 1. 4 1 1.0 -0. and shall not be distributed. IOVCC V Power supply voltage (1) VCI .AGND V Power supply voltage (1) AGND -VCL V Power supply voltage (1) DDVDH . Make sure (High) VGH ≥ ASSD (Low). 9 The information contained herein is the exclusive property of ILI Technology Corp. For die and wafer products. Make sure (High) ASSD ≥ VGL (Low). reproduced.3 ~ + 9. If these electrical characteristic conditions are exceeded during normal operation.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 13. 7. 8.6 -0. Item Symbol Unit Power supply voltage (1) VCC. When ILI9320 is used out of the absolute maximum ratings. 4 1. or disclosed in whole or in part without prior written permission of ILI Technology Corp.5 -0.3 -40 ~ + 85 -55 ~ + 110 Note 1. 6.VCL V Power supply voltage (1) VGH . Page 109 of 115 Version: 0.VGL V Input voltage Vt V Operating temperature Topr °C Storage temperature Tstg °C Notes: 1. specified up to 85°C.6 -0.5 -0.6 -0.DGND must be maintained 2.3 ~ + 18.41 . 6 1 8.3 ~ + 4.1. 9. 5 1.AGND V Power supply voltage (1) DDVDH . (High) IOVCC ≥ DGND (Low).0 -0. 2 1. VCC.3 ~ + 4. 3.

3V VCC = 2.3 0. SAP=”001”.8V . Page 110 of 115 Version: 0.3V IOL = 0.3 V.65~3.65 ~ 3. Ta=25 °C 5 10 IOP µA VIH VIL VOH1 VOL1 ILI V V V V µA VCC= 1.8V . GRAM data = 0000h.4 ~ 3.4 ~ 3. 335 50 335 Max. fOSC = 376KHz ( Line) GRAM data = 0000h Min.8V . VREG1OUT =4.3V VCC = 2.65 ~ 3.30V. IOVCC = 1.8 ~ 3.2*IOVCC 0.4 ~ 3. CP12-00=”0” CN12-00=”0 LCD Driving Voltage ( DDVDH-DGND ) Output voltage deviation Dispersion of the Average Output Voltage V DDVDH V mV mV 4.0V .3 V) Item Symbol Unit Min. VCC = 2. MN52-00=”0”.40 ~ 3.3V VCC = 2.65 ~ 3.41 .4 ~ 3. MP52-00=”0”.8*IOVCC -0. and shall not be distributed. fOSC = 376KHz (320 LCD Drive Power Supply Current ( DDVDH-DGND ) ILCD mA line) . ON4-0=”0”.30V Item Symbol External Clock Frequency External Clock Duty External Clock Rising Time External Clock Falling Time RC oscillation clock fcp fDuty Trcp Tfcp fOSC Test Condition VCC = 2.2.30V.5. Ta=25°C .1 mA IOVCC=1. Max. Clock Characteristics VCC = 2.8 ~ 3.2 395 Unit KHz µs µs KHz 13.2*IOVCC 0.1 - Max.3V VCC= 1. DC Characteristics (VCC = 2. Typ. LCD Driver Output Characteristics The information contained herein is the exclusive property of ILI Technology Corp.3V IOH = -0. 275 45 275 Typ. 0.4 ~ 3. IOVCC = 1.30V. IOVCC = 1.40 ~ 3.8*IOVCC -0.5 -10 5 6 10 3. Reset low-level width Reset rise time tRES trRES ms µs 1 10 tRES nRESET VIL trRES VIH 13. 395 55 0. reproduced.1mA Vin = 0 ~ VCC VCC=2.8V DDVDH=5. Reset Timing Characteristics Reset Timing Characteristics (VCC = 1. Ta=25 °C.8 ~ 3. Ta= -40 ~ 85 °C) Item Symbol Unit Test Condition Input high voltage Input low voltage Output high voltage(1) ( DB0-17 Pins) Output low voltage ( DB0-17 Pins) I/O leakage current Current consumption during normal operation (VCC – DGND ) Current consumption during standby mode (VCC – DGND ) VCC=2. IOVCC 0.1 - Note - 13.8V Min.3V VCC= 2.3.3V Rf = 130KΩ. 100 (VCC) 13. REV=”0”.0 IST µA VCC=2.4. or disclosed in whole or in part without prior written permission of ILI Technology Corp.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 Typ. OP4-0=”0”.2 0.

3V) Item Bus cycle time Write Read Symbol tCYCW tCYCR PWLW PWHW PWLR PWHR tWRr/tWRf tAS tAH tDSW tH tDDR tDHR Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Min. Max. 100 300 50 50 150 150 10 5 5 10 15 5 Typ.6. VCC=2. 500 25 100 Test Condition - Write low-level pulse width Write high-level pulse width Read low-level pulse width Read high-level pulse width Write / Read rise / fall time Write ( RS to nCS. SAP=010. ILI9320 Typ. 0N14-00=0.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color Item Driver output delay time Symbol Timing diagram VCC=2. 0P14-00=0. MP52-00=0. E/nWR ) Setup time Read ( RS to nCS. Ta=25°C REV=0.1. Max.65~3. Unit tdd - 35 - µs 13. and shall not be distributed.0V.8V. CP12-00=0. RC oscillation: fosc =376kHz (320 lines). or disclosed in whole or in part without prior written permission of ILI Technology Corp. AP=010. i80-System Interface Timing Characteristics Normal Write Mode (IOVCC = 1. MN52-00=0. AC Characteristics 13.4~3. Page 111 of 115 Version: 0. RW/nRD ) Address hold time Write data set up time Write data hold time Read data delay time Read data hold time The information contained herein is the exclusive property of ILI Technology Corp. Load capacitance C=20pF • when the level changes from a same grayscale level on all pins • Time to reach +/-35mV when VCOM polarity inverts Min.3V. DDVDH=5. reproduced.41 .6. VREG1OUT =4. CN12-00=0.8V. Load resistance R=10kΩ.

Serial Data Transfer Interface Timing Characteristics (IOVCC= 1. Max. 100 200 40 100 40 100 10 50 20 20 5 Typ. and shall not be distributed. Page 112 of 115 Version: 0. PWHR VIH tWRr tH Valid Data tDHR VOH VOL Valid Data VOH VOL VIH VIL tCYCW.3V) Item Serial clock cycle time Serial clock high – level pulse width Serial clock low – level pulse width Write ( received ) Read ( transmitted ) Write ( received ) Read ( transmitted ) Write ( received ) Read ( transmitted ) Symbol tSCYC tSCYC tSCH tSCH tSCL tSCL tSCr.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 VIH VIL RS VIH VIL tAS tAH nCS PWLW. or disclosed in whole or in part without prior written permission of ILI Technology Corp.653. reproduced. tSCf tCSU tCH tSISU tSIH tSOD tSOH Unit µs µs ns ns ns ns ns ns ns ns ns ns ns Min.4~3. nRD tWRf VIH VIL VIH VIL PWHW.3V and VCC=2. PWLR nWR.2. tCYCR tDSW Write Data DB[17:0] tDDR Read Data DB[17:0] VIH VIL Figure 51 i80-System Bus Timing 13. 5 100 Test Condition Serial clock rise / fall time Chip select set up time Chip select hold time Serial input data set up time Serial input data hold time Serial output data set up time Serial output data hold time The information contained herein is the exclusive property of ILI Technology Corp.41 .6.

25 Test Condition - The information contained herein is the exclusive property of ILI Technology Corp. or disclosed in whole or in part without prior written permission of ILI Technology Corp.4~3. VSYNC. VSYNC. HSYNC. HSYNC. trghf Unit ns ns ns ns ns ns ns ns ns Min.65 ~ 3. VCC=2.3V) Item VSYNC/HSYNC setup time ENABLE setup time ENABLE hold time PD Data setup time PD Data hold time DOTCLK high-level pulse width DOTCLK low-level pulse width DOTCLK cycle time DOTCLK. Page 113 of 115 Version: 0.3V) Item VSYNC/HSYNC setup time ENABLE setup time ENABLE hold time PD Data setup time PD Data hold time DOTCLK high-level pulse width DOTCLK low-level pulse width DOTCLK cycle time DOTCLK.3. - Max.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 VIH nCS VIL tCSU tSCr VIL tSISU tSCYC tSCf tSCL VIH VIL VIL VIH tCH tSCH VIH SCL VIH VIL tSIH Input Data VIH VIL Input Data SDI tSOD SDO VIH VIL VOH VOL Output Data VOH VOL Output Data VOH VOL Figure 52 SPI System Bus Timing 13. rise/fall time Symbol tSYNCS tENS tENH tPDS tPDH PWDH PWDL tCYCD trghr. trghf Unit ns ns ns ns ns ns ns ns ns Min.3V. reproduced.3V. RGB Interface Timing Characteristics 18/16-bit Bus RGB Interface Mode (IOVCC = 1.6. - Max. 0 10 10 10 40 40 40 100 - Typ.41 .4~3. and shall not be distributed. 0 10 10 10 30 30 30 80 - Typ. 25 Test Condition - 6-bit Bus RGB Interface Mode (IOVCC = 1.65 ~ 3. rise/fall time Symbol tSYNCS tENS tENH tPDS tPDH PWDH PWDL tCYCD trghr. VCC=2.

Page 114 of 115 Version: 0. reproduced. and shall not be distributed.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 trgbf trgbr HSYNC VSYNC VIH VIL tASE HSYNC VSYNC trgbf VIH VIL tSYNCS tENS VIH VIL PWDL trgbr VIH tENH VIH VIL PWDH VIH VIL tPDS VIH VIL tCYCD tPDH Write Data VIH VIL Figure53 RGB Interface Timing The information contained herein is the exclusive property of ILI Technology Corp. or disclosed in whole or in part without prior written permission of ILI Technology Corp.41 .

or disclosed in whole or in part without prior written permission of ILI Technology Corp. Revision History Version No.01 Date 2006/4/17 Page New Created Description The information contained herein is the exclusive property of ILI Technology Corp. Page 115 of 115 Version: 0.41 . V. and shall not be distributed. reproduced.a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9320 14.