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CSW 353

Assembly Language
Dr. Salma Hamdy
9/30/2013

s.hamdy@cis.asu.edu.eg

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Computer Architecture
• Computer = HW + SW

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Computer Architecture – (cont.)
• Design (implementation): specs  develop HW for the system: what HW to use and how to connect the parts. • Organization: the way the HW components operate  they are in place and we investigate the organizational structure to verify the computer parts operate as intended. • Architecture: structure and behavior of the computer as seen by the user. Includes information format, instruction set, techniques for addressing memory.
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) 9/30/2013 4 .Computer Architecture – (cont.

) 9/30/2013 5 .Computer Architecture – (cont.

Computer Architecture – (cont.) 9/30/2013 6 .

• ISA prepares the microprocessor to respond to all the user commands like execution of data.Instruction Set Architecture • Instruction Set Architecture (ISA) can be defined as an interface to allow easy communication between the programmer and the hardware. copying data. editing. 9/30/2013 7 . etc. deleting it.

• Opcode + Operand 9/30/2013 .) ISA Addressing Mode • The manner of accessing memory • Direct vs indricet.Instruction Set Architecture – (cont. 8 IS • The group of instructions given to the computer.

9/30/2013 9 .) • Does the computer performance depend on ISA? • CPU performance depends on Instruction Count. CPI (Cycles per instruction) and Clock cycle time.Instruction Set Architecture – (cont. And all three are affected by the instruction set architecture.

Apple supporters want the hardware to be simple and easy and software to take the major role.CISC and RISC Architectures • Intel supporters want the hardware to bear more responsibility and software on the easier side. 9/30/2013 10 . On the other hand. • Intel’s hardware oriented approach is termed as Complex Instruction Set Computer (CISC) while that of Apple is Reduced Instruction Set Computer (RISC). This would impact the hardware designing to be more complex but software coding would be relatively easy.

9/30/2013 11 .e. simple instructions take less time to interpret) at the cost of the number of instructions per program. • Reduced Instruction Set Computer (RISC) reducing the cycles per instruction (i.) • Complex Instruction Set Computer (CISC) Attempts to minimize the number of instructions per program.CISC and RISC Architectures – (cont. sacrificing the number of cycles per instruction.

CISC and RISC Architectures – (cont.  Unpredictable fetch-decode-execute time. • Example: x86 ISA 9/30/2013 12 .) CISC Architecture • Memory was expensive  bigger program  more storage  more money.  Variable length instruction. • Lead to many different kinds of instructions that access memory.  More complex instruction set  Handled by hardware. • Reduce number of instructions per program by having multiple operations within a single instruction.

) RISC Architecture • To reduce the ISA  Provide minimal set of instructions that could carry out all essential operations. • The complexity that is removed from ISA is moved into the domain of the assembly programmer/compiler. SPARC (Sun).CISC and RISC Architectures – (cont. 9/30/2013 13 • Examples: LC3. Allow memory access only with explicit load/store instructions. Each instruction performs less work.  Instruction execution time among different instructions is consistent. . MIPS. Having few simple instructions that are the same length. PowerPC (IBM). • Instruction complexity is reduced by: 1. 2.

9/30/2013 RISC • Simple instructions. • Only LOAD/STORE instructions access memory. • Many instructions can access memory. • Fixed length instructions. • Few addressing modes. few in number. • Complexity in compiler.) CISC • Many complex instructions. 14 .CISC and RISC Architectures – (cont. • Complexity in microcode. • Many addressing modes. • Variable length instructions.

• Motorola/PowerPC RISC. • Intel runs Linux/Windows. 9/30/2013 15 . • So the type of binaries/programs which run are different.) • Intel x86 CISC. • RISC runs Macintosh/apple computers (latest have Intel also).CISC and RISC Architectures – (cont.

and IS of that architecture. .Building A Computer • Adapt an architecture.CISC • Implement the design. organization.Mano .Intel x86 9/30/2013 16 . .

9/30/2013 17 .) • x86 assembly languages are used to produce object code for the x86 class of processors. • 8086 Assembly.Computer Architecture – (cont.

What is Assembly Language? • Talking to your Computer 1.High-level Language 18 .Machine Language 2.Assembly Language 3.

Still too many instructions. . .What is Assembly Language? – (cont.English-like abbreviations.) • Talking to your Computer 2.Requires assembler.Assembly Language . 19 .

What is Assembly Language? – (cont. 9/30/2013 20 . • Converted into executable machine code by an assembler.) • A low-level programming language in which there is a very strong correspondence between the language and the architecture's machine code instructions. • Each assembly language is specific to a particular computer architecture.

CSW 353 (Assembly Language) Computer Architecture 9/30/2013 21 .

• Solve problems related to processor.Course Logistics – Objectives • Know the basics of computer organization and instruction set architecture. • Know the basic components of modern computers. memory and input/output systems are organized and how pipelining could improve the performance of a computer. • Elaborate the knowledge by building a simple computer using either a programming language or drawing a chart. memory and input/output performance. and understand how they work. • Understand how processing. 22 .

Tamer Mostafa • csw353@gmail.hamdy@cis.asu.com – Dr.Course Logistics – Staff • Teachers – Dr. Salma Hamdy • s.edu.eg • Course page https://piazza.com/faculty_of_computer_and_information_sciences/fall 2013/csw353/home Access Code: csw353 23 .

• Assessment (100 points) Final Term Examination Practical Work Mid Term Examination 65 25 10 YOUR JOB read + think + solve + code = HW + lab tasks + exams 24 .Course Logistics – General • Class meets: Saturday 11:00-14:00 Monday 11:00-14:00 • Lab meets: check your schedule! • (3-hour lecture + 3-hour lab) a week.

Time management 2. Your rights. My rights. 25 . Questions Cheating and copied assignments. projects. or code segments. 3. programs. Your rights. Attendance 3.Course Logistics – Ethics Lecture 1. Mind + hands (if possible) 5. 6. Time management 2. 7. will not be tolerated. Attend ONLY in your class. Mind + hands (BOTH!!!) 5. Manners 4. Manners 4. TA’s rights. 7. 6. Questions Lab 1.

Computer System Architecture 3rd edition. 1992. Morris Mano.Course Logistics – Textbook • M. Prentice Hall. • 8086 Assembly reference to be decided. 26 .

Course Logistics – Textbook Outline Chapters 1-4 present the various digital components used in the organization and design of computer systems. Chapters 5-7 cover the steps that a designer must go through to design and program an elementary digital computer. Chapters 8-9 deal with the architecture of the central processing unit.12 present the organization and architecture of the input-output processor and the memory unit. 27 . Chapters 11.

Course Logistics – Textbook Outline Chapter 1: Digital Logic Circuits Chapter 2: Digital Components Chapter 3: Data Representation Chapter 4: Microoperations 28 .

Course Logistics – Textbook Outline Chapter 1: Digital Logic Circuits Chapter 2: Digital Components Chapter 3: Data Representation Chapter 4: Microoperations Chapter 5: Basic Computer Organization Chapter 6: Programming the Basic Computer Chapter 7: Microporgammed Control 29 .

Course Logistics – Textbook Outline Chapter 1: Digital Logic Circuits Chapter 2: Digital Components Chapter 3: Data Representation Chapter 4: Microoperations Chapter 5: Basic Computer Organization Chapter 6: Programming the Basic Computer Chapter 7: Microporgammed Control Chapter 12: Memory Organization Chapter 8: CPU Chapter 11: I/O Organization 30 .

Review of Digital Design Basics 1. 2. 4. 3. 5. Logic Gates Boolean Algebra Combinational Circuits Clock Flip-Flops Sequential Circuits . 6.

NOT. • Hence. Logic Gates • Two voltage levels – high and low (1 and 0. true and false).) 9/30/2013 32 . the use of binary arithmetic/logic in all computers. etc. • The manipulation of binary information is done by logic circuits called gates (AND.1. OR.

X = A + B  X is true if at least one of A or B is true • AND : symbol .2. . B  X is true if both A and B are true • NOT : symbol ’ . Boolean Algebra • Equations involving two values and three primary operators: • OR : symbol + . 9/30/2013 33 . X = A . X = A’  X is the inverted value of A (or symbol ).

Boolean Algebra – Basic Rules 9/30/2013 34 .2.

Boolean Algebra – DeMorgan’s Laws 9/30/2013 35 .2.

2. Boolean Algebra – Logic Function • Representation: Algebraic expression Truth table Logic Diagram 9/30/2013 36 .

B. • Consider a block with 3 inputs A.2. Can be compressed by only representing cases that have an output of 1  map simplification 9/30/2013 37 . Boolean Algebra – Logic Function • A truth table defines the outputs of a logic block for each set of inputs. C and an output E that is true only if exactly 2 inputs are true.

etc. • A basic logic block is the gate (AND. Boolean Algebra – Logic Block • A logic block has a number of binary inputs and produces a number of binary outputs – the simplest logic block is composed of a few transistors. OR.) 9/30/2013 38 . • A logic block is termed combinational if the output is only a function of the inputs.2. • A logic block is termed sequential if the block has some internal memory (state) that also influences the output. NOT.

3. and provide components required for data processing. • For generating binary control decisions. Combinational Circuits • A connected arrangement of logic gates with a set of inputs and outputs. 9/30/2013 39 .

Simplify Boolean function for each output. 2.3. Assign letters to input and output variables. Draw logic diagram. 4.) • Designing a combinational circuit: 1. Define truth table. 9/30/2013 40 . Combinational Circuits – (cont. 5. 3. State problem.

Combinational Circuits – (cont.3.) • Example1: Addition of two bits (half-adder) 9/30/2013 41 .

3. Combinational Circuits – (cont.) • Example2: Addition of three bits (full-adder) 9/30/2013 42 .

• A major school of thought (used in most processors built today): all circuits on the chip share a clock signal (a square wave) that tells every circuit when to accept inputs. and produces outputs at time TOX. 9/30/2013 43 . takes time TEX to execute the logic. Clock • A microprocessor is composed of many different circuits that are operating simultaneously – if each circuit X takes in inputs at time TIX. and when they must produce outputs. how much time they have to execute the logic. imagine the complications in co-ordinating the tasks of every circuit.4.

) Rising clock edge Cycle time Falling clock edge 4 GHz = clock speed = 1 cycle time 9/30/2013 44 .4. Clock – (cont.

9/30/2013 45 . the outputs change after a while (time = logic delay through circuit). Flip Flops • Until now.5. circuits were combinational – when inputs change. • Most systems include storage elements  need a signal to affect the stored value at discrete instants of time  clock pulse.

) • Flip-flop: a binary cell capable of storing one bit of information. • Different types according to number if inputs and manner by which inputs affects state.5. 9/30/2013 46 . Flip Flops – (cont. • Maintains state until directed by a clock (rising edge or falling edge) to switch state.

Flip Flops – (cont. • No clock  no state change. C (Clock).) SR Flip-flop • Inputs : S (Set) R (Reset). 9/30/2013 47 .5. • Clock change from 0 to 1  output affected.

9/30/2013 48 .) JK Flip-flop • Refinement of the SR. Flip Flops – (cont.5.

• Rising edge of clock causes the “state” storage to store some input values. 9/30/2013 49 .6. • This state will not change for an entire cycle (until next rising edge). Sequential Circuits • Consists of combinational circuit and a storage element.

6. Sequential Circuits – (cont.)
• Combinational circuit has some time to accept the value of “state” and “inputs” and produce “outputs”. • Some of the outputs (for example, the value of next “state”) may feed back (but through the latch) so they’re only seen in the next cycle.

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6. Sequential Circuits – (cont.)
•  specified by a time sequence of external inputs, external outputs, and internal flipflop binary states. • Representation:
– Boolean expression (for combinational part). – State table. – State diagram.
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6. Sequential Circuits – (cont.)
Example3: • Boolean Fn.

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) Example3: • State Table 9/30/2013 53 . Sequential Circuits – (cont.6.

) Example3: • State Diagram 0/1 00 01 9/30/2013 54 . Sequential Circuits – (cont.6.

) Example3: • State Diagram 9/30/2013 55 . Sequential Circuits – (cont.6.

and 11 when an external input x is equal to 1.) Example4: 2-bit counter • Consider a clocked sequential circuit that goes through a sequence of repeated binary states 00. 10.6. 9/30/2013 56 . • Draw the state diagram. Sequential Circuits – (cont. 01.

6.) Example4: 2-bit counter 9/30/2013 57 . Sequential Circuits – (cont.

6. Sequential Circuits – (cont.) Example4: 2-bit counter x FF A ? FF Clock 9/30/2013 B 58 .

) Example4: 2-bit counter 9/30/2013 59 . Sequential Circuits – (cont.6.

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6. Sequential Circuits – (cont.) Example4: 2-bit counter 9/30/2013 61 .

Sequential Circuits – (cont.) Example4: 2-bit counter 9/30/2013 62 .6.

Next Lecture • Continue review of digital design basics. 9/30/2013 63 .

Reading: Chapter 1.Assignment . 9/30/2013 64 .

com/questions/4185/whatare-different-types-of-computer-architectures -http://www. -http://www.edu/pclt/PCHW/clockidea.stackexchange.htm .God bless Google and Wiki! 9/30/2013 65 .Digital Design. M. Morris Mano.com/articles/risc-and-ciscarchitecture?page=1 -http://electronics. Prentice Hall.engineersgarage.References .yale. 4th ed. 2006.