You are on page 1of 67

CSW 353

(Assembly Language)

Computer Architecture
Dr. Salma Hamdy
10/6/2013

s.hamdy@cis.asu.edu.eg

1

Course Logistics – Textbook Outline
Chapter 1: Digital Logic Circuits Chapter 2: Digital Components Chapter 3: Data Representation Chapter 4: Register Transfer and Microoperations Chapter 5: Basic Computer Organization Chapter 6: Programming the Basic Computer Chapter 7: Microporgammed Control

Chapter 12: Memory Organization

Chapter 8: CPU

Chapter 11: I/O Organization
2

Digital Components
1. 2. 3. 4. 5. 6. Integrated Circuits Decoders Multiplexers Registers Binary Counters Memory Units

1. continuous piece of semiconductor material to perform a high-level function. Integrated Circuits • Miniature. • Usually referred to as a monolithic IC. 10/6/2013 4 . low-cost electronics circuits whose components are fabricated on a single.

1. Integrated Circuits – (cont.) • Characterized by 1. Scale 10/6/2013 5 .

Circuit technology (digital logic family): Bipolar or MOS or both. – Emitter Coupled Logic (ECL). also known as Current Mode Logic(CML).) 2. (obsolete) – Transistor Transistor logic (TTL). • Bipolar: – Diode logic (DL). (obsolete) – Resistor transistor logic (RTL).1. – Integrated Injection logic (I2L). Integrated Circuits – (cont. (obsolete) – Diode transistor logic (DTL). (obsolete) 10/6/2013 6 .

1. Integrated Circuits – (cont.)
2. Circuit technology (digital logic family): Bipolar or MOS or both. • MOS:
– PMOS family (using P-channel MOSFETs) (obsolete) – The NMOS family (using N-channel MOSFETs). – The CMOS family (using both N- and P-channel devices). – The Bi-MOS logic family uses both bipolar and MOS devices.
10/6/2013 7

1. Integrated Circuits – (cont.)
• Data sheet

10/6/2013

8

1. Integrated Circuits – (cont.)
• Basic components Combinational
– Decoders  binary adders or any Boolean function – Multiplexers

Sequential
– Flip-Flops – Registers
 binary counters and memory units

10/6/2013

9

10/6/2013 10 .2. • 𝒏-to-𝒎 line or 𝒏 × 𝒎. Decoders • Converts binary information from 𝒏 coded inputs to a maximum of 𝟐𝒏 unique outputs. (can use less than 𝒎) • Each output represents one of the minterms of the input variables.

Decoders – (cont.2.) • A 𝟑-to-𝟖 line decoder 10/6/2013 11 .

Decoders – (cont.) • Truth table for 𝟑-to-𝟖 line decoder 10/6/2013 12 .2.

and outputs will then represent the eight digits in a octal number system.) • A 𝟑-to-𝟖 line decoder can be used for: – Binary to octal conversion: input variable may represent a binary number.2. 10/6/2013 13 . Decoders – (cont.

2. 10/6/2013 14 .) • Generally. decoders can be used for: – Implementing Boolean functions: any combinational circuit with 𝒏 inputs and 𝒎 outputs can be implemented with an 𝒏-to-𝟐𝒏 decoder and 𝒎 OR gates. – Example: implement a full-adder circuit. Decoders – (cont.

2. Decoders – (cont. – Example: implement a full-adder circuit.) • Decoders can be used for: – Implementing Boolean functions. 10/6/2013 15 .

𝟖 line decoder with enable (demultiplexer) 10/6/2013 16 .) • A 𝟑 -to.2. Decoders – (cont.

Decoders – (cont.𝟖 line decoder with enable: 10/6/2013 17 .2.) • Truth table for 𝟑 -to.

10/6/2013 18 .) • NAND gate decoders produce the minterms in their complement form. Decoders – (cont. • 𝟐-to-𝟒 line NAND decoder with enable.2.

2. larger The most significant bit(s) decide(s) which decoder(s) is/are enabled and which is/are disabled.) • Decoder expansion: constructing decoder from smaller ones. 10/6/2013 19 . Decoders – (cont.

• Has 𝟐𝒏 (or less) input lines and 𝒏 output lines that generate the binary code corresponding to the input value.) • An encoder circuit performs the inverse operation of a decoder. Decoders – (cont.2. 10/6/2013 20 . • Example: octal to binary decoder.

It is assumed that only one input has the value of 1 at any given time. otherwise.) • An encoder circuit performs the inverse operation of a decoder. 10/6/2013 21 .2. • Has 𝟐𝒏 (or less) input lines and 𝒏 output lines. the circuit has no meaning. Decoders – (cont. • Example: octal to binary decoder.

Selected Problems 10/6/2013 22 .

Selected Problems – (cont.) 10/6/2013 23 .

) 10/6/2013 24 .Selected Problems – (cont.

Selected Problems – (cont.) 10/6/2013 25 .

) 10/6/2013 26 .Selected Problems – (cont.

Selected Problems – (cont.) Do 10/6/2013 27 .

Multiplexers • Multiplexing means transmitting a large number of information units over a smaller number of channels or lines. 10/6/2013 28 . data selector) is a combinational circuit that selects binary information from one or many input lines and directs it to as single output line. • Selection is controlled by a set of selection lines 𝟐𝒏 inputs and 𝒏 selection lines.3. • A digital multiplexer (MUX.

) • 𝟒-to-𝟏 multiplexer 10/6/2013 29 . Multiplexers – (cont.3.

one from each data input and using the 𝒏 inputs as selection lines. Multiplexers – (cont. • May have enable input to control the operation of the unit. • Two or more in single IC package.3. 10/6/2013 30 .) • A 𝟐𝒏 -to-𝟏 multiplexer is constructed from an 𝒏-to-𝟐𝒏 decoder by adding to it 𝟐𝒏 input lines.

) • Quadruple 𝟐-to-𝟏 line multiplexer 10/6/2013 31 .3. Multiplexers – (cont.

Selected Problems – (cont.) 10/6/2013 32 .

) 10/6/2013 33 .Selected Problems – (cont.

) 10/6/2013 34 .Selected Problems – (cont.

) 10/6/2013 35 .Selected Problems – (cont.

4. Registers • IC’s that contain storage cells are classified by the function they perform: – Registers – Counters – Memory units. 10/6/2013 36 .

• 𝒏-bit register has a group of 𝒏 flip-flops and is capable of storing any binary information of 𝒏 bits. or any kind of data. a storage address. Registers – (cont.) • A register is a group of flip-flops.4. • Register = flip-flops (load) + gates (control when/how data is transferred into register). 10/6/2013 37 . • Built into the CPU  Very fast • A register may hold a computer instruction .

) • Loading = transfer of new info into a register. Registers – (cont. • Parallel load = all bits of the register are loaded simultaneously (single clock pulse). A 4-bit register 10/6/2013 38 .4.

) • Parallel load • Master clock then a separate load control signal.4. Registers – (cont. 10/6/2013 39 .

4.) • Parallel load example • Design a sequential circuit whose state table is listed below. 10/6/2013 40 . Registers – (cont.

4. 10/6/2013 41 .) • Parallel load example • Design a sequential circuit whose state table is listed below. Registers – (cont.

) • Parallel load example • Design a sequential circuit whose state table is listed below.4. Registers – (cont. 10/6/2013 42 .

) • Parallel load example 10/6/2013 43 .4. Registers – (cont.

) • Shift Register: capable of shifting its binary information in one (unidirectional) or both directions (bidirectional). Registers – (cont. • Logical configuration: a chain of flip-flops in cascade. 10/6/2013 A 4-bit shift register 44 .4.

4. Registers – (cont.) • Serial transfer 10/6/2013 45 .

Registers – (cont.4.) • Serial transfer 10/6/2013 46 .

– Shift right operation and serial input line. 10/6/2013 47 . – Shift-left operation and serial input line.4. Registers – (cont. – Control state.) • The most general shift register has all these capabilities: – Clock pulse input to sync. • Bidirectional shift register with parallel load. – Parallel load operation an 𝒏 input lines. – 𝒏 parallel output lines.

4.) • Bidirectional shift register with parallel load 10/6/2013 48 . Registers – (cont.

4.) • Bidirectional shift register with parallel load 10/6/2013 49 . Registers – (cont.

4. Registers – (cont. 10/6/2013 50 .) • Bidirectional shift register with parallel load often used to interface digital systems situated remotely from each other. • Receiver accepts one at a time through serial input into a shift register. e. • Transmitter loads in parallel into a shift register. then taken in parallel after all bits are accumulated. transmits from serial output.g. transmission of 𝒏-bit between two points.

Counters • A counter is basically a register that goes through a predetermined sequence of states upon the application of input pulses.5. 0000. – Direct inspection of the sequence of states that the register must undergo. 0010 when does a bit change? 10/6/2013 51 . – e. • The design of synchronous binary counters: – Previous lecture (sequential circuits).g. 0001.

Counters – (cont. 10/6/2013 52 .5. • Example: 4-bit counter with JK flip-flips.) • Synchronous binary counters have a regular patter and their circuit will usually employ flip-flops with complementing capabilities T or JK.

5. 10/6/2013 To extend counter to next stage 53 .) • 4-bit synchronous binary counter. Counters – (cont.

10/6/2013 54 . Counters – (cont.) • Binary counters with Parallel Load for transmitting an initial binary number prior to the counter operation.5.

5. Counters – (cont.) • Binary counters with Parallel Load 10/6/2013 55 .

Selected Problems 10/6/2013 56 .

) 10/6/2013 57 .Selected Problems – (cont.

) 10/6/2013 58 .Selected Problems – (cont.

) 10/6/2013 59 .Selected Problems – (cont.

Selected Problems – (cont.) 10/6/2013 60 .

) 𝐴4 𝐴5 𝐴6 𝐴7 10/6/2013 61 .Selected Problems – (cont.

) 10/6/2013 62 .Selected Problems – (cont.

) 10/6/2013 63 .Selected Problems – (cont.

) 10/6/2013 64 .Selected Problems – (cont.

) 10/6/2013 65 .Selected Problems – (cont.

10/6/2013 66 .Next Lecture Register Transfer and Microoperations.Reading: Chapters 2+3. Assignment .

M.ac.com/articles/what-is-computer-ramrandom-access-memory. Prentice Hall.kr/ ch02 -http://www. Morris Mano.kut.God bless Google and Wiki! 10/6/2013 67 . 4th ed.Digital Design. 2006.References .html -http://newton.buzzle.anl. -http://microcom.dep.htm .gov/askasci/comp99/CS036.