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CSW 353

(Assembly Language)

Computer Architecture
Dr. Salma Hamdy
10/7/2013

s.hamdy@cis.asu.edu.eg

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Course Logistics – Textbook Outline
Chapter 1: Digital Logic Circuits Chapter 2: Digital Components Chapter 3: Data Representation Chapter 4: Register Transfer and Microoperations Chapter 5: Basic Computer Organization Chapter 6: Programming the Basic Computer Chapter 7: Microporgammed Control

Chapter 12: Memory Organization

Chapter 8: CPU

Chapter 11: I/O Organization
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Register Transfer and Microoperations
1. 2. 3. 4. Register Transfer Language Transfer (Register, Bus, Memory) Microoperations (Arithmetic , Logic, Shift) Arithmetic Logic Shift Unit

1. Register Transfer Language
• Circuits IC components  modules + data + control paths computer. • Microoperation: operations executed on data stored in registers (shift, clear, load, count). • Internal HW organization is best defined by specifying:
1. The set of registers and their functions. 2. The sequence of microoperations. 3. The control that initiates the sequence of microoperations.
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1. Register Transfer Language – (cont.)
Register Transfer Language: the symbolic notation used to describe the microoperations transfer among registers • The use of symbols instead of a narrative explanation provides an organized and concise manner. • A convenient tool for describing the internal organization of digital computers in a concise and precise manner.
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– R1 (Processor Register). – PC (Program Counter). – IR (Instruction Register). 10/7/2013 6 .1. Register Transfer • Registers are designated by Capital Letters (sometimes followed by numerals): – MAR (Memory Address Register).

) • Register Transfer: Information transfer from one register to another in symbolic form: 𝑹𝟐 ← 𝑹𝟏 • Register transfer with control function: 𝑷: 𝑹𝟐 ← 𝑹𝟏 10/7/2013 7 .1. Register Transfer – (cont.

) • Register Transfer: Information transfer from one register to another in symbolic form: 𝑹𝟐 ← 𝑹𝟏 • Register transfer with control function: 𝑷: 𝑹𝟐 ← 𝑹𝟏 means if(𝑷) then (𝑹𝟐 ← 𝑹𝟏) 10/7/2013 8 . Register Transfer – (cont.1.

) • Two or more operations at the same time (during a common clock pules): 𝑷: 𝑹𝟐 ← 𝑹𝟏. Register Transfer – (cont.1. 𝑹𝟏 ← 𝑹𝟐 10/7/2013 9 .

3. Bus Transfer • Common Bus is a more efficient scheme for transferring information between registers in a multiple-register configuration. 10/7/2013 10 . • Control signals determine which register is selected. • A bus structure = a set of common lines one for each bit of a register.

• Size of multiplexer = number of registers. 10/7/2013 11 . Multiplexers • The multiplexers select the source register whose binary information is placed on the bus.3. Bus Transfer – (cont. • Number of multiplexers = size of register.) • Constructing a common bus is done with: 1.

3.) 10/7/2013 12 . Bus Transfer – (cont.

3. 𝑹𝟏 ← 𝑩𝑼𝑺 Bus 𝑹𝟏 Register 10/7/2013 n 𝑪 Register 13 .) • Constructing a common bus is done with: 1. Multiplexers • The content of register 𝑪 is placed on the bus. Bus Transfer – (cont. and the content of the bus is loaded into register 𝑹𝟏 by activating its load control input 𝑩𝑼𝑺 ← 𝑪.

eight 16-bit registers  ? 10/7/2013 14 . • e. Bus Transfer – (cont. Multiplexers • In general a bus system will multiplex 𝒌 registers of 𝒏 bits to produce an 𝒏 -line common bus  𝒏 multiplexers of size 𝒌 × 𝟏.3.g.) • Constructing a common bus is done with: 1.

to prevent mixed interactions. high-impedance (open circuit).) • Constructing a common bus is done with: 2. 10/7/2013 15 . and to supply additional drive or relay capability.3. Three-State Bus Buffer • Tri-State: 0. 1. • Buffer: a device designed to be inserted between other devices to match impedance. Bus Transfer – (cont.

Bus Transfer – (cont.3. Three-State Bus Buffer • The outputs of the 𝒌 buffers are connected together to form a single bus line.) • Constructing a common bus is done with: 2. • No more than one buffer may be in the active state at any given time (how?) 10/7/2013 16 .

Three-State Bus Buffer • The outputs of the 𝒌 buffers are connected together to form a single bus line.3. 𝒎 • Size of decoder = 𝐦 × 𝒌 such that 𝟐 = 𝒌. • No more than one buffer may be in the active state at any given time  decoder. • Number of decoders = size of registers = 𝒏.) • Constructing a common bus is done with: 2. Bus Transfer – (cont. 10/7/2013 17 .

Three-State Bus Buffer • Bit 0 for four registers: 10/7/2013 18 .3. Bus Transfer – (cont.) • Constructing a common bus is done with: 2.

• Memory read : transfer information into 𝑫𝑹 from the memory word 𝑴 selected by the address in 𝑨𝑹.4. Memory Transfer • Memory Unit is a collection of storage cells together with associated circuits needed to transfer information in and out of storage. 𝑹𝒆𝒂𝒅: 𝑫𝑹 ← 𝑴[𝑨𝑹] • Memory Write : transfer information from 𝑹𝟏 into the memory word 𝑴 selected by the address in 𝑨𝑹. 𝑾𝒓𝒊𝒕𝒆 𝑴 𝑨𝑹 ← 𝑹𝟏 10/7/2013 19 .

but much larger. 10/7/2013 20 . Binary information is made permanent during HW production.Used to store constant tables.4. .) . Memory Transfer – (cont. . programs that boot the computer and perform diagnostics  usually small.Slower than registers.ROM: performs read operations only.RAM: can transfer the stored info out (read) and also receive new information in (write) any desired random location. .

Memory read enabled. Memory Transfer – (cont. . 10/7/2013 21 .4. • Read: .) • A memory unit that communicates with multiple registers.Word at address specified by chosen address register is loaded into register with enabled load input. • Left MUX decides which address register. • Decoder decides which destination register has an active load input.

4. . • Decoder decides which destination register has an active load input. Memory Transfer – (cont. • Write: . to memory at address specified by address 10/7/2013 register. • Left MUX decides which address register.) • A memory unit that communicates with multiple registers.Memory write enabled. 22 .Right MUX decides which destination register to transfer word from.

• All other microoperations change content during transfer. • The basic set of microoperations: – Arithmetic – Logic – Shift • Each have its symbolic hardware implementation.5. 10/7/2013 notation and 23 . Microoperations • Register transfer do not change binary info.

Arithmetic Microoperations • Basic arithmetic microoperation: – Add – Subtract – Complement – Shift • All other arithmetic microoperations can be obtained from a variation or a sequence of them.6. 10/7/2013 24 .

6.) • Basic arithmetic microoperation: 10/7/2013 25 . Arithmetic Microoperations – (cont.

10/7/2013 26 .) Binary Adder Hardware Implementation • Using full-adders connected in cascade.6. Arithmetic Microoperations – (cont.

6.) Binary Adder-Subtractor Hardware Implementation • Remember that 𝑨 − 𝑩 = 𝑨 + 𝟐′𝒔 𝒐𝒇 𝑩 = 𝑨 + 𝑩 + 𝟏 • Hence combine addition and subtraction in one circuit with a control input 𝑴. • 𝑴 = 𝟏 (add) • 𝑴 = 𝟎 (subtract) 10/7/2013 27 . Arithmetic Microoperations – (cont.

) Binary Adder-Subtractor Hardware Implementation • M = 0 : Adder B  M + C = B  0 + 0 = B.B 10/7/2013 28 . Arithmetic Microoperations – (cont.  A + B • M = 1 : Subtractor B  M + C = B  1 + 1 = B’ + 1= -B(2’s comp). A .6.

Arithmetic Microoperations – (cont.) Binary Incrementer Hardware Implementation • Binary counter (previous lectures). 10/7/2013 29 . • Combinational circuits: – Half-adders connected in cascade.6. – Least significant adder have one input = 1.

Arithmetic Microoperations – (cont.6.) Binary Incrementer Hardware Implementation • Combinational circuits: – Half-adders connected in cascade. 10/7/2013 30 .

6. Arithmetic Microoperations – (cont. 10/7/2013 31 .) Arithmetic Circuit • Combining all listed microoperations in one composite circuit.

Arithmetic Microoperations – (cont.) Arithmetic Circuit A+1111=A-1 10/7/2013 A-1+1=A 32 .6.

Logic Microoperations • Logic microoperations consider each bit of the register separately and treat them as binary variables. 𝐏: 𝑹𝟏 ← 𝑹𝟏𝑹𝟐 1010 Content of 𝑹𝟏  1100 Content of 𝑹𝟐 0110 Content of 𝑹𝟏 after 𝑷 = 𝟏 10/7/2013 33 . • e. • Seldom used in scientific computations but very useful for bit manipulation and logical decisions.7.g.

10/7/2013 34 .g. 𝐑𝟒 ← 𝑹𝟓  𝑹𝟔 • Means: if(𝑷 OR 𝑸) then (add 𝑹𝟏 to 𝑹𝟐 and put the result in 𝑹𝟏. 𝐏 + 𝐐: 𝑹𝟏 ← 𝑹𝟐+𝑹𝟑. Logic Microoperations – (cont. • e. – In control (or Boolean) function == AND.7. not ( ) • The plus sign usage: – In microoperation == addition. or (). and perform 𝑹𝟓 OR 𝑹𝟔 and put the results in 𝑹𝟒).) • Symbolic notation: and ().

) 10/7/2013 35 . Logic Microoperations – (cont.7.

10/7/2013 36 . NOT) and derive the rest from them. OR. Logic Microoperations – (cont. XOR.7.) Hardware Implementation • Most computers use only four microoperations (AND.

10/7/2013 37 . NOT) and derive the rest from them.7. Logic Microoperations – (cont. XOR. OR.) Hardware Implementation • Most computers use only four microoperations (AND.

) Some applications • Manipulating individual bits or a portion of a word stored in a register • Change bit values.7. or insert new bit values. Logic Microoperations – (cont. delete a group of bits. 10/7/2013 38 .

1010 A before • Selective-complement A  A B – Complements bits in A where there are corresponding 1’s in B. 1010 1100 B (Logic Operand) 10/7/2013 1100 B (Logic Operand) 1110 A After Selective-set 0110 A After 39 . It does not effect bit A before positions that have 0’s in B.7. It does not effect bit positions that have 0’s in B. Logic Microoperations – (cont.) Some applications • Selective-set A  A  B – Sets to 1 the bits in register A where there are corresponding 1’s in register B.

1010 A before 10/7/2013 1100 B (Logic Operand) 1000 A After 40 Selective-mask . Logic Microoperations – (cont. 1100 B (Logic Operand) 0010 A After Selective-clear • Selective-mask A A B – Similar to the selective-clear operation except that the bits of A are cleared only where there are corresponding 0’s in B.7.) Some applications • Selective-clear A  A  B – Clears to 0 the bits in A only where there are 1010 A before corresponding 1’s in B.

Logic Microoperations – (cont. – This is done by first masking the bits and then ORing them with the required value. 1) Mask 0110 1010 A before 0000 1111 B mask 0000 1010 A after mask 10/7/2013 2) OR 0000 1010 A before 1001 0000 B insert 1001 1010 A after insert 41 .) Some applications • Insert – The insert operation inserts a new value into a group of bits.7.

logic and data-processing operations. • Three types: – Logical – Circular – Arithmetic 10/7/2013 42 .8. • with conjunction with arithmetic. Shift Microoperations • Used for serial transfer of data.

• 𝑹𝟏 ← 𝒔𝒉𝒍 𝑹𝟏 • 𝑹𝟐 ← 𝒔𝒉𝒓 𝑹𝟐 0 0 10/7/2013 Register symbol must be the same on both sides of arrow 43 . • Shift-left or shift-right. • The bit transferred to the end position through the serial input is assumed to be 0 during a logical shift (zero inserted). Shift Microoperations Logical Shift • Transfers 0 through the serial input.8.

• 𝑹𝟏 ← 𝒄𝒊𝒍 𝑹𝟏 • 𝑹𝟐 ← 𝒄𝒊𝒓 𝑹𝟐 10/7/2013 Register symbol must be the same on both sides of arrow 44 . Shift Microoperations Circular Shift • Shift-left or shift-right. • The circular shift circulates the bits of the register around the two ends without loss of information.8.

10/7/2013 45 .8. Shift Microoperations Arithmetic Shift • Shifts a signed binary number to left or right • Shift-left == multiplication by 2. • Must leave the sign bit unchanged because the sign of the number remains the same. • Shift-right == division by 2.

10/7/2013 46 .. . Shift Microoperations Arithmetic Shift • Shift-left Carry out Sign bit Rn-1 Rn-2 MSB R2  ashl R2 0 insert .. R1 LSB R0 • Shift-right MSB R2  ashr R2 LSB lost LSB • Sign reversal occurs with overflow  detect with FF.8..

to shifter. 10/7/2013 47 . • Combinational circuit – More efficient. – n-bit shifter == n multiplexers. – Register on common bus.8. – Only one clock pulse to load and shift. – MUX to decided shift type. Shift Microoperations Hardware Implementation • Bidirectional shift register with parallel load (previous lectures). back to register.

8. Shift Microoperations Hardware Implementation • A 4-bit Combinational shifter 10/7/2013 48 .

Arithmetic Logic Shift Unit • Instead of individual registers performing microoperation  storage registers + ALU. 10/7/2013 49 . • ALU is combinational one clock pulse to complete task. • MUX to choose between logical and arithmetic operations outputs.9.

Arithmetic Logic Shift Unit – (cont.) Hardware Implementation • One stage of Arithmetic Logic Shift Unit. 10/7/2013 50 .9.

Selected Problems • To be selected! 10/7/2013 51 .

10/7/2013 52 . Assignment .Next Lecture Basic Computer Organization and Design.Reading: Chapter 4.

Prentice Hall.kr/ ch04 . M. Morris Mano.God bless Google and Wiki! 10/7/2013 53 . -http://microcom.kut. 2006.References .Digital Design.ac. 4th ed.