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CSW 353

(Assembly Language)

Computer Architecture
Dr. Salma Hamdy
10/30/2013

s.hamdy@cis.asu.edu.eg

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Computer System Architecture
Chapter 1: Digital Logic Circuits Chapter 2: Digital Components Chapter 3: Data Representation Chapter 4: Register Transfer and Microoperations Chapter 5: Basic Computer Organization Chapter 6: Programming the Basic Computer Chapter 7: Microporgammed Control

Chapter 12: Memory Organization

Chapter 8: CPU

Chapter 11: I/O Organization
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1. 2. 3. 4.

Instruction Codes Computer Registers Computer Instructions Timing and Control

Basic Computer Organization and Design - I
Ch5. Introduces the basic computer and shows its operation can be specified with register transfer statements.

10/30/2013 4 .1. • The user of a computer can control the process by means of a program (set of instructions that specify the operations. and can be instructed as to what specific sequence of operations it must perform. and the sequence by which processing has to occur. operands. Instruction Codes • The general-purpose computer is capable of executing various microoperations.

Instruction Codes – (cont. • Every computer has its own unique instruction set.) • Instructions and data are stored in memory. 10/30/2013 5 . Memory Read instruction Control register • Interpret binary code of instruction. • Execute it by issuing a sequence of microoperations.1. • The most important property of a general-purpose computer is the ability to store and execute instructions (stored program concept).

which is the group of bits that define such operations as add.1. subtract. • Its most basic part is the operation part. … etc. shift. operation part …………………… 10/30/2013 instruction 6 .) • Instruction: group of bits that instruct the computer to perform a specific operation. Instruction Codes – (cont. • Size of operation part depends on the total number of operations available in the computer (𝟐𝒏 distinct operations require an operation part of 𝒏 bits).

) • Executing an instruction by control unit: – Receives instruction from memory. • Operation code = macrooperation.1. – Issues a sequence of control signals to initiate microoperations in internal computer registers. 10/30/2013 7 . – Interprets its operation code (opcode) bits. • Operations vs. microoperation. Instruction Codes – (cont.

) • e. it issues control signals to read operand from memory and add it to a processor register. Instruction Codes – (cont. 10/30/2013 8 .1.g. A computer with 64 distinct operations has an instruction set with a 6-bit operation code. When the control interprets this code. One of them can be ADD operation with code 110010.

) • Operation must be performed on some data stored in memory.Memory word by address. information opcode about data instruction 10/30/2013 Specify: . • An instruction code therefore must include not only the operation.1. but also the registers or memory words where the operands are stored.Processor register by 𝒌 bits to select one among 𝟐𝒌 . . as well as the register or memory word where the result is to be stored. 9 . Instruction Codes – (cont.

) • Instruction code formats are invented by the designer who specify the architecture of the computer. we will adopt the following stored program organization: – – – – One processor register (accumulator 𝑨𝑪).1. Two-part instruction code. Operation is performed on operand and content of processor register. Address is where to find operand. 10 10/30/2013 . Instruction Codes – (cont. • In our basic computer design.

) 10/30/2013 11 .1. Instruction Codes – (cont.

– Address of operand  direct. 10/30/2013 12 . • Target address in a branch-type instruction.1. • One bit 𝑰 in the instruction code is used to distinguish between direct and indirect.) Effective Address • Address of operand in a computational instruction. Instruction Codes – (cont. – Address of a memory word that stores the address of operand  indirect. Addressing modes: • When the second part of instruction code specifies – An operand  immediate.

) • Indirect access mode bit Direct Indirect 𝑰 Memory references Effective address 0 1 457 1 2 1350 10/30/2013 13 . Instruction Codes – (cont.1.

 Register to store instruction read from memory. 10/30/2013 14 .  Register for holding memory addresses.  Counter to calculate address of next instruction. Computer Registers • Instructions are normally stored in consecutive memory locations and executed sequentially one at a time starting from a specific address.  Register to manipulate data.2.

) • Basic computer registers and memory and their functions. Computer Registers – (cont. branching 10/30/2013 15 .2.

Computer Registers – (cont. How to connect all of them? branching 10/30/2013 16 .2.) • Basic computer registers and memory and their functions.

Memory read/write.2. Selecting output on bus.) Common Bus System • • • • • • Bus size. Receiving data from bus. Varying register size. 10/30/2013 17 . Controls. Computer Registers – (cont.

) Registers Design 10/30/2013 18 .2. Computer Registers – (cont.

) Registers Design • Binary counter with parallel load and synchronous clear. 10/30/2013 19 . Computer Registers – (cont.2.

Computer Registers – (cont.2.) Registers Design 10/30/2013 20 .

) Registers Design • Register with parallel load.2. Computer Registers – (cont. 10/30/2013 21 .

eliminating the need for address bus.) Memory Design • Address is specified by 𝑨𝑹. • Any register can receive data from memory after a read operation except 𝑨𝑪. Computer Registers – (cont. • Content of any register can be specified from memory for a write operation. 10/30/2013 22 .2.

10/30/2013 23 . • This circuit has three sets of inputs.) AC • Its 16 inputs come from adder logic circuit. Computer Registers – (cont.2.

𝑨𝑪 ← 𝑫𝑹 10/30/2013 24 . Computer Registers – (cont.2.) Clock • Single pulse to 𝑫𝑹 ← 𝑨𝑪.

10/30/2013 25 . Computer Instructions Basic Computer Instruction Format • Memory-reference instruction. • Input-output instruction. • Register-reference instruction.3.

3. Computer Instructions – (cont.) Basic Computer Instruction Format 10/30/2013 26 .

(AND opcode: 000) • Instruction: 0 000 000000001100 10/30/2013 27 . Computer Instructions – (cont.g.) • Ho many instructions can this computer be designed to perform? • 3-bit opcode  only 7 memory instructions? • 12 bits in register and input-output more! e.3. • AND memory word in address 000000001100 to 𝑨𝑪.

• AND memory word in address 000000001100 to 𝑨𝑪.3. (AND opcode: 000) • Instruction: 0 000 000000001100 • Hexadecimal: 0 0 0 C 10/30/2013 28 . Computer Instructions – (cont.) • Ho many instructions can this computer be designed to perform? • 3-bit opcode  only 7 memory instructions? • 12 bits in register and input-output more! e.g.

3.) • ISZ opcode: 110 • Instruction: 0 110 0000 0000 0101 • Hexadecimal: 6 0 0 5 • Instruction: 1 110 0000 0000 1100 • Hexadecimal: E 0 0 C Memory Reference Instructions • 𝑰=0  first hex digit ranges from 0 to 6. • 𝑰=1  first hex digit ranges from 8 to E. Computer Instructions – (cont. 10/30/2013 29 .

) Register Reference Instructions • Instruction: 0 111 0000 0000 0101 • Hexadecimal: 7 0 0 5 • Instruction: 0 111 0000 0000 1100 • Hexadecimal: 7 0 0 C First hex digit is always 7. Computer Instructions – (cont. 10/30/2013 30 .3.

3. 10/30/2013 31 .) Input-Output Instructions • Instruction: 1 111 0000 0000 0101 • Hexadecimal: F 0 0 5 • Instruction: 1 111 0000 0000 1100 • Hexadecimal: F 0 0 C First hex digit is always F. Computer Instructions – (cont.

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control. logic. XOR must be programmed in the basic computer (Ch6). input output. Computer Instructions – (cont. • Commercial computers – Ch8. 10/30/2013 33 . • Efficiency. moving data. multiplication.3.g. shift.) Instruction Set • Completeness – Arithmetic. – e.

we will design a hardwired control unit. • Hardwired control vs. microprogrammed control (ch7). • For now. 10/30/2013 34 .4. Timing and Control • Timing of all registers and flip-flops is controlled by a master clock generator. • But the clock doesn’t change the state of a register unless the register is enabled by a control signal generated in a control unit.

• The timing sequence in the control unit can be easily generated by means of counters or shift registers. 10/30/2013 35 . Timing and Control – (cont.) • The control unit that supervises the operations in a digital system would normally consists of timing signals that determine the time sequence in which the operations are executed must know operation.4.

) Simple Examples 1. • This word-time signal can be generated by means of a counter that counts the required number of pulses. Word-time Generation for Serial Operation • The control unit in a serial operation must generate a word-time that stays on for a number of pulses equal to the number of bits in the shift register.4. Timing and Control – (cont. 10/30/2013 36 .

4.) 1. Word-time Generation for Serial Operation • If the word-time signal must stay on for eight clock pulses To shift register 10/30/2013 Notice that the flip-flops are negative-edge-triggered 37 . Timing and Control – (cont.

) 2.4. Timing-Signals Generation for Parallel Mode • The control units in systems the operate in parallel mode must generate timing signals that stay on for only one clock pulse. 10/30/2013 38 . but these timing signals must be distinguished from each other. Timing and Control – (cont. • These signals can be generated by a circular shift register. or a counter with a decoder.

4. Timing and Control – (cont.)
2. Timing-Signals Generation for Parallel Mode • Ring Counter: circular shift register with one flipflop set to one at a time.
initial value 1000

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Notice that the flip-flops are negative-edge-triggered

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4. Timing and Control – (cont.)
2. Timing-Signals Generation for Parallel Mode • Counter that goes through distinct states, with
decoder to decode the states.

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4. Timing and Control – (cont.)
2. Timing-Signals Generation for Parallel Mode • The timing signals when enabled by the clock pulse, can be used to generate multiple-phase clock pulses. • ANDing 𝑻𝒐 with 𝑪𝑷 produces a clock pulse at 1/4th the frequency of the master-clock pulses.

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4. Timing and Control – (cont.) Basic Computer Control Unit • Two decoders • Sequence counter • Control logic gates 10/30/2013 42 .

𝑻𝟐 . Timing and Control – (cont. 𝑺𝑪 is cleared if 𝑫𝟑 is active. then at 𝑻𝟒 . In register-transfer logic statement: 𝑫𝟑 𝑻𝟒 : 𝑺𝑪 ← 𝟎 10/30/2013 43 . 𝑻𝟑 .) Basic Computer Control Unit • Counter can be incremented or cleared.4. Example Suppose we want the timing sequence 𝑻𝒐 . 𝑻𝟏 .

) Basic Computer Control Unit • Initially. • 𝑺𝑪 increments with every cycle resulting the sequence: 10/30/2013 44 .4. Timing and Control – (cont. 𝑺𝑪 is cleared triggering only registers whose control inputs are connected to 𝑻𝒐 .

4.) Basic Computer Control Unit • 𝑫𝟑 𝑻𝟒 : 𝑺𝑪 ← 𝟎 How? 10/30/2013 45 . Timing and Control – (cont.

• Most commercial computer provide “wait cycles” in the processor.) Basic Computer Control Unit • A memory read/write cycle will be initiated with the rising edge of a timing signal.4. 10/30/2013 46 . and that edge will be used to load memory word into a register). • It will be assumed that the memory cycle time is less than the clock cycle time (so that read/write will finish before the next rising edge. Timing and Control – (cont.

5. Instruction Cycle • A program (sequence of instructions) residing in memory is executed by going through a cycle for each instruction. 10/30/2013 47 . which in turn. is divided into a sequence of subcycles or phases.

Decode the instruction. Instruction Cycle – (cont. Execute the instruction.) • In the basic computer. Read the effective address if needed. 2. • Upon completing step 4. each instruction goes through these phases: 1. 10/30/2013 48 . control goes back to step 1 and so on until a HALT instruction is encountered.5. 3. Fetch instruction from memory. 4.

Instruction Cycle – (cont.) Fetch and Decode • What happens? • The microoperations can be specified by the following register-transfer statements: • How are these implemented? 10/30/2013 49 .5.

SC increments after each clock pulse.5. To produce the sequence 𝑻𝟎 .… 10/30/2013 50 . 𝑻𝟐 . Instruction Cycle – (cont.) Fetch and Decode Remember. 𝑻𝟏 .

• Control unit examines opcode and Decoder output 𝑫𝟕 distinguished memory-reference instructions from the other two types. 10/30/2013 51 .5. Instruction Cycle – (cont.) Determining the Type of Instruction • During 𝑻𝟑 .

) Instruction Cycle (Initial configuration) 10/30/2013 52 .5. Instruction Cycle – (cont.

) Instruction Cycle (Initial configuration) • ? 10/30/2013 53 . Instruction Cycle – (cont.5.

5.) Instruction Cycle (Initial configuration) 10/30/2013 54 . Instruction Cycle – (cont.

• Let the bits of 𝑰𝑹 be 𝑩𝟏𝟏 𝑩𝟏𝟎 …. Instruction Cycle – (cont.) Register-Reference Instructions • 𝑫𝟕 = 𝟏 and 𝑰 = 𝟎. 10/30/2013 55 . at clock transition 𝑻𝟑 • 𝑰𝑹(0-11) specify one of 12 instructions. then all control functions can be simply denoted by 𝒓𝑩𝒊 . 𝑩𝟎 .5. • Since the control function is distinguished by one of the bits in 𝑰𝑹(0-11). • Let the Boolean relation 𝑫𝟕 𝑰′ 𝑻𝟑 = 𝐫.

) Register-Reference Instructions • Example: CLA Hex.5. Instruction Cycle – (cont. 7 8 0 0 Binary 0 111 1000 000 000 𝑰’ 𝑫𝟕 𝑩𝟏𝟏  Control function that initiates microoperations for this instruction is: ′ 𝑫𝟕 𝑰 𝑻𝟑 𝑩𝟏𝟏 = 𝒓𝑩𝟏𝟏 10/30/2013 the 56 .

Instruction Cycle – (cont.) Register-Reference Instructions • ?? 10/30/2013 57 .5.

the start flip-flip must be set manually.) Register-Reference Instructions • 𝑺𝑪 is cleared after the execution of each instruction initiating 𝑻𝟎 (fetch) that causes a new cycle.5. • After a HALT. 10/30/2013 58 . Instruction Cycle – (cont.

Selected Problems • To be selected! 10/30/2013 59 .

Reading: Chapter 5: sections 1-5.Next Lecture Continuation of Basic Computer Organization and Design. Assignment . 10/30/2013 60 .

2006. M.kr/ ch05 . Prentice Hall.References .kut. -http://microcom.Digital Design.ac. Morris Mano.God bless Google and Wiki! 10/30/2013 61 . 4th ed.