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PROGRAMMABLE SYNCHRONOUS DC/DC CONVERTER, DUAL LOW DROPOUT REGULATOR CONTROLLER

October 25, 1999

SC1164/5

TEL:805-498-2111 FAX:805-498-3804 WEB:http://www.semtech.com

DESCRIPTION
The SC1164/5 combines a synchronous voltage mode controller with two low-dropout linear regulators providing most of the circuitry necessary to implement three DC/DC converters for powering advanced ® microprocessors such as Pentium II. The SC1164/5 switching section features an integrated 5 bit D/A converter, pulse by pulse current limiting, integrated power good signaling, and logic compatible shutdown. The SC1164/5 switching section operates at a fixed frequency of 200kHz, providing an optimum compromise between size, efficiency and cost in the intended application areas. The integrated D/A converter provides programmability of output voltage from 2.0V to 3.5V in 100mV increments and 1.30V to 2.05V in 50mV increments with no external components. The SC1164/5 linear sections are low dropout regulators. The SC1164 supplies 1.5V for GTL bus and 2.5V for non-GTL I/O. For the SC1165 both LDO’s are adjustable.

FEATURES • Synchronous design, enables no heatsink solution • 95% efficiency (switching section) • 5 bit DAC for output programmability • On chip power good function • Designed for Intel Pentium® ll requirements • 1.5V, 2.5V or Adj. @ 1% for linear section APPLICATIONS • Pentium® ll or Deschutes microprocessor supplies • Flexible motherboards • 1.3V to 3.5V microprocessor supplies • Programmable triple power supplies

ORDERING INFORMATION
Part Number
(1)

Package

Linear Voltage

Temp. Range (TJ)

SC1164CSW SC1165CSW

SO-24 SO-24

1.5V/2.5V 0° to 125°C Adj. 0° to 125°C

Note: (1) Add suffix ‘TR’ for tape and reel.

PIN CONFIGURATION

BLOCK DIAGRAM

REF.

Top View

AGND GATE1 LDOS1 LDOS2 VCC OVP PWRGOOD CSCS+ PGNDH DH PGNDL

1 2 3 4 5 6 7 8 9 10 11 12

24 23 22 21 20 19 18 17 16 15 14 13

GATE2 LDOV VID0 VID1 VID2 VID3 VID4 VOSENSE EN BSTH BSTL DL

FET CONTROLLER 2.5V/ADJ.

1.265V REF.

FET CONTROLLER 1.5V/ADJ.

(24 Pin SOIC)
LDOV

Pentium is a registered trademark of Intel Corporation

1

© 1999 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 This datasheet has been downloaded from http://www.digchip.com at this page

5 8 1 0.25V. © 1999 SEMTECH CORP. 0mV < (CS+-CS-) < 60mV. TA = 25°C PARAMETER Switching Section Output Voltage Supply Voltage Supply Current Load Regulation Line Regulation Current Limit Voltage Oscillator Frequency Oscillator Max Duty Cycle Peak DH Sink/Source Current Peak DL Sink/Source Current Output Voltage Tempco Gain (AOL) OVP threshold voltage OVP source current Power good threshold voltage Dead time Linear Sections Quiescent current Output Voltage (LDO1 SC1164) Output Voltage (LDO2 SC1164) Reference Voltage (SC1165) Feedback Pin Bias Current (SC1165) Gain (AOL) Load Regulation Line Regulation Output Impedance Notes: (1) See Output Voltage table.0V 55 175 90 1 1 85 225 65 35 120 10 85 50 115 100 LDOV = 12V LDOS (1.3 0.5V.75V to 5.8A to 15A MIN TYP MAX UNITS See Note 1.278 10 90 0.515 1.500 2.5V.525 1.4V to 12.PROGRAMMABLE SYNCHRONOUS DC/DC CONVERTER. 1999 SC1164/5 ABSOLUTE MAXIMUM RATINGS Parameter VCC to GND PGND to GND BST to GND Operating Temperature Range Junction Temperature Range Storage Temperature Range Lead Temperature (Soldering) 10 seconds Thermal Impedance Junction to Ambient Thermal Impedance Junction to Case Symbol VCC Maximum -0. CONDITIONS IO = 2A VCC VCC = 5.475 2. DH-PGNDH = 3V BSTL-DL = 4.2) to GATE (1.2) (2) IO = 0 to 8A 5 2.3 1 2 652 MITCHELL ROAD NEWBURY PARK CA 91320 .265 1. DUAL LOW DROPOUT REGULATOR CONTROLLER October 25.252 1. VOSENSE = VO.3 to +15 0 to +70 0 to +125 -65 to +150 300 80 25 Units V V V °C °C °C °C °C/W °C/W TA TJ TSTG TL θJA θJC ELECTRICAL CHARACTERISTICS Unless specified: VCC = 4. LDOV = 11.0V IO = 0.3 to +7 ±1 -0. GND = PGND = 0V.500 1. (2) In application circuit. DL-PGNDL = 3V VOSENSE to VO VOVP = 3. 4.485 1.5 70 200 95 7 15 V mA % % mV kHz % A A o ppm/ C dB % mA % ns mA V V V uA dB % % KΩ BSTH-DH = 4.6V.

DUAL LOW DROPOUT REGULATOR CONTROLLER October 25. high if VO within 10% of setpoint Current Sense Input (negative) Current Sense Input (positive) Power Ground for High Side Switch High Side Driver Output Power Ground for Low Side Switch Low Side Driver Output Supply for Low Side Driver Supply for High Side Driver Logic low shuts down the converter. 3 © 1999 SEMTECH CORP. 1999 SC1164/5 PIN DESCRIPTION Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Pin Name AGND GATE1 LDOS1 LDOS2 VCC OVP PWRGOOD CSCS+ PGNDH DH PGNDL DL BSTL BSTH (1) EN VOSENSE (1) VID4 (1) VID3 (1) VID2 (1) VID1 (1) VID0 LDOV GATE2 (1) Pin Function Small Signal Analog and Digital Ground Gate Drive Output LDO1 Sense Input for LDO1 Sense Input for LDO2 Input Voltage High Signal out if VO>setpoint +20% Open collector logic output. 652 MITCHELL ROAD NEWBURY PARK CA 91320 .PROGRAMMABLE SYNCHRONOUS DC/DC CONVERTER. High or open for normal operation. Top end of internal feedback chain Programming Input (MSB) Programming Input Programming Input Programming Input Programming Input (LSB) +12V for LDO section Gate Drive Output LDO2 Top View AGND GATE1 LDOS1 LDOS2 VCC OVP PWRGOOD CSCS+ PGNDH DH PGNDL 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 GATE2 LDOV VID0 VID1 VID2 VID3 VID4 VOSENSE EN BSTH BSTL DL (24 Pin SOIC) Note: (1) All logic level inputs and outputs are open collector TTL compatible.

625 1.548 2.264 3. 1999 SC1164/5 OUTPUT VOLTAGE Unless specified: VCC = 5.576 1.822 1.00V.958 3.000 2.326 1.652 2. DUAL LOW DROPOUT REGULATOR CONTROLLER October 25.527 1.030 2.019 1.450 2.878 1.400 1.700 1.050 2.450 1.060 3.468 3.142 2.332 3.136 3.000 3.479 1.827 1.530 1.800 1. 0mV < (CS+-CS-) < 60mV.162 3.550 1.500 2.234 3.428 1.100 2.600 1.400 2.448 2.060 2.300 1.950 2.350 1.970 2.929 1.850 1.430 TYP 1.570 UNITS 4 © 1999 SEMTECH CORP.754 2. TA = 25oC PARAMETER Output Voltage CONDITIONS IO = 2A in Application Circuit VID 43210 01111 01110 01101 01100 01011 01010 01001 01000 00111 00110 00101 00100 00011 00010 00001 00000 11111 11110 11101 11100 11011 11010 11001 11000 10111 10110 10101 10100 10011 10010 10001 10000 MIN 1.274 1.726 1.979 2.624 1.921 1.000 2.773 1. VOSENSE = VO.254 2.PROGRAMMABLE SYNCHRONOUS DC/DC CONVERTER.724 1.900 3.081 2.776 1.377 1.744 2.600 2.500 MAX 1.646 2.244 2.940 3.323 1.856 2.750 1.058 2.940 2.100 3.300 2.400 3.900 1.675 1.346 2.300 3.352 2.871 1.366 3.675 1. GND = PGND = 0V.372 1.650 1.700 2.038 3. 652 MITCHELL ROAD NEWBURY PARK CA 91320 .573 1.550 2.500 1.800 2.200 3.470 1.842 2.156 2.200 2.421 1.

R14 AND R14 ARE NOT REQUIRED.1uF OVP VID0 VID1 VID2 VID3 VID4 SC1164/5CSW R12 * Q3 BUK556 VLIN1 PWRGD + + R15 * R17 ** 100k VINLIN (NORMALLY 3. R12. CONNECT LDOS1 (PIN3) DIRECTLY TO VLIN1 TO GENERATE 2. R18 REQUIRED IF VINLIN CAN BE PRESENT WITHOUT 12V BEING PRESENT.00k 2. PROGRAMMABLE SYNCHRONOUS DC/DC CONVERTER. R13.1uF APPLICATION CIRCUIT C2 1500uF VCC_CORE EN 16 C5 0.1uF U1 5 VCC CS+ CSVO SENSE PWRGOOD VID4 OVP VID0 VID1 VID2 + R16 TBD C13 1.1uF 12 24 2 4 1 + + + + C18 0.5V OUTPUT.12V October 25. 1999 5V + R1 10 0. C3 1500uF 9 8 17 7 18 4uH 15 11 10 13 14 23 3 R13 * C14 1500uF C16 1500uF Q2 BUK556 L1 R4 5mOhm C15 1500uF C17 1500uF Q1 BUK556 6 22 21 20 19 VID3 EN AGND PGNDH DL BSTL VDD LDOS1 PGNDL GATE2 GATE1 LDOS2 DH BSTH C1 0.32k R6 R5 © 1999 SEMTECH CORP. * SEE "SETTING LDO OUTPUT VOLTAGE" TABLE ** R17. DUAL LOW DROPOUT REGULATOR CONTROLLER R18 ** 100k SC1164/5 5 652 MITCHELL ROAD NEWBURY PARK CA 91320 . CONNECT LDOS2 (PIN4) DIRECTLY TO VLIN2 TO GENERATE 1.5V OUTPUT.3V) C11 330uF C12 330uF VLIN2 + + R14 * Q4 BUK556 C9 330uF + + C21 C22 330uF C10 330uF 330uF NOTE: FOR SC1164.

652 MITCHELL ROAD NEWBURY PARK CA 91320 .3V 4µH See notes 5mΩ 2. 1%.PROGRAMMABLE SYNCHRONOUS DC/DC CONVERTER.265 ⋅ (R A + R B ) + (IFB ⋅ R A ) RB Where : IFB = Feedback pin bias current R A = Top feedback resistor R B = Bottom feedback resistor See layout diagram for clarification R A and R B must be low enough so that the (IFB ⋅ R A ) term does not cause significant error 6 © 1999 SEMTECH CORP. 1/8W 1%.50V R12 (R14) 105Ω 105Ω 102Ω 100Ω 100Ω 100Ω 100Ω RA R13 (R15) 182Ω 169Ω 147Ω 130Ω 121Ω 97.Q2 OAR-1 Series MV-GX or equiv. DUAL LOW DROPOUT REGULATOR CONTROLLER October 25.Q3.32kΩ. 5%. C21.C5.1/8W SC1164/5CSW SETTING LDO OUTPUT VOLTAGE RB VOUT LDO1 (LDO2) 3. 1%. 1/8W 100kΩ.Q2. 1/8W 10Ω. 1/8W 1kΩ.45V 3. Low ESR Notes C1. C22 L1 Q1.C3.R18 U1 1500µF/6.C14C17 C9-C12. Q4 R4 R5 R6 R1 R12 R13 R14 R15 R17. Reference 4 6 6 1 4 1 1 1 1 1 1 1 1 2 1 Part/Description Vendor Various SANYO Various 8 Turns 16AWG on MICROMETALS T50-52D core See notes IRC Various Various Various Various Various Various Various Various SEMTECH See Table Below (Not required for SC1164) See Table Below (Not required for SC1164) See Table Below (Not required for SC1164) See Table Below (Not required for SC1164) Required if Voltage is applied to the linear FET(s) without 12V applied to SC1164/5 FET selection requires trade-off between efficiency and cost. 1/8W 1%. 1/8W 1%. 1/8W 1%.80V 2.10V 2.C13.1µF Ceramic 18 C2. 1999 SC1164/5 MATERIALS LIST Qty.6Ω 18. Absolute maximum RDS(ON) = 22 mΩ for Q1. 5%.90V 2.3V 330µF/6.C 0.7Ω VOUT = 1.50V 1.30V 3.

Io=10A Transient Response Vo=2.5V 95% Typical Efficiency at Vo=2.5V Sync Lo Rds 80% 2.5V Typical Efficiency at Vo=2.5V Sync Lo Rds 80% 2.5V Sync 2.8V 95% 90% 90% Efficiency Efficiency 85% 85% 80% 2.5V Std 2.0V Std 2.8V.5V Std 3.8V Sync 2.8V Sync Lo Rds 75% 75% 70% 0 2 4 6 8 Io (Amps) 10 12 14 16 70% 0 2 4 6 8 Io (Amps) 10 12 14 16 Typical Efficiency at Vo=3. 652 MITCHELL ROAD NEWBURY PARK CA 91320 .PROGRAMMABLE SYNCHRONOUS DC/DC CONVERTER.0V Sync Lo Rds 75% 75% 70% 0 2 4 6 8 Io (Amps) 10 12 14 16 70% 0 2 4 6 8 Io (Amps) 10 12 14 16 Typical Efficiency at Vo=2. Vo=2. 1999 95% 95% SC1164/5 90% 90% Efficiency Efficiency 85% 85% 80% 3.0V Sync 2. DUAL LOW DROPOUT REGULATOR CONTROLLER October 25.5V Sync 3.8V.0V Typical Ripple. Io=300mA to 10A 7 © 1999 SEMTECH CORP.8V Std 2.

The connection between the junction of Q1. the Top FET (Q1) and the Bottom FET (Q2) must be kept as small as possible. For SC1164. 1999 SC1164/5 LAYOUT GUIDELINES Careful attention to layout requirements are necessary for successful implementation of the SC1164/5 PWM controller. 3). Isolated or semi-isolated areas of the ground plane may be deliberately introduced to constrain ground currents to particular areas.1uF 7 8 9 10 11 12 AGND GATE1 LDOS1 LDOS2 VCC OVP PWRGOOD CSCS+ PGNDH DH PGNDL GATE2 LDVO VID0 VID1 VID2 VID3 VID4 VOSENSE EN BSTH BSTL DL 24 23 22 Cin 21 20 19 18 17 16 15 14 13 Q2 Cout 4uH + Q1 + 1. Since this connection has fast voltage transitions. High currents switching at 200kHz are present in the application and their effect on ground plane voltage differentials must be understood and minimized.1uF 5 6 0. LDOS1 connects to Vo Lin1. 2). RB1 and RB2 are not required. The connection between the output inductor and the sense resistor should be a wide trace or copper area. for example the input capacitor and bottom FET ground. RA2. It should be as short as practical. there are no fast voltage or current transitions in this connection and length is not so important. The high power parts of the circuit should be laid out first. Minimizing this loop area will a) reduce EMI.32k SC1164/5 RA1 5V Q3 + Cin Lin RB1 Cout Lin1 + Vo Lin1 Heavy lines indicate high current paths. resulting in more reliable gate switching signals. fast transition switching. however adding unnecessary impedance will reduce efficiency. This loop contains all the high current. RA1. LDOS2 connects to Vo Lin2 Vo Lin2 RA2 Q4 RB2 Cout Lin2 + Layout diagram for the SC1164/5 8 © 1999 SEMTECH CORP. A ground plane should be used.PROGRAMMABLE SYNCHRONOUS DC/DC CONVERTER. b) lower ground injection currents. DUAL LOW DROPOUT REGULATOR CONTROLLER October 25. 12V IN 5V 10 1 2 3 4 0. The loop formed by the Input Capacitor(s) (Cin). 652 MITCHELL ROAD NEWBURY PARK CA 91320 . Q2 and the output inductor should be a wide trace or copper region. 1). resulting in electrically “cleaner” grounds for the rest of the system and c) minimize source ringing. the number and position of ground plane interruptions should be such as to not unnecessarily compromise ground plane integrity.00k 5mOhm Vout 2. keeping this connection short will minimize EMI. Connections should be as wide and as short as possible to minimize loop inductance.

and connections between Cout and the load must be short. avoid pulse currents in the Cin. the Vcc pin should be decoupled directly to AGND by a 0. Q1. Q2 loop.1µF ceramic capacitor. 8) Ideally. DUAL LOW DROPOUT REGULATOR CONTROLLER October 25. the AGND pin may be connected to the ground path between the Output Capacitor(s) and the Cin. the traces running back to CS+ and CS. Q1. Q2 loop flowing in this area. Under no circumstances should AGND be returned to a ground inside the Cin. Q1. 6) Vcc for the SC1164/5 should be supplied from the SC1164/5 5V supply through a 10Ω resistor. wide copper areas to minimize inductance and resistance. The 0.on the SC1164/5 should run parallel and close to each other. trace lengths should be as short as possible. the grounds for the two LDO sections should be returned to the ground side of (one of) the output capacitor(s).pins as possible. fast transient load currents are supplied by Cout only. 5) The SC1164/5 is best placed over a quiet ground plane area. Q2 loop. The AGND pin should be connected to the ground side of (one of) the output capacitor(s). 1999 4) The Output Capacitor(s) (Cout) should be located as close to the load as possible.1µF capacitor should be mounted as close to the CS+ and CS. 652 MITCHELL ROAD NEWBURY PARK CA 91320 . 7) The Current Sense resistor and the divider across it should form as small a loop as possible. 5V + Vout + Currents in various parts of the power section 9 © 1999 SEMTECH CORP.PROGRAMMABLE SYNCHRONOUS DC/DC CONVERTER. If this is not possible. PGNDH and PGNDL should be returned to the ground plane close to the package.

3 8. The resulting power dissipation in the top FET will be: PRR = Q RR ⋅ VIN ⋅ f OSC To a first order approximation. Because of fast transient load current requirements in modern microprocessor core supplies.8 Ripple current allowance will define the minimum permitted inductor value. Too large an inductor will produce a slow current ramp rate and will cause the output capacitor to supply more of the transient load current for longer . The maximum ESR can be simply calculated from: fast enough to reduce the voltage dropped across the ESR at a faster rate than the capacitor sags. hence ensuring a good recovery from transient with no additional excursions. if we assume 100ns then: PSW = I O ⋅ V IN ⋅ 10 − 2 The choice of which to use is simply a cost/performance issue.PROGRAMMABLE SYNCHRONOUS DC/DC CONVERTER. it is reasonable to assume that the stored charge on the bottom FET body diode will be moved through the top FET as it starts to turn on. Each Capacitor Technology Low ESR Tantalum OS-CON Low ESR Aluminum C (µF) 330 330 1500 ESR (mΩ) 60 25 44 Qty.8V out at 14. so some allowance must be made. it is convenient to only consider conduction losses to determine FET suitability. PSW = IO ⋅ VIN ⋅ ( t r + t f ) ⋅ fOSC 4 L≤ R ESR C (VIN − VO ) It c) Body diode recovery losses are more difficult to estimate. the maximum allowable value of inductor can be calculated. Note that most of the output voltage ripple is produced by the inductor ripple current flowing in the output capacitor ESR. switching losses and bottom FET body diode recovery losses. 652 MITCHELL ROAD NEWBURY PARK CA 91320 .The power dissipation in the top FET is a combination of conduction losses. DUAL LOW DROPOUT REGULATOR CONTROLLER October 25.Having decided on a suitable type and value of output capacitor.2A requirement. Ripple current can be calculated from: R ESR V ≤ t It ILRIPPLE= VIN 4⋅L⋅ fOSC Where Vt = Maximum transient voltage excursion It = Transient current step For example. 6 3 5 Total C (µF) 2000 990 7500 ESR (mΩ) 10 8. but to a first approximation. with Low ESR Aluminum being the cheapest. To meet this kind of ESR level. typical FET losses would be: The calculated maximum inductor value assumes 100% duty cycle. a) Conduction losses are simply calculated as: 2 PCOND = IO ⋅ RDS( on ) ⋅ δ where δ = duty cycle ≈ VO VIN b) Switching losses can be estimated by assuming a switching time.The FETs are chosen based on several criteria with probably the most important being power dissipation and power handling capability. Choosing an inductor value of 50 to 75% of the calculated maximum will guarantee that the inductor current will ramp 10 © 1999 SEMTECH CORP. POWER FETS . 1999 SC1164/5 COMPONENT SELECTION SWITCHING SECTION OUTPUT CAPACITORS . to meet a 100mV transient limit with a 10A load step. INDUCTOR . but taking up the most space. The maximum inductor value may be calculated from: or more generally. there are three available capacitor technologies. Output capacitor ESR is therefore one of the most important criteria. the output capacitor ESR must be less than 10mΩ. the output capacitors must supply all transient load current requirements until the current in the output inductor ramps up to the new level. We must also be concerned with ripple current in the output inductor and a general rule of thumb has been to allow 10% of maximum output current as ripple current. 2. For a 5V in. TOP FET .Selection begins with the most critical component. Rqd.leading to an output voltage sag below the ESR excursion calculated above.

6 122. suitable capacitors must be chosen accordingly. power dissipation will be approximately halved and temperature rise reduced by a factor of 4. DUAL LOW DROPOUT REGULATOR CONTROLLER October 25.48 0. 2 oz printed o circuit board material.95 0.20 7.53 Package TO220 D PAK SO-8 2 SC1164/5 BUK556H 22 IRL2203 Si4410 7.since the RMS ripple current in the input capacitors may be as high as 50% of the output current.0 13. 652 MITCHELL ROAD NEWBURY PARK CA 91320 . 11 © 1999 SEMTECH CORP. thermal impedances of 40 C/W 2 o for the D PAK and 80 C/W for the SO-8 are readily achievable.4 (1) With 20 C/W Heatsink It is apparent that single SO-8 Si4410 are not adequate for this application. thermal impedance is mostly determined by the heatsink used.8 96 (1) BUK556H 49. there may be restrictions on input di/dt. there is very little voltage across it. The body diode is forced into conduction at the beginning and end of the bottom switch conduction period. Also. For the surface mount packages on double sided FR4. The corresponding temperature rise is detailed below: Temperature rise ( C) FET type Top FET (1) o Bottom FET 39.6 IRL2203 Si4410 o 31. either as extra output capacitance or. Conduction losses for the FET can be determined by: 2 ⋅ R DS ( on ) ⋅ (1 − δ ) PCOND = I O INPUT CAPACITORS . more usually.0 24. additional input capacitors.5 Package TO220 D PAK SO-8 2 BUK556H 22 IRL2203 Si4410 Each of the package types has a characteristic thermal impedance.PROGRAMMABLE SYNCHRONOUS DC/DC CONVERTER.0 13.79 1. but by using parallel pairs in each position. for the TO-220 package.Bottom FET losses are almost entirely due to conduction. during fast load transients. These restrictions require useable energy storage within the converter circuitry. so when the FET turns on and off. resulting in low switching losses. Choosing low ESR input capacitors will help maximize ripple rating for a given size. 1999 FET type RDS(on) (mΩ) PD (W) 2.62 1.5 BOTTOM FET . For the example above: FET type RDS(on) (mΩ) PD (W) 1.

PROGRAMMABLE SYNCHRONOUS DC/DC CONVERTER. DUAL LOW DROPOUT REGULATOR CONTROLLER October 25. 652 MITCHELL ROAD NEWBURY PARK CA 91320 . 1999 SC1164/5 OUTLINE DRAWING .SO-24 JEDEC MS-013AD B17104B ECN 99-667 12 © 1999 SEMTECH CORP.