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Zirconium Oxide Based Gate Dielectrics with Equivalent Oxide Thickness of Less Than 1.

0 nm and Performance of Submicron MOSFET using a Nitride Gate Replacement Process


Yanjun Ma, Yoshi Ono, Lisa Stecker, David R. Evans, and S.T. Hsu
Sharp Laboratories of America, 5700 NW Pacific Rim Blvd, Camas, WA 98607

Abstract
Zirconium oxide is investigated as a possible replacement for Si02 gate dielectric thinner than 1.5nm. A maximum capacitance of 31 fF/pm2 (measured in accumulation at -2V) is obtained for a 3.9nm Zr02 film with leakage current of -ImA/cm2 at -l.OV, yielding an equivalent oxide thickness of less than 1.0 nm. Doping with A1 produced amorphous films with better uniformity, but slightly lower dielectric constant. Submicron MOSFETs with TiN gate electrode and Zr02 or A1 doped Zr02 gate dielectrics have been fabricated and good device performance is obtained.

Introduction
Because of high direct tunneling currents, Si02 thinner than 1.5 nm cannot be used as the gate dielectric of CMOS devices. Currently there is intense effort in the search for the replacement of Si02, with Ti02 and Ta205attracting the most attentionrl]. However, these oxides are not stable on Si surfaces and there is a tendency for forming a thick interfacial Si02 layer. This is exacerbated by the necessity for a high temperature, post deposition anneal. Thus achieving an equivalent Si02 thickness (EOT) of less than 1.5 nm has proved to be very difficult. ZrO2 is attractive because of its high dielectric constant (-25), wide energy bandgap (-5 eV), and high stability. More importantly there are reports that Zr02 is stable on Si surfaces[2]. In this work we report preliminary results on zirconium oxide based films. A record maximum accumulation capacitance about 3 1 fF/pm2 with a leakage current of -1 mA/cm2 has been achieved for a 3.9 nm sputtered Zr02 film with an effective dielectric constant of 18.5. A1 doping (-25% by XPS) is used to increase the crystallization temperature of the gate dielectric with slight reduction in dielectric constant. Submicron MOSFETs have been fabricated with the Zr02 and Zr-Al-0 gate dielectrics with good characteristics.

be necessary to reduce the leakage current of deposited films. As shown in Fig.1, post deposition anneals at 400-500C are sufficient to achieve reduced leakage current. This is drastically different than the case of TiO2, where anneals at more than 750C are usually needed to reduce the leakage current[3]. This may be due to the stability of Zr02 compared to Ti02 where oxygen defects can easily form. Physical thickness of the film is evaluated by spectroscopic ellipsometry. While undoped Zr02 film exhibits crystallinity after only a 400C anneal, as shown in Figure 2, A1 doping prevented the crystallization after anneals of up to 800C. In addition, film uniformity appears to be improved with AI doping. An Al/TiN top electrode is then deposited by sputtering and patterned to make lOOxl00 pm2 capacitors for electrical testing. XPS investigation of AI and Zr chemical states of the doped film are consistent with the presence of A1203and ZrO2 local environments. MOS transistors having the high-k gate dielectrics were processed using a nitride gate replacement process[4], where conventional source/drain with LDD structure were formed with a nitride dummy gate. After premetal dielectric fill and CMP, the nitride dummy gate and the sacrificial gate oxide was removed and the Zr02 and Al-Zr-0 gate dielectrics were sputter-deposited. We used a 50nm thick sputtered TiN for the gate electrode and the final contact is made with Al. The maximum process temperature after gate stack formation is 400C.

Results and Discussion


Figure 3 showed high frequency CV curves for two ZrOz films after post deposition anneals in forming gas and O2 respectively. As can be seen a maximum accumulation capacitance of -31 fF/pm2 is obtained for a 3.9nm film. This corresponds to a classical dielectric thickness (CDT= E ~ I o ~ / C ) of 1.1 nm. Including the quantum mechanical correction (estimated to be about 0.3 nm), an EOT less than I.Onm and an effective dielectric constant of -18 are obtained. Since the bulk dielectric constant is estimated to be -25, we can estimated that there is at most a 2A Si02 layer at the Zr02/Si interface. The O2 anneal produced a film having a slightly lower effective dielectric constant (-16) than FG anneal. This may be explained by the presence of an additional 2A thick oxide layer at the interface. The leakage characteristics of the films is shown by the IV curves plotted in Figure 4

Experiment
Zr02 films were prepared by sputtering a Zr target in a mixture of oxygen and argon at room temperature. A1 doping is achieved by co-sputtering using an AI target. Post deposition anneal in either oxygen or inert gases is found to

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where the 3.9nm film showed a leakage current of about 1 mA/cm2 at the likely operating voltage of -lV. In Figure 5 we plotted the CV results for A1 doped Zr02 films. In this case, a maximum capacitance of -28 fF/um2 is obtained for a 3nm film, yielding an effective dielectric constant of about 11. Figure 6 showed the IV curves for these films. For the 3nm film, the gate leakage current is -0.5 A/cm2 at -1.5 V and -0.1 Ncm2 at the likely operating voltage of -1 V. The leakage currents are about the same for doped and undoped Zr02 films of similar thickness. The effective dielectric constant as a function of film thickness is plotted in Figure 7. The dielectric constants of doped films are lower than those of undoped films. There is a slight dependence of effective dielectric constant of the film as a function of film thickness. As shown in Fig. 8 the leakage current on n-type substrate is about lox larger than films of similar thickness on p-type substrate. The temperature dependence of the leakage current is also much larger. This suggests that the energy barrier for electron conduction is much smaller than that for hole conduction. In fact it has been reported that the electron affinity of pure Zr02 is about 3.5 eV[5]. This will produce an electron barrier of about 0.6 eV and a hole barrier of 3.3 eV. A1 doped ZrO2 film is expected to have a lower electron affinity and more symmetric barriers for electrons and holes.[5] In reliability tests, the polarity of the stress and the substrate type made a significant difference. Under gate injection, Fig. 9, classic breakdown behavior is seen near 3V and after stressing to below breakdown, no signs of stress induced leakage current (SILC) can be seen. On the other hand, Fig. 10, substrate injection on n-type substrates showed significant SILC but no obvious dielectric breakdown. The SILC continuously increases until saturation. At voltages close to 6V, signs of breakdown appear but subsequent voltage ramps show the saturated SILC with breakdowns reFor a occurring at nearly the same voltage range. preliminary reliability evaluation, we defined one fail criterion as the SILC current reaching lox the initial current. The time to fail distribution for constant voltage testing is seen in Fig. 11 fit to a Weibull distribution. Because of the different breakdown behaviors, it is difficult to predict the projected lifetime of these films. There is also a slight hysteresis of -5OmeV in the CV of these films, indicating the presence of charge trapping in the film. The presence of electron traps is not surprising since the dielectric films were made using sputtering. With anneal, the hysteresis can be reduced but not eliminated in our anneal studies. PMOS transistor characteristics with Al-Zr-0 gate dielectric were shown in Figs. 12 and 13. Good characteristics were achieved, demonstrating the feasibility of integrating Zr-Al-0 gate dielectrics in CMOS process. The hole mobility of the devices with the Al-Zr-0 gate dielectric is compared with Si02 gate dielectric[4]. The hole mobility is about 15% lower than predicted by the universal

curve, but is similar to a PMOS device made of TiN/Ta205 gate stack[6]. The thickness of the Zr-Al-0 gate dielectrics is about 5.5nm with a C,,, measured at accumulation of more than 20 fF/pm2, yielding a CDT-1.7nm and an EOT-1.4nm. Note that the gate dielectric is deposited by sputtering into a trench, there will be non-uniformity due to the step coverage issue. TEM measurement indicates that the Al-Zr-0 film thickness at the edge of the gate is about 3.4nm. So CVD deposition method will be needed to use this process. In summary, Zr02 film is a promising candidate for replacing Si02 as the gate dielectric below 1.5nm. There are still issues that need to be resolved before it can be implemented in production.

References
[ l ] Ultrathin Si02 and high-k materials for ULSI Gate dielectrics, ed. H.R. Huff, C.A. Richter, M.L. Green, G. Lucovsky, and T. Hattori, (MRS, Warrendale, PA, 1999). [2] R. B. Beyers, Ph.D thesis, Stanford U. (1989). [3] Y.Ma, Y. Ono, and S.T. Hsu, Deposition and Treatment of Ti02 as an alternative for Ultrathin Gate Dielectrics, in Ref. [l], p355. [4] Y. Ma, D.R. Evans, T. Nguyen, Y. Ono, and S.T. Hsu, Fabrication and Characterization of sub-0.25pm Copper Gate, IEEE EDL 20, 251 (1999). [SI P. Odier and J.P. Loup, Study of electronic minority defects in stabilised zirconia by thermal emission,of electrons, in Science and Technology of Zirconia, ed. A.H. Heuer and L.W. Hobbs, p380 (Amer. Ceramic SOC,1981). [ 6 ] A. Chatterjee, et al, CMOS Metal Replacement Gate Transistors using Ta Pentoxide Gate Insulator, IEDM Tech. Digest, p777, (1998).
I

-3

-2 V g ( V )

-1

Fig.1. I-V curves of as-deposited and annealed (5OOOC 30s Oz) Zr-AI-0 films.

200
150

100 -

50

0 20

30

40 50 60 2 theta (degree)

70

Fig.2. X-ray diffraction results of ZrOz and AI doped Zr-0 films of about 30nm thick after 800C anneal for 10s.

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5
(U

30
25 20 15

l.E-01

39 A FG anneal

s 1.o

E 1.E-03
c n

-1 .E-05 1.E-07 l.E-09 -2

10 5 0
7

-1.5 -1 -0.5 Gate Voltage (V)

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-1 .o

0.0

vg (VI
Figure 3. High frequency (100KHz) CV curves for ZrOz films after forming gas (450C) and oxygen (400C) anneal.

Fig. 6. Accumulation IV characteristics of the Zr-AI-0 films shown in Fig.5.

25

20
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-?1.E03
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cv E

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50 Film Thickness (A)

75

Figure 4. Corresponding IV results of the films shown in Figure. 3.


. . _ .

Fig.7. Effective dielectric constant as a function of film thickness. AI doped films (small diamonds) have a smaller dielectric constant than undoped films after forming gas (squares) or 400C 0 2 anneal (triangles). They are calculated assuming a quantum correction of 3A for all films, EDC=~.~*T/(E,JC,,,-~).

1000

1 +3nm,

10
0
0.1

I
0 100 200 Temperature ("C)

1
300

-2

-1

v,

Fig. 5 . High frequency CV characteristics of Zr-AI-0 films on p-type substrate. Post deposition anneals were done at 400C.

Fig. 8. Temperature dependence of leakage current for Zr-AI-0 films on n(@1.5V) and p-type (0-1.W)substrate.

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2I

1.E-01
after breakdown

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h

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r

-3

-2.5

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Figure 9. Stress induced leakage measurement of an AI doped Zr02 film (3.9nm) on a p-type substrate.

vg (V)
Fig. 12. Gate characteristics of a 0.6pmxlprn PMOSFET withZr-AI-0 gate dielectrics and TIN gate electrode. Vt=-0.42V and STS=72 mV for this transistor.

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Figure 10. Stress induced leakage current measurement for a AI doped Zr02 film (-4.5nm) on n-type substrate. 21

Fig.13. Drain characteristics of a 0.6pmxlpm PMOSFET transistor shown in Figure 12.

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1

0.1
10
Time

10

100 to Fail (s)

1000

10000

6eff (MV/cm)
Figure 14. Comparison of hole mobility of TIN gate electrode devices with S O l and AI-Zr-0 gate dielectrics.

Figure 11. Time-to-Fail distribution for IOOprn x 100prn N-type substrate ZrOl capacitors

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