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Freescale Semiconductor Data Sheet: Technical Data

Document Number: KL25P80M48SF0 Rev. 3, 9/19/2012

KL25 Sub-Family Data Sheet

KL25P80M48SF0

Supports the following: MKL25Z32VFM4, MKL25Z64VFM4, MKL25Z128VFM4, MKL25Z32VFT4, MKL25Z64VFT4, MKL25Z128VFT4, MKL25Z32VLH4, MKL25Z64VLH4, MKL25Z128VLH4, MKL25Z32VLK4, MKL25Z64VLK4, and MKL25Z128VLK4
Features • Operating Characteristics – Voltage range: 1.71 to 3.6 V – Flash write voltage range: 1.71 to 3.6 V – Temperature range (ambient): -40 to 105°C • Performance – Up to 48 MHz ARM® Cortex-M0+ core • Memories and memory interfaces – Up to 128 KB program flash memory – Up to 16 KB RAM • Clocks – 32 kHz to 40 kHz or 3 MHz to 32 MHz crystal oscillator – Multi-purpose clock source • System peripherals – Nine low-power modes to provide power optimization based on application requirements – 4-channel DMA controller, supporting up to 63 request sources – COP Software watchdog – Low-leakage wakeup unit – SWD interface and Micro Trace buffer – Bit Manipulation Engine (BME) • Security and integrity modules – 80-bit unique identification (ID) number per chip • Human-machine interface – Low-power hardware touch sensor interface (TSI) – General-purpose input/output • Analog modules – 16-bit SAR ADC – 12-bit DAC – Analog comparator (CMP) containing a 6-bit DAC and programmable reference input • Timers – Six channel Timer/PWM (TPM) – Two 2-channel Timer/PWM (TPM) – Periodic interrupt timers – 16-bit low-power timer (LPTMR) – Real-time clock • Communication interfaces – USB full-/low-speed On-the-Go controller with onchip transceiver and 5 V to 3.3 V regulator – Two 8-bit SPI modules – Two I2C modules – One low power UART module – Two UART modules

Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © 2012 Freescale Semiconductor, Inc.

Table of Contents
1 Ordering parts...........................................................................3 1.1 Determining valid orderable parts......................................3 2 Part identification......................................................................3 2.1 Description.........................................................................3 2.2 Format...............................................................................3 2.3 Fields.................................................................................3 2.4 Example............................................................................4 3 Terminology and guidelines......................................................4 3.1 Definition: Operating requirement......................................4 3.2 Definition: Operating behavior...........................................4 3.3 Definition: Attribute............................................................5 3.4 Definition: Rating...............................................................5 3.5 Result of exceeding a rating..............................................6 3.6 Relationship between ratings and operating requirements......................................................................6 3.7 Guidelines for ratings and operating requirements............7 3.8 Definition: Typical value.....................................................7 3.9 Typical Value Conditions...................................................8 4 Ratings......................................................................................8 4.1 Thermal handling ratings...................................................8 4.2 Moisture handling ratings..................................................9 4.3 ESD handling ratings.........................................................9 4.4 Voltage and current operating ratings...............................9 5 General.....................................................................................9 5.1 AC electrical characteristics..............................................10 5.2 Nonswitching electrical specifications...............................10 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 5.2.7 5.2.8 Voltage and current operating requirements.........10 LVD and POR operating requirements.................11 Voltage and current operating behaviors..............12 Power mode transition operating behaviors..........13 Power consumption operating behaviors..............13 EMC radiated emissions operating behaviors.......20 Designing with radiated emissions in mind...........21 Capacitance attributes..........................................21 5.3.1 5.3.2 Device clock specifications...................................21 General Switching Specifications..........................22 5.4 Thermal specifications.......................................................22 5.4.1 5.4.2 Thermal operating requirements...........................22 Thermal attributes.................................................22

6 Peripheral operating requirements and behaviors....................23 6.1 Core modules....................................................................23 6.1.1 SWD Electricals ...................................................23

6.2 System modules................................................................25 6.3 Clock modules...................................................................25 6.3.1 6.3.2 MCG specifications...............................................25 Oscillator electrical specifications.........................27

6.4 Memories and memory interfaces.....................................29 6.4.1 Flash electrical specifications................................29

6.5 Security and integrity modules..........................................30 6.6 Analog...............................................................................31 6.6.1 6.6.2 6.6.3 ADC electrical specifications.................................31 CMP and 6-bit DAC electrical specifications.........35 12-bit DAC electrical characteristics.....................36

6.7 Timers................................................................................39 6.8 Communication interfaces.................................................39 6.8.1 6.8.2 6.8.3 6.8.4 6.8.5 USB electrical specifications.................................39 USB VREG electrical specifications......................39 SPI switching specifications..................................40 I2C.........................................................................44 UART....................................................................44

6.9 Human-machine interfaces (HMI)......................................45 6.9.1 TSI electrical specifications...................................45

7 Dimensions...............................................................................45 7.1 Obtaining package dimensions.........................................45 8 Pinout........................................................................................45 8.1 KL25 Signal Multiplexing and Pin Assignments................45 8.2 KL25 Pinouts.....................................................................48 9 Revision History........................................................................52

5.3 Switching specifications.....................................................21

KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
2 Freescale Semiconductor, Inc.

Ordering parts

1 Ordering parts
1.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to www.freescale.com and perform a part number search for the following device numbers: PKL25 and MKL25

2 Part identification
2.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received.

2.2 Format
Part numbers for this device have the following format: Q KL## A FFF R T PP CC N

2.3 Fields
This table lists the possible values for each field in the part number (not all combinations are valid):
Field Q KL## A FFF Qualification status Kinetis family Key attribute Program flash memory size Description Values • M = Fully qualified, general market flow • P = Prequalification • KL25 • Z = Cortex-M0+ • • • • 32 = 32 KB 64 = 64 KB 128 = 128 KB 256 = 256 KB

Table continues on the next page...

KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
Freescale Semiconductor, Inc. 3

Terminology and guidelines Field R T PP Silicon revision Temperature range (°C) Package identifier Description Values • (Blank) = Main • A = Revision after main • V = –40 to 105 • • • • FM = 32 QFN (5 mm x 5 mm) FT = 48 QFN (7 mm x 7 mm) LH = 64 LQFP (10 mm x 10 mm) LK = 80 LQFP (12 mm x 12 mm)

CC N

Maximum CPU frequency (MHz) Packaging type

• 4 = 48 MHz • R = Tape and reel • (Blank) = Trays

2.4 Example
This is an example part number: MKL25Z64VLK4

3 Terminology and guidelines
3.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip.

3.1.1 Example
This is an example of an operating requirement, which you must meet for the accompanying operating behaviors to be guaranteed:
Symbol VDD Description 1.0 V core supply voltage 0.9 Min. 1.1 Max. V Unit

KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
4 Freescale Semiconductor, Inc.

Terminology and guidelines

3.2 Definition: Operating behavior
An operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions.

3.2.1 Example
This is an example of an operating behavior, which is guaranteed if you meet the accompanying operating requirements:
Symbol IWP Description Digital I/O weak pullup/ 10 pulldown current Min. 130 Max. µA Unit

3.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements.

3.3.1 Example
This is an example of an attribute:
Symbol CIN_D Description Input capacitance: digital pins — Min. 7 Max. pF Unit

3.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: • Operating ratings apply during operation of the chip. • Handling ratings apply when the chip is not powered.

KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
Freescale Semiconductor, Inc. 5

) ir qu e n me t (m ax .Terminology and guidelines 3. .0 V core supply voltage –0.Possible incorrect operation Fatal range Expected permanent failure –∞ Operating (power on) in.5 Result of exceeding a rating 40 Failures in time (ppm) 30 20 The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. Rev.) ∞ n Ha dli ng r ng ati (m (m Ha nd Fatal range Expected permanent failure Handling range No permanent failure Fatal range Expected permanent failure –∞ Handling (power off) ∞ KL25 Sub-Family Data Sheet Data Sheet.No permanent failure .No permanent failure . 10 0 Operating rating Measured characteristic 3. Inc.3 Min.) g tin (m ax . 3. V Unit 3.4.Possible incorrect operation Normal operating range .) tin gr e tin gr a O ra pe O ra pe O ra pe O ra pe Fatal range Expected permanent failure Degraded operating range . mi ) tin gr e ir qu e n me t (m in.Correct operation Degraded operating range . ) lin g ing rat ax .No permanent failure .Possible decreased life .1 Example This is an example of an operating rating: Symbol VDD Description 1.2 Max.Possible decreased life . 6 Freescale Semiconductor.6 Relationship between ratings and operating requirements tin gr a g tin ( n. 1. 9/19/2012.

Rev.8. • If you must exceed an operating requirement at times other than during normal operation (for example. during power sequencing). µA Unit 3. Freescale Semiconductor. 130 Max. Inc. 3.1 Example 1 This is an example of an operating behavior that includes a typical value: Symbol IWP Description Digital I/O weak pullup/pulldown current 10 Min. don’t exceed any of the chip’s operating requirements. • During normal operation. is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions Typical values are provided as design guidelines and are neither tested nor guaranteed.8 Definition: Typical value A typical value is a specified value for a technical characteristic that: • Lies within the range of values specified by the operating behavior • Given the typical manufacturing process.7 Guidelines for ratings and operating requirements Follow these guidelines for ratings and operating requirements: • Never exceed any of the chip’s ratings. 9/19/2012. 70 Typ. 7 . 3. limit the duration as much as possible.Terminology and guidelines 3. 3.8.2 Example 2 This is an example of a chart that shows typical values for various voltage and temperature conditions: KL25 Sub-Family Data Sheet Data Sheet.

1 Thermal handling ratings Symbol TSTG TSDR Description Storage temperature Solder temperature. Determined according to IPC/JEDEC Standard J-STD-020. 8 Freescale Semiconductor. lead-free Min.Ratings 5000 4500 4000 3500 IDD_STOP (μA) 3000 2500 2000 1500 1000 500 0 0. High Temperature Storage Life.3 Value °C V Unit 4 Ratings 4. Inc. 3. –55 — Max. Determined according to JEDEC Standard JESD22-A103.05 1. Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. KL25 Sub-Family Data Sheet Data Sheet.95 1. 150 260 Unit °C °C Notes 1 2 1. Rev. 2.90 0.9 Typical Value Conditions Typical values assume you meet the following conditions (or other conditions as specified): Symbol TA VDD Description Ambient temperature 3. .10 TJ 150 °C 105 °C 25 °C –40 °C 3.00 VDD (V) 1.3 V supply voltage 25 3. 9/19/2012.

5 General KL25 Sub-Family Data Sheet Data Sheet.3 –0.3 — –0. 3. +2000 +500 +100 Unit V V mA Notes 1 2 1. 4.3 –0. Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 4. Freescale Semiconductor.3 –0. — Max. -2000 -500 -100 Max.3 –25 VDD – 0.0 Unit V mA V V mA V V V V 1.8 120 3.63 6. Determined according to JEDEC Standard JESD22-C101. 2.3 25 VDD + 0. human body model Electrostatic discharge voltage. –0.6 VDD + 0. Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). Inc. Determined according to IPC/JEDEC Standard J-STD-020.3 ESD handling ratings Symbol VHBM VCDM ILAT Description Electrostatic discharge voltage. Determined according to JEDEC Standard JESD22-A114. Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.2 Moisture handling ratings Symbol MSL Description Moisture sensitivity level Min.3 3. charged-device model Latch-up current at ambient temperature of 105°C Min. Analog pins are defined as pins that do not have an associated general purpose I/O port function. 3. Rev.63 3. 3 Unit — Notes 1 1. 9 . 9/19/2012.General 4.3 –0.4 Voltage and current operating ratings Symbol VDD IDD VDIO VAIO ID VDDA VUSB_DP VUSB_DM VREGIN Description Digital supply voltage Digital supply current Digital pin input voltage (except RESET) Analog pins1and RESET pin input voltage Instantaneous maximum current single pin limit (applies to all port pins) Analog supply voltage USB_DP input voltage USB_DM input voltage USB regulator input Min.3 Max.

6 0. propagation delays are measured from the 50% to the 50% point.1 0. and • are normal drive strength 5.1 –0.7 V ≤ VDD ≤ 3.1 — — Unit V V V V V V Notes VDD – VDDA VDD-to-VDDA differential voltage VSS – VSSA VSS-to-VSSA differential voltage VIH Input high voltage • 2. Inc.6 3.1 Voltage and current operating requirements Table 1. 1.6 V • 1.1 0.7 V ≤ VDD ≤ 2.71 1.7 V VIL Input low voltage • 2.2 Nonswitching electrical specifications 5. and rise and fall times are measured at the 20% and 80% points. assumes: 1. as shown in the following figure.7 V ≤ VDD ≤ 2.7 V ≤ VDD ≤ 3.General 5.1 AC electrical characteristics Unless otherwise specified.6 V • 1. Figure 1. unless otherwise specified. output pins • have CL=30pF loads.2.75 × VDD Max. 0.7 V — — Table continues on the next page. • are slew rate disabled. 9/19/2012..35 × VDD 0.71 –0.3 × VDD V V KL25 Sub-Family Data Sheet Data Sheet.7 × VDD 0. Rev. Input signal measurement reference All digital I/O switching characteristics. . 10 Freescale Semiconductor. 3. 3. Voltage and current operating requirements Symbol VDD VDDA Description Supply voltage Analog supply voltage Min..

The negative DC injection current limiting resistor is calculated as R=(VDIO_MIN-VIN)/|IIC|.60 2.98 3. — Unit V 1 Notes -25 — 1. 0.3V (Positive current injection) IICcont Contiguous pin DC injection current —regional limit. Inc. VDD supply LVD and POR operating requirements Symbol VPOR VLVDH Description Falling VDD POR detect voltage Falling low-voltage detect threshold — high range (LVDV=01) Low-voltage warning thresholds — high range VLVW1H VLVW2H VLVW3H VLVW4H VHYSH VLVDL • Level 1 falling (LVWV=00) • Level 2 falling (LVWV=01) • Level 3 falling (LVWV=10) • Level 4 falling (LVWV=11) Low-voltage inhibit reset/recover hysteresis — high range Falling low-voltage detect threshold — low range (LVDV=00) 2. 1. If these limits cannot be observed then a current limiting resistor is required.82 2. 5. The negative DC injection current limiting resistor is calculated as R=(VAIO_MIN-VIN)/|IIC|. 1. Voltage and current operating requirements (continued) Symbol VHYS IICDIO Description Input hysteresis Digital pin negative DC injection current — single pin • VIN < VSS-0.56 Max.3V IICAIO Analog2 pin DC injection current — single pin • VIN < VSS-0. If this limit cannot be observed then a current limiting resistor is required.08 — 1.3V (Negative current injection) • VIN > VDD+0. then there is no need to provide current limiting resistors at the pads.2 — +25 — mA V 1. 11 .00 ±60 1.70 2.88 2. 0. If VIN greater than VDIO_MIN (=VSS-0. 3. then there is no need to provide current limiting resistors at the pads. 9/19/2012. There is no diode connection to VDD.90 3.5 2.48 Typ. Freescale Semiconductor. If VIN is greater than VAIO_MIN (=VSS-0. 3. Analog pins are defined as pins that do not have an associated general purpose I/O port function..1 2.78 2.2.2 LVD and POR operating requirements Table 2.92 — 1. All analog pins are internally clamped to VSS and VDD through ESD protection diodes.66 V V V V mV V Min..8 2. KL25 Sub-Family Data Sheet Data Sheet. includes sum of negative injection currents or sum of positive injection currents of 16 contiguous pins • Negative current injection • Positive current injection VRAM VDD voltage required to retain RAM mA -5 — — +5 -5 — mA 3 Min.06 × VDD Max. The positive injection current limiting resistor is calcualted as R=(VIN-VAIO_MAX)/|IIC|.80 2.72 2.54 2. All digital I/O pins are internally clamped to VSS through a ESD protection diode.3V) and VIN is less than VAIO_MAX(=VDD+0.3V) is observed. Select the larger of these two calculated resistances.General Table 1.3V) is observed.62 2. Rev. 2.64 Unit V V 1 Notes Table continues on the next page.

IOL = 18 mA • 1.General Table 2.5 — — — 100 V V mA 1 VDD – 0. IOH = -5 mA • 1. 9/19/2012. .7 V ≤ VDD ≤ 3.71 V ≤ VDD ≤ 2.5 — — V V 1 Min. 3.96 2.06 2.. Inc.00 2.025 65 1 V V mA μA μA μA μA 2 2 2 — — 0.6 V. Rev.90 2.5 mA VOL Output low voltage — High drive pad • 2.71 V ≤ VDD ≤ 2.7 V ≤ VDD ≤ 3. IOH = -6 mA IOHT VOL Output high current total for all ports Output low voltage — Normal drive pad • 2. Rising thresholds are falling threshold + hysteresis voltage 5. IOH = -1.5 VDD – 0.6 V.84 1. Unit Notes 1 Table continues on the next page.. VDD supply LVD and POR operating requirements (continued) Symbol VLVW1L VLVW2L VLVW3L VLVW4L VHYSL VBG tLPO Description Low-voltage warning thresholds — low range • Level 1 falling (LVWV=00) • Level 2 falling (LVWV=01) • Level 3 falling (LVWV=10) • Level 4 falling (LVWV=11) Low-voltage inhibit reset/recover hysteresis — low range Bandgap voltage reference Internal low power oscillator period — factory trimmed 1.7 V ≤ VDD ≤ 3. 12 Freescale Semiconductor.71 V ≤ VDD ≤ 2.7 V.6 V.16 — 1.04 — 0.00 1000 1. Typ.7 V. IOL = 6 mA IOLT IIN IIN IIN IOZ Output low current total for all ports Input leakage current (per pin) for full temperature range Input leakage current (per pin) at 25 °C Input leakage current (total all pins) for full temperature range Hi-Z (off-state) leakage current (per pin) — — — — — — — 0. IOH = -18 mA • 1.3 Voltage and current operating behaviors Table 3.94 2.10 ±40 1.2.74 1.71 V ≤ VDD ≤ 2.86 1.80 1.7 V ≤ VDD ≤ 3.5 0.7 V.5 0.6 V.5 mA VOH Output high voltage — High drive pad • 2.5 100 1 0. Max. KL25 Sub-Family Data Sheet Data Sheet.5 V V 1 VDD – 0. Voltage and current operating behaviors Symbol VOH Description Output high voltage — Normal drive pad • 2. IOL = 5 mA • 1. IOL = 1.97 900 1. Max.7 V.5 VDD – 0. Unit Notes 1 1.03 1100 V V V V mV V μs Min.

Measured at VDD supply voltage = VDD min and Vinput = VDD 5. Freescale Semiconductor. All other GPIOs are normal drive only. 13 .4 Power mode transition operating behaviors All specifications except tPOR and VLLSx→RUN recovery times in the following table assume this clock configuration: • CPU and system clocks = 48 MHz • Bus and flash clock = 24 MHz • FEI clock mode Table 4.8 V to execution of the first instruction across the operating temperature range of the chip. 2. Rev. 300 Unit μs Notes KL25 Sub-Family Data Sheet Data Sheet. PTD6. Power mode transition operating behaviors Symbol tPOR Description After a POR event. Inc. — Max. 20 20 Max. Voltage and current operating behaviors (continued) Symbol RPU RPD Description Internal pullup resistors Internal pulldown resistors Min. Measured at VDD supply voltage = VDD min and Vinput = VSS 4. PTB1. amount of time from the point VDD reaches 1. PTB0. Measured at VDD = 3. 3.2. — Typ. 9/19/2012.General Table 3. and PTD7 I/O have both high drive and normal drive capability selected by the associated PTx_PCRn[DSE] control bit. 50 50 Unit kΩ kΩ Notes 3 4 1. • VLLS0 → RUN — • VLLS1 → RUN — • VLLS3 → RUN — • LLS → RUN — • VLPS → RUN — • STOP → RUN — 4 4.4 μs 4 4.6 μs 42 53 μs 93 115 μs 95 115 μs Min.6 V 3.4 μs 4 4.

0 mA IDD_WAIT 3 — 2.5 MHz bus • at 3.0 V IDD_RUN Run mode current . all peripheral clocks disabled. code of while(1) loop executing from flash • at 3.48 MHz core / 24 MHz bus and flash. all peripheral clocks enabled.9 4.7 mA 5 — 188 570 μA 5 — 224 613 μA Table continues on the next page.0 V Wait mode current . — Max.. Power consumption operating behaviors Symbol IDDA Description Analog supply current Min. — — 6. 3.core and system disabled / 10.48 MHz core / 24 MHz flash/ bus disabled.4 MHz core / 0.8 MHz flash / bus clock disabled.2.5 3. — Typ. code of while(1) loop executing from flash • at 3.0 V IDD_VLPR Very low power run mode current .4 — mA IDD_RUNCO_ Run mode current in compute operation . LPTMR CM running using 4MHz internal reference clock.8 7. .0 V IDD_RUN Run mode current . 9/19/2012.48 MHz core / 24 MHz bus and flash.7 5. 4.core disabled / 48 MHz system / 24 MHz bus / flash disabled (flash doze enabled).48 MHz core / 24 MHz flash / bus clock disabled.1 5. all peripheral clocks disabled • at 3.8 MHz bus and flash. Rev.3 mA mA 3 — 3. code of while(1) loop executing from flash • at 3.0 V • at 25 °C • at 125 °C IDD_WAIT Wait mode current .General 5.. CoreMark® benchmark code executing from flash • at 3.0 V IDD_VLPRCO Very low power run mode current in compute operation .core disabled / 24 MHz system / 24 MHz bus / flash disabled (flash doze enabled).1 6.0 V IDD_RUNCO Run mode current in compute operation . code of while(1) loop executing from flash • at 3.5 Power consumption operating behaviors Table 5.4 6.4 MHz core / 0. See note Unit mA Notes 1 2 — 6. all peripheral clocks disabled • at 3.0 V 3 — 2. all peripheral clocks disabled.2 mA 3 — 5.2 mA IDD_PSTOP2 Stop mode current with partial stop 2 clocking option .3 mA 3.8 8. KL25 Sub-Family Data Sheet Data Sheet. 14 Freescale Semiconductor.0 V 3 — 4. code of while(1) loop executing from flash • at 3. Inc.

all peripheral clocks disabled • at 3.8 MHz bus / flash disabled (flash doze enabled).4 10 20 37 81 16 35 50 112 201 μA — — — — — 345 357 392 438 551 490 827 869 927 1065 μA Min...7 39 43 49 69 μA — — — — — 4. — Typ.core disabled / 4 MHz system / 0.0 V at 25 °C at 50 °C at 70 °C at 85 °C at 105 °C IDD_VLPS Very-low-power stop mode current at 3. 9/19/2012.0 V at 25 °C at 50 °C at 70 °C at 85 °C at 105 °C IDD_VLLS3 Very low-leakage stop mode 3 current at 3.5 13 30 3. 745 Unit μA Notes 5.General Table 5.0 V Stop mode current at 3.3 5.6 6. 3.4 MHz core / 0. Rev.0V at 25°C at 50°C at 70°C at 85°C at 105°C — — — — — 0.4 2.0 V at 25 °C at 50 °C at 70 °C at 85 °C at 105 °C IDD_LLS Low leakage stop mode current at 3.0 V Very low power wait mode current .3 2. Power consumption operating behaviors (continued) Symbol IDD_VLPR Description Very low power run mode current . Freescale Semiconductor. 15 .8 MHz bus and flash. all peripheral clocks enabled.1 9.7 1.5 5.2 19 21 26 38 μA — — — — — 1. 300 Max.2 21 3. code of while(1) loop executing from flash • at 3. Inc.4 13 14 17 25 μA — — — — — 1. 4 IDD_VLPW — 135 496 μA 5 IDD_STOP Table continues on the next page.9 3.1 13 1. KL25 Sub-Family Data Sheet Data Sheet.0 V at 25 °C at 50 °C at 70 °C at 85 °C at 105 °C IDD_VLLS1 Very low-leakage stop mode 1 current at 3.

2. External 4MHz crystal clock adder. 3. See each module's specification for its supply current. Low power mode peripheral adders — typical value Symbol IIREFSTEN4MHz Description -40 4 MHz internal reference clock (IRC) adder. Measured by entering STOP or VLPS mode with 4 MHz IRC enabled. CoreMark benchmark compiled using Keil 4. 16 Freescale Semiconductor. 5. 9/19/2012. 943 11760 13260 15700 23480 Unit nA Notes Table 6. Power consumption operating behaviors (continued) Symbol IDD_VLLS0 Description Very low-leakage stop mode 0 current (SMC_STOPCTRL[PORPO] = 0) at 3. Inc. 56 25 56 Temperature (°C) 50 56 70 56 85 56 105 56 µA Unit IIREFSTEN32KHz 52 52 52 52 52 52 µA IEREFSTEN4MHz 206 228 237 245 251 258 uA Table continues on the next page. Incremental current consumption from peripheral activity is not included. — — — — — Typ. 3. optimized for time. No brownout 6 — — — — — 176 760 2120 4500 12130 860 3577 11660 18450 22441 nA Min. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device.54 with optimization level 3. 6. Rev. 32 kHz internal reference clock (IRC) adder. Measured by entering STOP mode with the 32 kHz IRC enabled.General Table 5. 381 956 2370 4800 12410 Max. MCG configured for FEI mode.0 V at 25 °C at 50 °C at 70 °C at 85 °C at 105 °C 1. MCG configured for PEE mode. Measured by entering STOP or VLPS mode with the crystal enabled. 4..0 V at 25 °C at 50 °C at 70 °C at 85 °C at 105 °C IDD_VLLS0 Very low-leakage stop mode 0 current (SMC_STOPCTRL[PORPO] = 1) at 3. MCG configured for BLPI mode.. KL25 Sub-Family Data Sheet Data Sheet. .

KL25 Sub-Family Data Sheet Data Sheet. Rev. 3. Includes ERCLK32K (32 kHz external crystal) power consumption.General Table 6. MCGIRCLK (4MHz internal reference clock) OSCERCLK (4MHz external crystal) IBG Bandgap adder when BGEN bit is set and device is placed in VLPx. Low power mode peripheral adders — typical value (continued) Symbol IEREFSTEN32KHz Description -40 External 32 kHz crystal clock adder by means of the OSC0_CR[EREFSTEN and EREFSTEN] bits. MCGIRCLK (4MHz internal reference clock) OSCERCLK (4MHz external crystal) ITPM TPM peripheral adder measured by placing the device in STOP or VLPS mode with selected clock source configured for output compare generating 100Hz clock signal. LLS. Inc.. Includes selected clock source power consumption. Includes 6-bit DAC power consumption. VLLS1 VLLS3 LLS VLPS STOP ICMP CMP peripheral adder measured by placing the device in VLLS1 mode with CMP enabled using the 6-bit DAC and a single external input for compare. No load is placed on the I/O generating the clock signal. 86 235 45 86 256 45 86 265 45 86 274 45 86 280 45 86 287 45 µA 66 214 66 237 66 246 66 254 66 260 66 268 µA 22 22 22 22 22 22 µA 25 Temperature (°C) 50 70 85 105 Unit 440 440 490 510 510 490 490 490 560 560 540 540 540 560 560 560 560 560 560 560 570 570 570 610 610 580 580 680 680 680 nA IRTC 432 357 388 475 532 810 nA IUART µA Table continues on the next page.. 17 . Measured by entering all modes with the crystal enabled. Includes selected clock source and I/O switching currents. or VLLSx mode. 9/19/2012. UART peripheral adder measured by placing the device in STOP or VLPS mode with selected clock source waiting for RX data at 115200 baud rate. RTC peripheral adder measured by placing the device in VLLS1 mode with external 32 kHz crystal enabled by means of the RTC_CR[OSCE] bit and the RTC ALARM set for 1 minute. Freescale Semiconductor.

ADC is configured for low power mode using the internal clock and continuous conversions. Inc. 18 Freescale Semiconductor.5. 9/19/2012. .General Table 6.2. Low power mode peripheral adders — typical value (continued) Symbol IADC Description -40 ADC peripheral adder combining the measured values at VDD and VDDA by placing the device in STOP or VLPS mode. and BLPE for VLPR mode USB regulator disabled No GPIOs toggled Code execution from flash with cache enabled For the ALLOFF curve.1 • • • • • Diagram: Typical IDD_RUN operating behavior The following data was measured under these conditions: MCG in FBE for run mode. 3. all peripheral clocks are disabled except FTFA KL25 Sub-Family Data Sheet Data Sheet. Rev. 366 25 366 Temperature (°C) 50 366 70 366 85 366 105 366 µA Unit 5.

00E+00 '1-1 1 '1-1 2 '1-1 3 '1-1 4 '1-1 6 '1-1 12 '1-1 24 '1-2 48 CLK Ratio Flash-Core Core Freq (MHz) Figure 2. Freescale Semiconductor.00E-03 All Peripheral CLK Gates 4. 19 .00E-03 7. Code Residence = Flash. Run mode supply current vs.General Run Mode Current Vs Core Frequency Temperature = 25.00E-03 6. CACHE = Enable.00E-03 1. Rev.00E-03 Current Consumption on VDD(A) 5. core frequency KL25 Sub-Family Data Sheet Data Sheet.00E-03 2. Clocking Mode = FBE 8. VDD = 3.00E-03 000.00E-03 All Off All On 3. Inc. 9/19/2012. 3.

General VLPR Mode Current Vs Core Frequency Temperature = 25.Measurement of Electromagnetic Emissions. CACHE = Enable. band 1 Radiated emissions voltage. KL25 Sub-Family Data Sheet Data Sheet.00E-06 50. . from among the measured orientations in each frequency range. Code Residence = Flash.Measurement of Electromagnetic Emissions. V DD = 3. EMC radiated emissions operating behaviors for 64-pin LQFP package Symbol VRE1 VRE2 VRE3 VRE4 VRE_IEC Description Radiated emissions voltage. Inc. Clocking Mode = BLPE 400. Rev. Measurements were made while the microcontroller was running basic application code.00E+00 '1-1 '1-2 '1-2 '1-4 1 2 4 CLK Ratio Flash-Core Core Freq (MHz) Figure 3. 13 15 12 7 M Unit dBμV dBμV dBμV dBμV — 2. core frequency 5.00E-06 All Peripheral CLK Gates 200.00E-06 250.00E-06 350. 20 Freescale Semiconductor.6 EMC radiated emissions operating behaviors Table 7.00E-06 100. 3 Notes 1. band 4 IEC level Frequency band (MHz) 0. 9/19/2012.2. band 3 Radiated emissions voltage.15–50 50–150 150–500 500–1000 0. band 2 Radiated emissions voltage. 3. Determined according to IEC Standard 61967-1. 150 kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2. Integrated Circuits . 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and Wideband TEM Cell Method.00E-06 Current Consumption on VDD (A) 300.00E-06 000.15–1000 Typ. Integrated Circuits . 2 1.00E-06 All Off All On 150. The reported emission level is the value of the maximum measured emission. rounded up to the next whole number. VLPR mode current vs.

Max. Inc.3 V.1 Device clock specifications Symbol fSYS fBUS fFLASH fSYS_USB fLPTMR fSYS fBUS fFLASH fLPTMR fERCLK fLPTMR_pin Description Normal run mode System and core clock Bus clock Flash clock System and core clock when Full Speed USB in operation LPTMR clock VLPR System and core clock Bus clock Flash clock LPTMR clock External reference clock LPTMR clock mode1 — — — — — — Table continues on the next page. TA = 25 °C. Capacitance attributes Symbol CIN_A CIN_D Description Input capacitance: analog pins Input capacitance: digital pins Min.2. — — Max. fSYS = 48 MHz. Rev. 21 . Perform a keyword search for “EMC design.General 2. 9/19/2012. 3. Freescale Semiconductor. Specified according to Annex D of IEC Standard 61967-2. Measurement of Radiated Emissions—TEM Cell and Wideband TEM Cell Method 5. fBUS = 48 MHz 3. 4 1 1 24 16 24 MHz MHz MHz MHz MHz MHz — — — 20 — 48 24 24 — 24 MHz MHz MHz MHz MHz Min. VDD = 3..3 Switching specifications 5.com. fOSC = 8 MHz (crystal). 7 7 Unit pF pF 5. Unit Notes KL25 Sub-Family Data Sheet Data Sheet..3.8 Capacitance attributes Table 8.” 5.2. 2. Go to www.7 Designing with radiated emissions in mind To find application notes that provide guidance on designing your system to minimize interference from radiated emissions: 1.freescale.

3. 3. and I2C signals. — — — — Max.1 Thermal operating requirements Table 9.2 General Switching Specifications These general purpose specifications apply to all signals configured for GPIO. 16 16 8 8 Unit MHz MHz MHz MHz Notes fLPTMR_ERCL LPTMR external reference clock fosc_hi_2 fTPM fUART0 Oscillator crystal or resonator frequency — high frequency mode (high range) (MCG_C2[RANGE]=1x) TPM asynchronous clock UART0 asynchronous clock 1. –40 –40 Max. Inc.General Symbol K Description Min. 22 Freescale Semiconductor. Symbol Description GPIO pin interrupt pulse width (digital glitch filter disabled) — Synchronous path External RESET and NMI pin interrupt pulse width — Asynchronous path GPIO pin interrupt pulse width — Asynchronous path Port rise and fall time — 1.4. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any other module. 1. The greater synchronous and asynchronous timing must be met.4 Thermal specifications 5. Rev. UART. 2. Thermal operating requirements Symbol TJ TA Description Die junction temperature Ambient temperature Min. 5. This is the shortest pulse that is guaranteed to be recognized.3. 9/19/2012. 75 pF load 36 ns Min. — — — Unit Bus clock cycles ns ns Notes 1 2 2 3 5.5 100 16 Max. . 125 105 Unit °C °C KL25 Sub-Family Data Sheet Data Sheet.

/min. 3. junction to ambient (natural convection) Thermal resistance.4.0 5.2 Thermal attributes Table 10. junction to ambient (200 ft. 2.1. 6 Peripheral operating requirements and behaviors 6. 3. 23 . 9/19/2012. Microcircuits. junction to ambient (200 ft.6 34 20 5 10 2.1 SWD Electricals Table 11. Rev.8 8 °C/W °C/W °C/W 2 3 4 1.0 12 1.71 Max. air speed) Thermal resistance.1 Core modules 6. Integrated Circuits Thermal Test Method Environmental Conditions —Natural Convection (Still Air). Determined according to JEDEC Standard JESD51-8.Peripheral operating requirements and behaviors 5. Freescale Semiconductor. 4. Integrated Circuit Thermal Test Method Environmental Conditions —Junction-to-Board. Integrated Circuit Thermal Test Method Environmental Conditions—Forced Convection (Moving Air). Inc. air speed) Thermal resistance. Determined according to Method 1012. SWD full voltage range electricals Symbol Description Operating voltage Table continues on the next page.1 of MIL-STD 883. junction to case Thermal characterization parameter. with the cold plate temperature used for the case temperature..6 Unit V KL25 Sub-Family Data Sheet Data Sheet. Integrated Circuits Thermal Test Method Environmental Conditions —Natural Convection (Still Air).. Determined according to JEDEC Standard JESD51-2./min. junction to board Thermal resistance. junction to ambient (natural convection) Thermal resistance. The value includes the thermal resistance of the interface material between the top of the package and the cold plate. Thermal attributes Board type Single-layer (1S) Symbol RθJA Description Thermal resistance. or EIA/JEDEC Standard JESD51-6. 1. Test Method Standard. junction to package top outside center (natural convection) 80 LQFP 70 64 LQFP 71 48 QFN 84 32 QFN 92 Unit °C/W Notes 1 Four-layer (2s2p) RθJA 53 52 28 33 °C/W Single-layer (1S) RθJMA — 59 69 75 °C/W Four-layer (2s2p) RθJMA — 46 22 27 °C/W — — — RθJB RθJC ΨJT 34 15 0. Determined according to JEDEC Standard JESD51-2. 3. Min.

Peripheral operating requirements and behaviors Table 11. Serial wire data timing KL25 Sub-Family Data Sheet Data Sheet. SWD full voltage range electricals (continued) Symbol J1 Description SWD_CLK frequency of operation • Serial wire debug J2 J3 SWD_CLK cycle period SWD_CLK clock pulse width • Serial wire debug J4 J9 J10 J11 J12 SWD_CLK rise and fall times SWD_DIO input data setup time to SWD_CLK rise SWD_DIO input data hold time after SWD_CLK rise SWD_CLK high to SWD_DIO data valid SWD_CLK high to SWD_DIO high-Z 20 — 10 0 — 5 — 3 — — 32 — ns ns ns ns ns ns 0 1/J1 25 — MHz ns Min. 24 Freescale Semiconductor. Unit J2 J3 J3 SWD_CLK (input) J4 J4 Figure 4. 3. 9/19/2012. Serial wire clock input timing SWD_CLK J9 J10 SWD_DIO J11 Input data valid SWD_DIO J12 Output data valid SWD_DIO J11 SWD_DIO Output data valid Figure 5. Inc. Max. Rev. .

6 Unit kHz kHz %fdco 1 Notes Δfdco_res_t Resolution of trimmed average DCO output frequency at fixed voltage and temperature — using SCTRIM and SCFTRIM Δfdco_t Δfdco_t Total deviation of trimmed average DCO output frequency over voltage and temperature Total deviation of trimmed average DCO output frequency over fixed voltage and temperature range of 0 .94 39. 25 . MCG specifications Symbol fints_ft fints_t Description Internal reference frequency (slow clock) — factory trimmed at nominal VDD and 25 °C Internal reference frequency (slow clock) — user trimmed Min. 10.4 ±3 ± 1.0625 25 48 kHz MHz MHz 3. Freescale Semiconductor.5 %fdco %fdco 1. 6. or 11 FLL ffll_ref fdco FLL reference frequency range DCO output frequency range Low range (DRS = 00) 640 × ffll_ref Mid range (DRS = 01) 1280 × ffll_ref — — +0.Peripheral operating requirements and behaviors 6.70 °C Internal reference frequency (fast clock) — factory trimmed at nominal VDD and 25 °C Frequency deviation of internal reference clock (fast clock) over temperature and voltage --factory trimmed at nominal VDD and 25 °C Internal reference frequency (fast clock) — user trimmed at nominal VDD and 25 °C Loss of external clock minimum frequency — RANGE = 00 Loss of external clock minimum frequency — RANGE = 01. 9/19/2012.5/-0.3 Max. — 31.7 ± 0. 2 1..25 20 40 — — — 5 — — MHz kHz kHz — 20. KL25 Sub-Family Data Sheet Data Sheet.1 MCG specifications Table 12. 32. 3.768 — ± 0..3. Inc.97 41. — 39.3 Clock modules 6. 2 fintf_ft Δfintf_ft — — 4 +1/-2 — ±3 MHz %fintf_ft 2 fintf_t floc_low floc_high 3 (3/5) x fints_t (16/5) x fints_t 31.0625 ± 0. 4 Table continues on the next page.2 System modules There are no specifications necessary for the device's system modules.25 — Typ. Rev.

11. or changing from FLL disabled (BLPE. this specification assumes it is already running. FBE. PEE). 3. 3. this specification assumes it is already running.97 150 × + 1075(1/ fpll_ref) 10-6 ps ps % % s 11 — — 120 50 — — ps ps 10 48.97 — MHz Min. The deviation is relative to the factory trimmed frequency at nominal VDD and 25 °C. 9. .47 — 1350 600 — — — — — ± 2. This specification applies to any time the PLL VCO divider or reference divider is changed. 26 Freescale Semiconductor. 7.99 Max. Rev.0 600 — — 4. BLPI) to PLL enabled (PBE. 6 fdco_t_DMX32 DCO output frequency Ipll — 2. Excludes any oscillator currents that are also consuming power while PLL is in operation.Peripheral operating requirements and behaviors Table 12. 6.0 — — 1060 100 — MHz µA 9 — — 1 ms 8 — 180 — ps 7 — 47. This specification was obtained using a Freescale developed PCB. 10. 2. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock mode). trim value is changed. If a crystal/resonator is being used as the reference. fints_ft. DRS bits are changed. 23. fpll_ref = 2 MHz. MCG specifications (continued) Symbol Description Low range (DRS = 00) 732 × ffll_ref Mid range (DRS = 01) 1464 × ffll_ref Jcyc_fll tfll_acquire fvco Ipll FLL period jitter • fVCO = 48 MHz FLL target frequency acquisition time PLL VCO operating frequency PLL operating current • PLL at 96 MHz (fosc_hi_1 = 8 MHz. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 1.0 µA MHz 9 fpll_ref Jcyc_pll 10 1. This specification is based on standard deviation (RMS) of period or frequency. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 0. VDIV multiplier = 48) PLL operating current • PLL at 48 MHz (fosc_hi_1 = 8 MHz. 5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device. KL25 Sub-Family Data Sheet Data Sheet. 8. The resulting system clock frequencies must not exceed their maximum specified values. 9/19/2012. Inc.49 ± 4. 4. — Unit MHz Notes 5. FBI). FEE. This specification applies to any time the FLL reference source or reference divider is changed. or changing from PLL disabled (BLPE. — Typ. BLPI) to FLL enabled (FEI. fpll_ref = 2 MHz.98 ± 5. PLL jitter is dependent on the noise characteristics of each PCB and results will vary. If a crystal/resonator is being used as the reference. DMX32 bit is changed. VDIV multiplier = 24) PLL reference frequency range PLL period jitter (RMS) • fvco = 48 MHz • fvco = 100 MHz Jacc_pll PLL accumulated jitter over 1µs (RMS) • fvco = 48 MHz • fvco = 100 MHz Dlock Dunl tpll_lock Lock entry frequency tolerance Lock exit frequency tolerance Lock detector detection time — — ± 1. The DCO frequency deviation (Δfdco_t) over voltage and temperature must be considered.

Peripheral operating requirements and behaviors 6. 3. — 500 200 300 950 1.5 3 4 — — — 10 — 1 — — — — — — — — — — — — MΩ MΩ MΩ MΩ μA μA μA mA mA mA 2. Inc.71 Table 13. Rev.2 Oscillator electrical specifications This section provides the electrical characteristics of the module.1 Symbol VDD IDDOSC Oscillator DC electrical specifications Description Supply voltage Supply current — low-power mode (HGO=0) • 32 kHz • 4 MHz • 8 MHz (RANGE=01) • 16 MHz • 24 MHz • 32 MHz — — — — — — Min.2.. 6. high-gain mode (HGO=1) Table continues on the next page. Oscillator DC electrical specifications Typ. low-power mode (HGO=0) Feedback resistor — low-frequency.6 — — — — — — Unit V 1 nA μA μA μA mA mA 1 — — — — — — — — — — — — 25 400 500 2. KL25 Sub-Family Data Sheet Data Sheet. 3 2. 9/19/2012.3. 1. 3 2. 27 . Freescale Semiconductor.5 Max. 4 Notes IDDOSC Supply current — high gain mode (HGO=1) • 32 kHz • 4 MHz • 8 MHz (RANGE=01) • 16 MHz • 24 MHz • 32 MHz Cx Cy RF EXTAL load capacitance XTAL load capacitance Feedback resistor — low-frequency.3. low-power mode (HGO=0) Feedback resistor — high-frequency.2 1.. 3. high-gain mode (HGO=1) Feedback resistor — high-frequency.

3. Oscillator frequency specifications Typ. 4. low-power mode (HGO=0) Series resistor — high-frequency. KL25 Sub-Family Data Sheet Data Sheet.6 — V — VDD — V 1.. VDD=3. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any other devices. high-gain mode (HGO=1) — 0 0. — — — Typ. 40 8 Unit kHz MHz Notes fosc_hi_2 8 — 32 MHz fec_extal tdc_extal — 40 — 50 48 60 MHz % 1. Inc.Peripheral operating requirements and behaviors Table 13. RF is integrated and must not be attached externally.. Rev. Temperature =25 °C 2. 28 Freescale Semiconductor. low-power mode (HGO=0) Series resistor — low-frequency. 9/19/2012. For all other cases external capacitors must be used. — — Max. — 200 — Max. 32 3 Table 14. low-power mode (HGO=0) Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency. When low power mode is selected. 2 Table continues on the next page.Cy can be provided by using the integrated capacitors when the low frequency oscillator (RANGE = 00) is used. 5.6 — — kΩ V Min. low-power mode (HGO=0) Peak-to-peak amplitude of oscillation (oscillator mode) — high-frequency. Cx. . Oscillator DC electrical specifications (continued) Symbol RS Description Series resistor — low-frequency. — — — Unit kΩ kΩ kΩ Notes — VDD — V — 0.3 V.. 6.2 Symbol fosc_lo fosc_hi_1 Oscillator frequency specifications Description Oscillator crystal or resonator frequency — low frequency mode (MCG_C2[RANGE]=00) Oscillator crystal or resonator frequency — high frequency mode (low range) (MCG_C2[RANGE]=01) Oscillator crystal or resonator frequency — high frequency mode (high range) (MCG_C2[RANGE]=1x) Input clock frequency (external clock mode) Input clock duty cycle (external clock mode) Min. high-gain mode (HGO=1) Series resistor — high-frequency.3. high-gain mode (HGO=1) Peak-to-peak amplitude of oscillation (oscillator mode) — high-frequency. See crystal or resonator manufacturer's recommendation 3. high-gain mode (HGO=1) — Vpp5 Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency.2.

6. — — — Typ. — — — Unit ms ms ms Notes 3. 7.4 Memories and memory interfaces 6. when it is divided by FRDIV.6 Max. 6. — — — Typ. 750 250 0. NVM program/erase timing specifications Symbol thvpgm4 thversscr thversall Description Longword Program high-voltage time Sector Erase high-voltage time Erase All high-voltage time Min. high-gain mode (HGO=1) Crystal startup time — 8 MHz high-frequency (MCG_C2[RANGE]=01). Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register being set. 9/19/2012. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.Peripheral operating requirements and behaviors Table 14.1 Flash timing specifications — program and erase The following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. 29 . 3. restrict the frequency of the input clock so that. Freescale Semiconductor. 3. Inc.1 Flash electrical specifications This section describes the electrical characteristics of the flash memory module. When transitioning from FBE to FEI mode. low-power mode (HGO=0) Crystal startup time — 8 MHz high-frequency (MCG_C2[RANGE]=01).1. Table 15. 2. it remains within the limits of the DCO input clock frequency. 18 113 452 Unit μs ms ms 1 1 Notes 1. Rev. 4 — 1 — ms 1. Oscillator frequency specifications (continued) Symbol tcst Description Crystal startup time — 32 kHz low-frequency.4. KL25 Sub-Family Data Sheet Data Sheet. low-power mode (HGO=0) Crystal startup time — 32 kHz low-frequency. Proper PC board layout procedures must be followed to achieve specifications. 4. Maximum time based on expectations at cycling end-of-life.5 13 52 Max.4. high-gain mode (HGO=1) Min.

30 Freescale Semiconductor. Maximum times for erase parameters based on expectations at cycling end-of-life.1. 3.4 Symbol Reliability specifications Description Table 18. Flash command timing specifications Typ.1. 2. Inc. Flash high voltage current behaviors Typ.5 1. — — — 65 14 — — 65 62 — Max. Rev. 6.4. Typical endurance defined in Engineering Bulletin EB619. — — Table 17. Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ 125°C. Assumes 25MHz flash clock frequency.4.4. 2. . Engineering Bulletin EB618 does not apply to this technology. 6. KL25 Sub-Family Data Sheet Data Sheet.Peripheral operating requirements and behaviors 6. 60 45 30 145 114 1.2 Symbol trd1sec1k tpgmchk trdrsrc tpgm4 tersscr trd1all trdonce tpgmonce tersall tvfykey Flash timing specifications — commands Description Read 1s Section execution time (flash sector) Program Check execution time Read Resource execution time Program Longword execution time Erase Flash Sector execution time Read 1s All Blocks execution time Read Once execution time Program Once execution time Erase All Blocks execution time Verify Backdoor Access Key execution time Min. — — — Unit years years cycles 2 Notes tnvmretp10k Data retention after up to 10 K cycles tnvmretp1k nnvmcycp Data retention after up to 1 K cycles Cycling endurance 1.3 Symbol IDD_PGM IDD_ERS Flash high voltage current behaviors Description Average current adder during high voltage flash programming operation Average current adder during high voltage flash erase operation Min.0 4. Program Flash 5 20 10 K Typ.1.5 Max. NVM reliability specifications Min. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25°C use profile.8 25 — 500 30 Unit μs μs μs μs ms ms μs μs ms μs 2 1 1 2 Notes 1 1 1 1. 2.1 50 100 50 K Max.0 Unit mA mA 6. — — — — — — — — — — Table 16. 9/19/2012.

6.5 Security and integrity modules There are no specifications necessary for the device's security and integrity modules.0 kΩ MHz MHz 5 5 6 Typ.1 — 0 0 VDDA VSSA — 8 4 2 Max. Rev. 31 . 6.1 Symbol VDDA ΔVDDA ΔVSSA VREFH VREFL VADIN CADIN 16-bit ADC operating conditions Description Supply voltage Supply voltage Ground voltage ADC reference voltage high ADC reference voltage low Input voltage Input capacitance • 16-bit mode • 8-/10-/12-bit modes Conditions Absolute Delta to VDD (VDD-VDDA) Delta to VSS (VSS . Inc..13 VSSA VREFL — — — 13-/12-bit modes fADCK < 4 MHz ≤ 13-bit mode 16-bit mode ≤ 13 bit modes No ADC hardware averaging Continuous conversions enabled. 3. 1.1. 6. 3. All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy specifications.0 — — — 5 18.6 Analog 6. 20. 9/19/2012.VSSA) Table 19..0 12. ADCx_DM0.000 — 818.1 ADC electrical specifications The 16-bit accuracy specifications listed in Table 19 and Table 20 are achievable on the differential pins ADCx_DP0.0 2.71 -100 -100 1. subsequent conversion time Table continues on the next page. Freescale Semiconductor.6.6 +100 +100 VDDA VSSA VREFH 10 5 5 kΩ 4 Unit V mV mV V V V pF 2 2 3 3 Notes RADIN RAS Input resistance Analog source resistance fADCK fADCK Crate ADC conversion clock frequency ADC conversion clock frequency ADC conversion rate KL25 Sub-Family Data Sheet Data Sheet. 16-bit ADC operating conditions Min.330 Ksps — 1.Peripheral operating requirements and behaviors 6.

1 — Max. For packages without dedicated VREFH and VREFL pins. Typical values are for reference only and are not tested in production.. .2 — Max.1. 37. 0. VREFL = VSSA) Description Supply current Conditions1 Min. subsequent conversion time 1.0 MHz unless otherwise stated.467 Unit Ksps Notes 6 Z ADIN SIMPLIFIED CHANNEL SELECT CIRCUIT Z AS R AS V ADIN V AS C AS Pad leakage due to input protection R ADIN ADC SAR ENGINE R ADIN INPUT PIN R ADIN INPUT PIN R ADIN C ADIN INPUT PIN Figure 6.7 Unit mA Notes 3 16-bit ADC electrical characteristics KL25 Sub-Family Data Sheet Data Sheet. the ADHSC bit must be set and the ADLPC bit must be clear. 3. 5. Typical values assume VDDA = 3. 4. For guidelines and examples of conversion rate calculation. Temp = 25 °C.0 V. ADC input impedance equivalency diagram 6. 2. 461.6. The results in this data sheet were derived from a system which has < 8 Ω analog source resistance. fADCK = 1. Rev. The analog source resistance must be kept as low as possible to achieve the best results.037 Typ. To use the maximum ADC conversion clock frequency. 1. Typ. 16-bit ADC characteristics (VREFH = VDDA. DC potential difference. 3.215 Table continues on the next page. 9/19/2012. and VREFL is internally tied to VSSA. 6. 32 Freescale Semiconductor. download the ADC calculator tool SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT Min.Peripheral operating requirements and behaviors Table 19. VREFH is internally tied to VDDA. Inc. The RAS/CAS time constant should be kept to < 1ns. This resistance is external to MCU. 16-bit ADC operating conditions (continued) Symbol Crate Description ADC conversion rate Conditions 16-bit mode No ADC hardware averaging Continuous conversions enabled..2 Symbol IDDA_ADC Table 20.

1 7. KL25 Sub-Family Data Sheet Data Sheet.4 3. 3.4 13..7 to +0.5 • 12-bit modes LSB4 5 5 DNL INL Integral nonlinearity EFS Full-scale error EQ Quantization error • 16-bit modes • ≤13-bit modes ENOB Effective number 16-bit differential mode of bits • Avg = 32 • Avg = 4 16-bit single-ended mode • Avg = 32 • Avg = 4 12.0 4.8 — ±0.5 6 12.2 2. ADHSC = 1 Sample Time TUE Total unadjusted error Differential nonlinearity Min. Rev.Peripheral operating requirements and behaviors Table 20.4 4.0 ±0.7 ±0.9 6.9 13.0 5. Freescale Semiconductor. VREFL = VSSA) (continued) Symbol Description ADC asynchronous clock source Conditions1 • ADLPC = 1. 33 .4 -1 to 0 — -5.5 -4 -1.4 Typ.9 -0.9 14.02 × ENOB + 1. ADHSC = 0 • ADLPC = 1.5 Unit MHz MHz MHz MHz LSB4 Notes tADACK = 1/ fADACK fADACK See Reference Manual chapter for sample times • 12-bit modes • <12-bit modes • 12-bit modes • <12-bit modes — — — — — — — — — — ±4 ±1.8 — — bits bits LSB4 LSB4 VADIN = VDDA 5 -2.8 ±2.3 9.2 2.3 to 0.5 13.2 ±1.8 11. 16-bit ADC characteristics (VREFH = VDDA.1 6.7 to +1.76 — — bits bits dB 7 SINAD THD Signal-to-noise plus distortion Total harmonic distortion See ENOB 16-bit differential mode • Avg = 32 16-bit single-ended mode • Avg = 32 — — –94 -85 — — dB dB 7 SFDR Spurious free dynamic range 16-bit differential mode • Avg = 32 16-bit single-ended mode • Avg = 32 82 78 95 90 — — dB dB Table continues on the next page.1 to +1.4 -1.2 Max. Inc.9 -0. ADHSC = 1 • ADLPC = 0.. 3.1 -1. 9/19/2012.5 • <12-bit modes • 12-bit modes • <12-bit modes LSB4 5 ±6.2 6.2 11. ADHSC = 0 • ADLPC = 0. 1.4 ±0.

AVGS = %11) 6. Typical values are for reference only and are not tested in production. Inc. 34 Freescale Semiconductor. conversion rate and the ADLPC bit (low power). 7. 3.Peripheral operating requirements and behaviors Table 20. Typ. . VREFL = VSSA) (continued) Symbol EIL Description Input leakage error Conditions1 Min.2 IIn × RAS Max. Figure 7. fADCK = 2.0 V. ADC conversion clock < 12 MHz. 1 LSB = (VREFH . ADC conversion clock < 12 MHz. ADC conversion clock < 16 MHz. Unit mV Notes IIn = leakage current (refer to the MCU's voltage and current operating ratings) Temp sensor slope VTEMP25 Temp sensor voltage Across the full temperature range of the device 25 °C — — 1.0 MHz unless otherwise stated. the HSC bit must be clear with 1 MHz ADC conversion clock speed. The ADC supply current depends on the ADC conversion clock speed. Rev. ADC_CLK for 16-bit differential mode KL25 Sub-Family Data Sheet Data Sheet. For lowest power operation the ADLPC bit must be set. Temp = 25°C. Input data is 1 kHz sine wave. Max hardware averaging (AVGE = %1.VREFL)/2N 5. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA 2. Typical values assume VDDA = 3. 4. 3. Input data is 100 Hz sine wave. Typical ENOB vs.715 719 — — mV/°C mV 1. 16-bit ADC characteristics (VREFH = VDDA. 9/19/2012.

ADC_CLK for 16-bit single-ended mode 6.. PMODE = 1) Propagation delay. high-speed mode (EN = 1. 1. Freescale Semiconductor. 9/19/2012.. PMODE = 1) Supply current. 35 . low-speed mode (EN = 1. Typical ENOB vs. PMODE = 0) Analog input voltage Analog input offset voltage Analog comparator hysteresis1 — — — — VDD – 0.2 CMP and 6-bit DAC electrical specifications Table 21. high-speed mode (EN = 1.71 — — VSS — Typ. 3. — — — — — Max. 3. KL25 Sub-Family Data Sheet Data Sheet.5 — 20 80 5 10 20 30 — — 50 250 — — — — — 0. Comparator and 6-bit DAC electrical specifications Symbol VDD IDDHS IDDLS VAIN VAIO VH Description Supply voltage Supply current.6. Rev. low-speed mode (EN = 1. PMODE = 0) Min. Inc.Peripheral operating requirements and behaviors Figure 8.6 200 20 VDD 20 Unit V μA μA V mV Table continues on the next page.5 200 600 mV mV mV mV V V ns ns • CR0[HYSTCTR] = 00 • CR0[HYSTCTR] = 01 • CR0[HYSTCTR] = 10 • CR0[HYSTCTR] = 11 VCMPOh VCMPOl tDHS tDLS Output high Output low Propagation delay.

00E-03 140.7 1 1. 9/19/2012. VRSEL.7 1 1.9 2.3 Typ.00E-03 000.2 2. 2.5 0. PMODE = 1) 6.00E-03 60.Peripheral operating requirements and behaviors Table 21.00E-03 160. 40 — 0. — 7 — — Max.3 V.00E-03 0. Rev. Vin level (VDD = 3.5 2.6 Vinn (V) 1.00E-03 120.00E-03 80.8 3. PSEL.00E-03 40.1 0.3 Unit μs μA LSB3 LSB 1.5 2. Comparator and 6-bit DAC electrical specifications (continued) Symbol IDAC6b INL DNL Description Analog comparator initialization delay2 6-bit DAC current adder (enabled) 6-bit DAC integral non-linearity 6-bit DAC differential non-linearity Min. Vin level (VDD = 3.2 2.4 0.00E+00 0.5 –0.00E-03 CMP Hysteresis (V) 100.00E-03 CMP Hysteresis (V) 50.00E-03 20.1 Vinn (V) Figure 10. Typical hysteresis vs. 3. Typical hysteresis vs.00E-03 000.00E-03 HYS TCTR S etting 0 1 2 3 80.1 -20.9 2.4 0.00E-03 60. .7 V.00E-03 2 3 30.6. MSEL. — — –0.1 Figure 9.3 1. 36 Freescale Semiconductor.00E-03 HYSTCTR S etting 0 1 40. 3. Inc.00E-03 20.00E+00 0.3 V.3 12-bit DAC electrical characteristics KL25 Sub-Family Data Sheet Data Sheet.7 to VDD – 0. VOSEL) and the comparator output settling to a stable level.8 3. 1 LSB = Vreference/64 CMP Hysteresis vs Vinn 90. Comparator initialization delay is defined as the time between software writes to change control inputs (writes to DACEN.6 1.00E-03 70. PMODE = 0) CMP Hysteresis vs Vinn 180.00E-03 10. Typical hysteresis is measured with input voltage range limited to 0.3 1.

7 — — — — — ±0. DAC set to 0x000 DAC output voltage range high — highspeed mode. — — — — — — VDACR −100 — — — — — 60 — — — Table 23.. KL25 Sub-Family Data Sheet Data Sheet.6 90 — — 250 Unit μA μA μs μs μs mV mV LSB LSB LSB %FSR %FSR dB μV/C %FSR/C Ω 6 2 3 4 5 5 1 1 1 Notes IDDA_DACL Supply current — low-power mode IDDA_DACH Supply current — high-speed mode P tDACLP tDACHP Full-scale settling time (0x080 to 0xF7F) — low-power mode Full-scale settling time (0x080 to 0xF7F) — high-power mode tCCDACLP Code-to-code settling time (0xBF8 to 0xC08) — low-power mode and high-speed mode Vdacoutl Vdacouth INL DNL DNL DAC output voltage range low — high-speed mode. 250 900 200 30 1 100 VDACR ±8 ±1 ±1 ±0. 1. The DAC reference can be selected to be VDDA or the voltage output of the VREF module (VREF_OUT) 2.8 ±0. DAC set to 0xFFF Integral non-linearity error — high speed mode Differential non-linearity error — VDACR > 2 V Differential non-linearity error — VDACR = VREF_OUT Gain error Power supply rejection ratio.1 Symbol VDDA VDACR TA CL IL 12-bit DAC operating requirements Desciption Supply voltage Reference voltage Temperature Output load capacitance Output load current Table 22.4 V Temperature coefficient offset voltage Temperature coefficient gain error Output resistance load = 3 kΩ VOFFSET Offset error EG PSRR TCO TGE Rop Table continues on the next page.6 Unit V V °C pF mA 2 1 Notes Operating temperature range of the device — — 100 1 1.71 1.2 Symbol P 12-bit DAC operating behaviors Description Min. no load.3. 37 .1 — 3. — — 100 15 0.7 0. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC 6.4 ±0. Rev. 3.6.6. 12-bit DAC operating requirements Min. Inc. 12-bit DAC operating behaviors Typ.3. 3. no load. 9/19/2012. Freescale Semiconductor.Peripheral operating requirements and behaviors 6.000421 — Max.13 Max..6 3. VDDA ≥ 2.

Peripheral operating requirements and behaviors Table 23. Typ.4 V Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV VDDA = 3. 38 Freescale Semiconductor. 12-bit DAC operating behaviors (continued) Symbol SR Description Slew rate -80h→ F7Fh→ 80h • High power (SPHP) • Low power (SPLP) BW 3dB bandwidth • High power (SPHP) • Low power (SPLP) 550 40 — — — — 1. temperature range is across the full range of the device Figure 11. Inc. 4. 3. reference select set for VDDA (DACx_CO:DACRFS = 1). 3. 9/19/2012. 5. Settling within ±1 LSB The INL is measured for 0 + 100 mV to VDACR −100 mV The DNL is measured for 0 + 100 mV to VDACR −100 mV The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2. 6. Max.05 1. high power mode (DACx_C0:LPEN = 0). Rev. Unit V/μs Notes 1. digital code KL25 Sub-Family Data Sheet Data Sheet. 2.0 V. DAC set to 0x800. .12 — — kHz Min.7 0. Typical INL error vs.2 0.

39 . temperature 6.usb. Inc.org. Offset at half scale vs.7 Timers See General switching specifications. 9/19/2012. For the most up-to-date standards.8.Peripheral operating requirements and behaviors Figure 12. Freescale Semiconductor. 3.8 Communication interfaces 6. 6. KL25 Sub-Family Data Sheet Data Sheet. visit http://www.1 USB electrical specifications The USB electricals for the USB On-the-Go module conform to the standards documented by the Universal Serial Bus Implementers Forum. Rev.

USB VREG electrical specifications Symbol VREGIN IDDon IDDstby IDDoff Description Input supply voltage Quiescent current — Run mode. 5. load current equal zero Quiescent current — Shutdown mode • VREGIN = 5.6 3. pass-through mode External output capacitor External output capacitor equivalent series resistance Short circuit current 3 2.8. .Peripheral operating requirements and behaviors 6. as well as input signal transitions of 3 ns and a 30 pF maximum load on all SPI pins. The following tables provide timing characteristics for classic SPI timing modes. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad. Rev.6 V Quiescent current — Standby mode.1 1.6 V.1 Max. Inc.8.16 100 — V V V μF mΩ mA 2 — — — — 650 — — — — 4 120 1 nA μA mA mA Min.7 — — Typ.6 V • Run mode • Standby mode VReg33out COUT ESR ILIM Regulator output voltage — Input supply (VREGIN) < 3. unless noted. Table 25. fperiph/2048 Max.0 V. 9/19/2012. fperiph/2 Unit Hz Note 1 Table continues on the next page. 1 Symbol fop Description Frequency of operation Min.6 3.5 186 10 Unit V μA μA Notes 1.76 1 — 3. Temp = 25 °C unless otherwise stated. See the SPI chapter of the chip's Reference Manual for information about the modified transfer formats used for communicating with slower peripheral devices.8 — 2.3 SPI switching specifications The Serial Peripheral Interface (SPI) provides a synchronous serial bus with master and slave operations. 2.1 — 120 1. 3. load current equal zero.0 V and temperature=25C • Across operating voltage and temperature ILOADrun ILOADstby VReg33out Maximum load current — Run mode Maximum load current — Standby mode Regulator output voltage — Input supply (VREGIN) > 3.2 USB VREG electrical specifications Table 24. 6.2 — 290 3. Typical values assume VREGIN = 5. All timing is shown with respect to 20% VDD and 80% VDD thresholds. Many of the transfer attributes are programmable..3 2. 40 Freescale Semiconductor.1 2.. SPI master mode timing on slew rate disabled pads Num.6 8. input supply (VREGIN) > 3. KL25 Sub-Family Data Sheet Data Sheet. 2.

Inc. For SPI1 fperiph is the system clock (fSYS). 2 3 4 5 6 7 8 9 10 11 Symbol tSPSCK tLead tLag tWSPSCK tSU tHI tv tHO tRI tFI tRO tFO Description SPSCK period Enable lead time Enable lag time Clock (SPSCK) high or low time Data setup time (inputs) Data hold time (inputs) Data valid (after SPSCK edge) Data hold time (outputs) Rise time input Fall time input Rise time output Fall time output — 25 ns — Min. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS). For SPI0 fperiph is the bus clock (fBUS). 1 2 3 4 5 6 7 8 9 10 11 Symbol fop tSPSCK tLead tLag tWSPSCK tSU tHI tv tHO tRI tFI tRO tFO Description Frequency of operation SPSCK period Enable lead time Enable lag time Clock (SPSCK) high or low time Data setup time (inputs) Data hold time (inputs) Data valid (after SPSCK edge) Data hold time (outputs) Rise time input Fall time input Rise time output Fall time output — 36 ns — Min.25 Unit ns tSPSCK tSPSCK ns ns ns ns ns ns Note 2 — — — — — — — — 1. SPI master mode timing on slew rate enabled pads Num. SPI master mode timing on slew rate disabled pads (continued) Num. 2048 x tperiph — — 1024 x tperiph — — 10 — tperiph .Peripheral operating requirements and behaviors Table 25. 2. Freescale Semiconductor. 2. 9/19/2012.30 96 0 — 0 — Max.30 16 0 — 0 — Max.25 Unit Hz ns tSPSCK tSPSCK ns ns ns ns ns ns Note 1 2 — — — — — — — — 1. fperiph/2048 2 x tperiph 1/2 1/2 tperiph . 2 x tperiph 1/2 1/2 tperiph . Rev. tperiph = 1/fperiph Table 26. tperiph = 1/fperiph KL25 Sub-Family Data Sheet Data Sheet. fperiph/2 2048 x tperiph — — 1024 x tperiph — — 52 — tperiph . 41 . 3.

9/19/2012.30 Max. . MSB. bit 1. For LSBF = 1. bit order is LSB. 1 1. . bit 6. fperiph/4 — — — — Unit Hz ns tperiph tperiph ns Note 1 2 — — — Table continues on the next page.Peripheral operating requirements and behaviors SS1 (OUTPUT) 3 SPSCK (CPOL = 0) (OUTPUT) SPSCK (CPOL = 1) (OUTPUT) 2 5 5 10 11 4 10 11 6 MISO (INPUT) 7 MSB IN2 BIT 6 . . SPI master mode timing (CPHA = 1) Table 27. Rev.. . bit 6. MSB. . 0 4 x tperiph 1 1 tperiph . 1 2 3 4 5 Symbol fop tSPSCK tLead tLag tWSPSCK Description Frequency of operation SPSCK period Enable lead time Enable lag time Clock (SPSCK) high or low time Min. . 3. Inc. 1 9 LSB IN 8 MOSI 2 (OUTPUT)PORT DATA MASTER MSB OUT 1. bit order is LSB.... .. . . Figure 14.. SPI slave mode timing on slew rate disabled pads Num. 1 MASTER LSB OUT PORT DATA 2. . For LSBF = 1. Figure 13. KL25 Sub-Family Data Sheet Data Sheet. LSBF = 0. 42 Freescale Semiconductor..If configured as output BIT 6 . LSBF = 0. If configured as an output. .. 1 8 LSB IN 9 LSB OUT MOSI (OUTPUT) MSB OUT2 BIT 6 . SPI master mode timing (CPHA = 0) SS1 (OUTPUT) 2 SPSCK (CPOL = 0) (OUTPUT) SPSCK (CPOL = 1) (OUTPUT) 3 10 11 4 5 5 10 11 6 MISO (INPUT) 7 MSB IN2 BIT 6 . bit 1. 2.

2. 4. For SPI1 fperiph is the system clock (fSYS). Rev. 2.25 Unit Hz ns tperiph tperiph ns ns ns ns ns ns ns ns Note 1 2 — — — — — 3 4 — — — For SPI0 fperiph is the bus clock (fBUS). 43 . SPI slave mode timing on slew rate disabled pads (continued) Num. Freescale Semiconductor. fperiph/4 — — — — — — tperiph tperiph 122 — tperiph .30 2 7 — — — 0 — Max. Inc. 3. 6 7 8 9 10 11 12 13 Symbol tSU tHI ta tdis tv tHO tRI tFI tRO tFO 1. 4.Peripheral operating requirements and behaviors Table 27. tperiph = 1/fperiph Time to data active from high-impedance state Hold time to high-impedance state KL25 Sub-Family Data Sheet Data Sheet. 2 7 — — — 0 — Max. For SPI1 fperiph is the system clock (fSYS). 0 4 x tperiph 1 1 tperiph . Description Data setup time (inputs) Data hold time (inputs) Slave access time Slave MISO disable time Data valid (after SPSCK edge) Data hold time (outputs) Rise time input Fall time input Rise time output Fall time output — 25 ns — Min. 3. 3. — — tperiph tperiph 22 — tperiph . tperiph = 1/fperiph Time to data active from high-impedance state Hold time to high-impedance state Table 28. 1 2 3 4 5 6 7 8 9 10 11 12 13 Symbol fop tSPSCK tLead tLag tWSPSCK tSU tHI ta tdis tv tHO tRI tFI tRO tFO 1.25 Unit ns ns ns ns ns ns ns Note — — 3 4 — — — For SPI0 fperiph is the bus clock (fBUS). SPI slave mode timing on slew rate enabled pads Num. 9/19/2012. Description Frequency of operation SPSCK period Enable lead time Enable lag time Clock (SPSCK) high or low time Data setup time (inputs) Data hold time (inputs) Slave access time Slave MISO disable time Data valid (after SPSCK edge) Data hold time (outputs) Rise time input Fall time input Rise time output Fall time output — 36 ns — Min.

Peripheral operating requirements and behaviors SS (INPUT) 2 12 13 4 SPSCK (CPOL = 0) (INPUT) SPSCK (CPOL = 1) (INPUT) 3 5 5 12 13 9 8 MISO (OUTPUT) see note 6 MOSI (INPUT) NOTE: Not defined! SLAVE MSB 7 MSB IN 10 BIT 6 . . 1 SLAVE LSB OUT 9 BIT 6 . 1 11 11 SEE NOTE SLAVE LSB OUT BIT 6 .5 UART See General switching specifications. . SPI slave mode timing (CPHA = 0) SS (INPUT) 2 SPSCK (CPOL = 0) (INPUT) SPSCK (CPOL = 1) (INPUT) 4 12 13 3 5 5 12 13 10 MISO (OUTPUT) MOSI (INPUT) NOTE: Not defined! see note 8 SLAVE 6 MSB IN MSB OUT 7 11 BIT 6 . . 3. 44 Freescale Semiconductor.4 I2C See General switching specifications. . 1 LSB IN Figure 15. Rev. . . 6. . 1 LSB IN Figure 16. SPI slave mode timing (CPHA = 1) 6.8. KL25 Sub-Family Data Sheet Data Sheet.8. 9/19/2012. . . Inc.

9.freescale. TSI electrical specifications Symbol TSI_RUNF TSI_RUNV TSI_EN TSI_DIS TSI_TEN TSI_CREF TSI_DVOLT Description Fixed power consumption in run mode Variable power consumption in run mode (depends on oscillator's current selection) Power consumption in enable mode Power consumption in disable mode TSI analog enable time TSI reference capacitor Voltage variation of VP & VM around nominal values Min.1 TSI electrical specifications Table 29. 45 .1 Obtaining package dimensions Package dimensions are provided in package drawings. To find a package drawing. 3.com and perform a keyword search for the drawing’s document number: If you want the drawing for this package 32-pin QFN 48-pin QFN 64-pin LQFP 80-pin LQFP Then use this document number 98ASA00473D 98ASA00466D 98ASS23234W 98ASS23174W 8 Pinout KL25 Sub-Family Data Sheet Data Sheet.2 66 1. go to www. — 1. Inc.0 — Max — 128 — — — — 1. 9/19/2012.Dimensions 6.9 Human-machine interfaces (HMI) 6.0 — — — — 0. Rev.19 Type 100 — 100 1.03 Unit µA µA µA µA µs pF V 7 Dimensions 7. Freescale Semiconductor.

80 64 LQFP LQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 1 2 — — — — 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 48 QFN — — — — — — 1 2 3 4 5 6 7 8 — — 9 10 11 12 13 14 32 QFN 1 — — — — — — 2 3 4 5 6 — — — — 7 — — 8 — 9 Pin Name PTE0 PTE1 PTE2 PTE3 PTE4 PTE5 VDD VSS USB0_DP USB0_DM VOUT33 VREGIN PTE20 PTE21 PTE22 PTE23 VDDA VREFH VREFL VSSA PTE29 PTE30 Default DISABLED DISABLED DISABLED DISABLED DISABLED DISABLED VDD VSS USB0_DP USB0_DM VOUT33 VREGIN ADC0_DP0/ ADC0_SE0 ADC0_DM0/ ADC0_SE4a ADC0_DP3/ ADC0_SE3 ADC0_DM3/ ADC0_SE7a VDDA VREFH VREFL VSSA CMP0_IN5/ ADC0_SE4b DAC0_OUT/ ADC0_SE23/ CMP0_IN4 DISABLED DISABLED DISABLED SWD_CLK DISABLED DISABLED SWD_DIO NMI_b DISABLED TSI0_CH1 TSI0_CH2 TSI0_CH3 TSI0_CH4 TSI0_CH5 VDD VSS USB0_DP USB0_DM VOUT33 VREGIN ADC0_DP0/ ADC0_SE0 ADC0_DM0/ ADC0_SE4a ADC0_DP3/ ADC0_SE3 ADC0_DM3/ ADC0_SE7a VDDA VREFH VREFL VSSA CMP0_IN5/ ADC0_SE4b DAC0_OUT/ ADC0_SE23/ CMP0_IN4 PTE29 PTE30 TPM0_CH2 TPM0_CH3 TPM_CLKIN0 TPM_CLKIN1 PTE20 PTE21 PTE22 PTE23 TPM1_CH0 TPM1_CH1 TPM2_CH0 TPM2_CH1 UART0_TX UART0_RX UART2_TX UART2_RX ALT0 ALT1 PTE0 PTE1 PTE2 PTE3 PTE4 PTE5 SPI1_MOSI SPI1_SCK SPI1_MISO SPI1_PCS0 SPI1_MOSI ALT2 ALT3 UART1_TX UART1_RX ALT4 ALT5 ALT6 I2C1_SDA I2C1_SCL ALT7 RTC_CLKOUT CMP0_OUT SPI1_MISO 23 24 25 26 27 28 29 30 31 19 20 21 22 23 24 25 26 27 — 15 16 17 18 19 20 21 — — — — 10 11 12 13 14 — PTE31 PTE24 PTE25 PTA0 PTA1 PTA2 PTA3 PTA4 PTA5 PTE31 PTE24 PTE25 PTA0 PTA1 PTA2 PTA3 PTA4 PTA5 UART0_RX UART0_TX I2C1_SCL I2C1_SDA USB_CLKIN TPM0_CH4 TPM0_CH0 TPM0_CH1 TPM0_CH5 TPM2_CH0 TPM2_CH1 TPM0_CH0 TPM0_CH1 TPM0_CH2 SWD_DIO NMI_b I2C0_SCL I2C0_SDA SWD_CLK KL25 Sub-Family Data Sheet Data Sheet. 3. . The Port Control Module is responsible for selecting which ALT functionality is available on each pin. Inc. 9/19/2012.Pinout 8.1 KL25 Signal Multiplexing and Pin Assignments The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. 46 Freescale Semiconductor. Rev.

9/19/2012. 47 . 3. Freescale Semiconductor.Pinout 80 64 LQFP LQFP 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 28 29 — — — — 30 31 32 33 34 35 36 37 38 — — — — 39 40 41 42 43 44 48 QFN — — — — — — 22 23 24 25 26 27 28 29 30 — — — — 31 32 — — 33 34 32 QFN — — — — — — 15 16 17 18 19 20 21 — — — — — — — — — — — 22 Pin Name PTA12 PTA13 PTA14 PTA15 PTA16 PTA17 VDD VSS PTA18 PTA19 RESET_b PTB0/ LLWU_P5 PTB1 PTB2 PTB3 PTB8 PTB9 PTB10 PTB11 PTB16 PTB17 PTB18 PTB19 PTC0 PTC1/ LLWU_P6/ RTC_CLKIN PTC2 PTC3/ LLWU_P7 VSS VDD PTC4/ LLWU_P8 PTC5/ LLWU_P9 PTC6/ LLWU_P10 Default DISABLED DISABLED DISABLED DISABLED DISABLED DISABLED VDD VSS EXTAL0 XTAL0 RESET_b ADC0_SE8/ TSI0_CH0 ADC0_SE9/ TSI0_CH6 ADC0_SE12/ TSI0_CH7 ADC0_SE13/ TSI0_CH8 DISABLED DISABLED DISABLED DISABLED TSI0_CH9 TSI0_CH10 TSI0_CH11 TSI0_CH12 ADC0_SE14/ TSI0_CH13 ADC0_SE15/ TSI0_CH14 ADC0_SE11/ TSI0_CH15 DISABLED VSS VDD DISABLED DISABLED CMP0_IN0 CMP0_IN0 VSS VDD PTC4/ LLWU_P8 PTC5/ LLWU_P9 PTC6/ LLWU_P10 SPI0_PCS0 SPI0_SCK SPI0_MOSI UART1_TX LPTMR0_ ALT2 EXTRG_IN SPI0_MISO TPM0_CH3 CMP0_OUT TSI0_CH9 TSI0_CH10 TSI0_CH11 TSI0_CH12 ADC0_SE14/ TSI0_CH13 ADC0_SE15/ TSI0_CH14 ADC0_SE11/ TSI0_CH15 ADC0_SE8/ TSI0_CH0 ADC0_SE9/ TSI0_CH6 ADC0_SE12/ TSI0_CH7 ADC0_SE13/ TSI0_CH8 VDD VSS EXTAL0 XTAL0 PTA18 PTA19 PTA20 PTB0/ LLWU_P5 PTB1 PTB2 PTB3 PTB8 PTB9 PTB10 PTB11 PTB16 PTB17 PTB18 PTB19 PTC0 PTC1/ LLWU_P6/ RTC_CLKIN PTC2 PTC3/ LLWU_P7 I2C1_SCL SPI1_PCS0 SPI1_SCK SPI1_MOSI SPI1_MISO UART0_RX UART0_TX TPM2_CH0 TPM2_CH1 EXTRG_IN TPM0_CH0 CMP0_OUT TPM_CLKIN0 TPM_CLKIN1 SPI1_MISO SPI1_MOSI I2C0_SCL I2C0_SDA I2C0_SCL I2C0_SDA TPM1_CH0 TPM1_CH1 TPM2_CH0 TPM2_CH1 EXTRG_IN UART1_RX UART1_TX TPM_CLKIN0 TPM_CLKIN1 LPTMR0_ ALT1 ALT0 ALT1 PTA12 PTA13 PTA14 PTA15 PTA16 PTA17 SPI0_PCS0 SPI0_SCK SPI0_MOSI SPI0_MISO ALT2 ALT3 TPM1_CH0 TPM1_CH1 UART0_TX UART0_RX SPI0_MISO SPI0_MOSI ALT4 ALT5 ALT6 ALT7 57 58 59 60 61 62 63 45 46 47 48 49 50 51 35 36 — — 37 38 39 23 24 — — 25 26 27 I2C1_SDA UART1_RX TPM0_CH1 TPM0_CH2 CLKOUT KL25 Sub-Family Data Sheet Data Sheet. Inc. Rev.

KL25 Sub-Family Data Sheet Data Sheet.Pinout 80 64 LQFP LQFP 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 52 53 54 55 56 — — — — 57 58 59 60 61 62 63 64 48 QFN 40 — — — — — — — — 41 42 43 44 45 46 47 48 32 QFN 28 — — — — — — — — — — — — 29 30 31 32 Pin Name PTC7 PTC8 PTC9 PTC10 PTC11 PTC12 PTC13 PTC16 PTC17 PTD0 PTD1 PTD2 PTD3 PTD4/ LLWU_P14 PTD5 PTD6/ LLWU_P15 PTD7 Default CMP0_IN1 CMP0_IN2 CMP0_IN3 DISABLED DISABLED DISABLED DISABLED DISABLED DISABLED DISABLED ADC0_SE5b DISABLED DISABLED DISABLED ADC0_SE6b ADC0_SE7b DISABLED ADC0_SE6b ADC0_SE7b ADC0_SE5b ALT0 CMP0_IN1 CMP0_IN2 CMP0_IN3 ALT1 PTC7 PTC8 PTC9 PTC10 PTC11 PTC12 PTC13 PTC16 PTC17 PTD0 PTD1 PTD2 PTD3 PTD4/ LLWU_P14 PTD5 PTD6/ LLWU_P15 PTD7 SPI0_PCS0 SPI0_SCK SPI0_MOSI SPI0_MISO SPI1_PCS0 SPI1_SCK SPI1_MOSI SPI1_MISO UART2_RX UART2_TX UART2_RX UART2_TX UART0_RX UART0_TX TPM0_CH0 TPM0_CH1 TPM0_CH2 TPM0_CH3 TPM0_CH4 TPM0_CH5 SPI1_MISO SPI1_MOSI SPI0_MISO SPI0_MOSI ALT2 SPI0_MISO I2C0_SCL I2C0_SDA I2C1_SCL I2C1_SDA TPM_CLKIN0 TPM_CLKIN1 TPM0_CH4 TPM0_CH5 ALT3 ALT4 ALT5 SPI0_MOSI ALT6 ALT7 8. Many signals may be multiplexed onto a single pin. Rev.2 KL25 Pinouts The below figures show the pinout diagrams for the devices supported by this document. Inc. 3. 9/19/2012. 48 Freescale Semiconductor. see the previous section. . To determine what signals can be used on which pin.

49 PTA17 PTA18 PTA1 PTA2 PTA4 VDD VSS . 9/19/2012. Rev. Freescale Semiconductor. Inc. 3.Pinout PTD6/LLWU_P15 PTD4/LLWU_P14 PTC6/LLWU_P10 PTC12 PTC13 PTC11 PTC10 PTD2 PTD7 PTD5 PTD3 PTD1 PTC9 PTC8 PTD0 71 PTC7 PTC5/LLWU_P9 62 PTC17 79 75 72 69 80 78 76 68 70 67 66 65 64 77 74 PTE0 PTE1 PTE2 PTE3 PTE4 PTE5 VDD VSS USB0_DP USB0_DM VOUT33 VREGIN PTE20 PTE21 PTE22 PTE23 VDDA VREFH VREFL VSSA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 25 26 28 29 31 23 24 27 32 35 30 36 33 34 37 38 39 40 73 63 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 PTC4/LLWU_P8 PTC16 VDD VSS PTC3/LLWU_P7 PTC2 PTC1/LLWU_P6/RTC_CLKIN PTC0 PTB19 PTB18 PTB17 PTB16 PTB11 PTB10 PTB9 PTB8 PTB3 PTB2 PTB1 PTB0/LLWU_P5 RESET_b PTA19 PTE29 PTE30 PTE25 PTA0 PTA3 PTA5 PTE31 PTE24 PTA12 PTA15 PTA16 PTA13 PTA14 Figure 17. KL25 80-pin LQFP pinout diagram KL25 Sub-Family Data Sheet Data Sheet.

Inc. PTA18 PTA1 PTA2 PTA5 VDD . KL25 64-pin LQFP pinout diagram KL25 Sub-Family Data Sheet Data Sheet.Pinout PTD6/LLWU_P15 PTD4/LLWU_P14 PTC6/LLWU_P10 PTD0 PTC9 PTD7 PTC8 61 62 59 55 52 51 PTC5/LLWU_P9 50 PTC11 PTD3 PTD1 58 64 60 57 56 54 PTE0 PTE1 VDD VSS USB0_DP USB0_DM VOUT33 VREGIN PTE20 PTE21 PTE22 PTE23 VDDA VREFH VREFL VSSA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 21 22 25 26 23 24 27 28 29 31 17 18 19 20 30 63 53 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 PTC4/LLWU_P8 PTC10 PTD5 PTD2 PTC7 VDD VSS PTC3/LLWU_P7 PTC2 PTC1/LLWU_P6/RTC_CLKIN PTC0 PTB19 PTB18 PTB17 PTB16 PTB3 PTB2 PTB1 PTB0/LLWU_P5 RESET_b PTA19 PTE30 PTE31 PTE29 PTE24 PTE25 PTA0 PTA3 PTA12 PTA13 PTA4 VSS Figure 18. 3. 9/19/2012. 50 Freescale Semiconductor. Rev.

Pinout PTD6/LLWU_P15 PTD4/LLWU_P14 PTC6/LLWU_P10 PTC5/LLWU_P9 38 48 46 45 47 44 43 42 41 40 39 37 PTC4/LLWU_P8 PTD7 PTD5 PTD3 PTD2 PTD1 PTD0 PTC7 VDD VSS USB0_DP USB0_DM VOUT33 VREGIN PTE20 PTE21 VDDA VREFH VREFL VSSA 1 2 3 4 5 6 7 8 9 10 11 12 21 22 23 13 14 15 16 17 18 19 20 24 36 35 34 33 32 31 30 29 28 27 26 25 PTC3/LLWU_P7 PTC2 PTC1/LLWU_P6/RTC_CLKIN PTC0 PTB17 PTB16 PTB3 PTB2 PTB1 PTB0/LLWU_P5 RESET_b PTA19 PTE24 PTE25 PTA1 PTA2 PTE29 PTE30 PTA0 PTA3 PTA4 VDD Figure 19. Inc. Freescale Semiconductor. KL25 48-pin QFN pinout diagram KL25 Sub-Family Data Sheet Data Sheet. Rev. 51 PTA18 VSS . 3. 9/19/2012.

9/19/2012. No. initial public release. Inc. Completed all the TBDs. Table 30. 3. Revision History Rev. 52 Freescale Semiconductor. 1 2 3 Date 7/2012 9/2012 9/2012 Substantial Changes Initial NDA release. Updated Signal Multiplexing and Pin Assignments table to add UART2 signals. KL25 32-pin QFN pinout diagram 9 Revision History The following table provides a revision history for this document.Revision History PTD6/LLWU_P15 PTD4/LLWU_P14 PTC6/LLWU_P10 PTC5/LLWU_P9 26 32 31 29 30 28 27 25 PTC4/LLWU_P8 PTD7 PTD5 PTC7 PTE0 VSS USB0_DP USB0_DM VOUT33 VREGIN VDDA VSSA 1 2 3 4 5 6 7 8 10 11 12 13 14 15 16 9 24 23 22 21 20 19 18 17 PTC3/LLWU_P7 PTC2 PTC1/LLWU_P6/RTC_CLKIN PTB1 PTB0/LLWU_P5 RESET_b PTA19 PTA18 PTA1 PTA2 PTE30 VDD PTA0 PTA3 Figure 20. KL25 Sub-Family Data Sheet Data Sheet. Rev. PTA4 VSS .

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