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# http://www.tutorialspoint.com/computer_logical_organization/sequential_circuits.htm The combinational circuit does not use any memory.

Hence the previous state of input does not have any effect on the present state of the circuit. But sequential circuit has memory so output can vary based on input. This type of circuits uses previous input output cloc! and a memory element. Bloc! diagram Bloc! "iagram of sequential circuit #lip #lop

#lip flop is a sequential circuit which generally samples its inputs and changes its outputs only at particular instants of time and not continuously. #lip flop is said to be edge sensitive or edge triggered rather than being level triggered li!e latches. \$%& #lip #lop

't is basically \$%& latch using ()(" gates with an additional enable input. 't is also called as level triggered \$&%##. #or this circuit in output will ta!e place if and only if the enable input *+, is made active. 'n short this circuit will operate as an \$%& latch if +- . but there is no change in the output if + - /. Bloc! "iagram Bloc! "iagram of \$& #lip #lop 0ircuit "iagram 0ircuit "iagram of \$& #lip #lop Truth Table Truth Table of \$& #lip #lop 1peration \$.(. . 0ondition 1peration

\$ - & - / : (o change

'f \$ - & - / then output of ()(" gates 2 and 3 are forced to become ..

Hence &4 and \$4 both will be equal to .. \$ince \$4 and &4 are the input of the basic \$%& latch using ()(" gates there will be no change in the state of outputs.

## \$-/ &-. +-.

\$ince \$ - / output of ()("%2 i.e. &4 - . and + - . the output of ()("%3 i.e. \$4 - /.

## 1utput of ()("%2 i.e. &4 - / and output of ()("%3 i.e. \$4 - ..

Hence output of \$%& ()(" latch is 6n7. - . and 6n7. bar - /. This is the reset condition.

## \$-. &-. +-.

)s \$ - . & - . and + - . the output of ()(" gates 2 and 3 both are / i.e. \$4 - &4 /.

Hence the &ace condition will occur in the basic ()(" latch.

## 8aster \$lave 9: #lip #lop

8aster slave 9: ## is a cascade of two \$%& ## with feedbac! from the output of second

to input of first. 8aster is a positive level triggered. But due to the presence of the inverter in the cloc! line the slave will respond to the negative level. Hence when the cloc! - . *positive level, the master is active and the slave is inactive. ;hereas when cloc! - / *low level, the slave is active and master is inactive. 0ircuit "iagram 0ircuit "iagram of 9%: #lip #lop Truth Table Truth Table of 9%: #lip #lop 1peration \$.(. . 0ondition 1peration

9 - : - / *(o change,

;hen cloc! - / the slave becomes active and master is inactive. But since the \$ and & inputs have not changed the slave outputs will also remain unchanged. Therefore outputs will not change if 9 - : -/.

9 - / and : - . *&eset,

0loc! - .: 8aster active slave inactive. Therefore outputs of the master become 6. / and 6. bar - .. That means \$ - / and & -..

0loc! - /: \$lave active master inactive Therefore outputs of the slave become 6 - / and 6 bar - ..

)gain cloc! - .: 8aster active slave inactive. Therefore even with the changed outputs 6 - / and 6 bar - . fed bac! to master its outputs will 6. - / and 6. bar - .. That means \$ - / and & - ..

Hence with cloc! - / and slave becoming active the outputs of slave will remain 6 - / and 6 bar - .. Thus we get a stable output from the 8aster slave.

9 - . and : - / *\$et,

0loc! - .: 8aster active slave inactive. Therefore outputs of the master become 6. . and 6. bar - /. That means \$ - . and & -/.

0loc! - /: \$lave active master inactive Therefore outputs of the slave become 6 - . and 6 bar - /.

)gain cloc! - .: then it can be shown that the outputs of the slave are stabilized to 6 - . and 6 bar - /.

9 - : - . *Toggle,

0loc! - .: 8aster active slave inactive. 1utputs of master will toggle. \$o \$ and & also will be inverted.

## 0loc! - /: \$lave active master inactive. 1utputs of slave will toggle.

These changed output are returned bac! to the master inputs. But since cloc! - / the master is still inactive. \$o it does not respond to these changed outputs. This avoids the multiple toggling which leads to the race around condition. The master slave flip flop will avoid the race around condition.

## "elay #lip #lop / " #lip #lop

"elay #lip #lop or " #lip #lop is the simple gated \$%& latch with a ()(" inverter connected between \$ and & inputs. 't has only one input. The input data is appearing at the output after some time. "ue to this data delay between i/p and o/p it is called delay flip flop. \$ and & will be the complements of each other due to ()(" inverter. Hence \$

- & - / or \$ - & - . these input condition will never appear. This problem is avoid by \$& - // and \$& - . conditions. Bloc! "iagram Bloc! "iagram of " #lip #lop 0ircuit "iagram 0ircuit "iagram of " #lip #lop Truth Table Truth Table of " #lip #lop 1peration \$.(. . 0ondition +-/ 1peration

## <atch is disabled. Hence is no change in output.

+ - . and " - /

'f + - . and " - / then \$ - / and & - .. Hence irrespective of the present state the ne=t state is 6n7. - / and 6n7. bar - .. This is the reset condition.

+ - . and " - .

if + - . and " - . then \$ - . and & - /. This will set the latch and 6n7. - . and 6n7. bar - / irrespective of the present state.

## Toggle #lip #lop / T #lip #lop

Toggle flip flop is basically a 9: flip flop with 9 and : terminals permanently connected together. 't has only input denoted by T is shown in the \$ymbol "iagram. The symbol for

positive edge triggered T flip flop is shown in the Bloc! "iagram. \$ymbol "iagram \$ymbol "iagram of T #lip #lop Bloc! "iagram Bloc! "iagram of T #lip #lop Truth Table Truth Table of T #lip #lop 1peration \$.(. . 0ondition 1peration

T-/ 9-:-/

T-. 9-:-.