56 views

Uploaded by Thanasis Stam

buck converter design

save

- Buck Converter
- buck converter
- Buck converter
- Buck converter
- Simulation of Buck Boost Converter
- BUCK Converter Desig Kit
- Buck converters
- Boost Converter
- Buck Converter
- Buck Converter Basics
- Buck Converter
- Buck Converter
- Buck Converter
- Buck Converter Design Example
- Buck Converter
- LED Lighting Management Solutions
- Non-Isolation Soft-Switching Buck Conve r t e r For
- ZXLD1362
- (Fix)Gaincontrol 2011
- datasheet lnk3204
- 5. Questions & Answers on Application of Diodes
- DC to DC converter
- Data Sheet
- chap02
- AEI305
- Wireless Remote Control
- project work-converted.pptx
- 369-4258-1-PB
- Unbalance in Power Systems.pdf
- Fundamental of Electric Traction Drives.pdf
- A European Benchmarking of Voltage Quality Regulation
- VSC-HVDC Control Under Unbalanced Supply Conditions
- Study on High Voltage Capacitor Unbalance Protection in HVDC Projects
- classification methodologies of power quality.pdf
- VOLTAGE UNBALANCE.pdf
- Battery Energy Storage for Intermittent Renewable Electricity Production
- A European Benchmarking of voltage quality regulation.pdf
- Dynamic Study Model for the Interconnected Power Systems of Europe in Different Simulation Tools
- Modeling and Simulation of the Propagation of Harmonics in Electric Power Networks Part II
- 00551343
- Effects of Balanced and Unbalanced Distribution System Modeling on Power Flow Analysis
- VOLTAGE UNBALANCE.pdf
- An Analytical Approach for Stohastic Assessment of Balanced and Unbalanced Voltage Sags in Large Systems
- Cigre_power quality indices and objectives.pdf
- Application Guide PSCAD 2007
- AT1
- railway electrification 25kV Ac design on British Railway.pdf
- FACTS for AVAILABILITY and Power Quality Improvement in High Speed Railway Electrification
- contributions towards the development of iec61000-3-13 on voltage unbalance.pdf
- Unbalance in Power Systems
- Short-circuit analysis of the onsite electric power system at Ringhals unit 4.pdf
- Fundamental of Electric Traction Drives.pdf
- Fault Impedance Calculation as Autotransformer Tab change in traction power supply system.pdf
- 43X II Service Manual
- classification methodologies of power quality.pdf
- Voltage Unbalance Emission Limits for Installations – General Guidelines and System Specific Considerations
- TRACTION POWER SUPPLY SYSTEM FOR California high speed train project.pdf
- LOAD FLOW METHOD FOR UNBALANCED SYSTEMS.pdf

You are on page 1of 7

Zheng Zhang Department of Electrical Engineering and Computer Science, MIT Email: z zhang@mit.edu Submitted on May 16, 2012

Abstract—This report presents the design procedure of a buck converter, which converts a 22V∼32V DC input voltage to a 15V DC output, under a resistive load variation from 1.5Ω to 4.5Ω. Detailed analysis and simulation results, as well as electrical and thermal device speciﬁcations are provided. A voltage-mode PI controller is designed to stabilize the averaged system under input and load variations. The worst-case efﬁciency of this buck converter is above 94.59%.

S Is V1

q(t)

+VD D -

Lo ILo +Vo Ro Co -

ID

I. D ESIGN R EQUIREMENTS The design requirements of the electrical parameters for the buck converter are listed in Table I.

TABLE I D ESIGN R EQUIREMENTS . Input voltage range Input voltage transient limit Output power range Output voltage (static) Output voltage (transient) Output voltage ripple (p-p value) Input current ripple (p-p value, ideal source) Efﬁciency 22 ∼ 32 V 44 V for up to 1 ms 50 ∼ 150 V 15 V±3% 15 V±20% ≤ 100 mV ≤ 100 mA ≥ 88% Fig. 1. Top-level schematic of a buck converter.

Besides, it is required that the junction temperature of the power devices should remain sufﬁciently (at least 25◦ C) below the allowable maximum junction temperature, while the ambient temperature is in the range of −20◦ C∼ +50◦ C. It is also required that the temperature rise of inductor should be below 50◦ C. II. T OP -L EVEL D ESIGN V IEW As shown in Fig. 1, assume that the duty ratio of the switch is d and the input DC voltage is V1 , then the output DC voltage can be decided as Vo = dV1 . (1) And the power at the output stage is Po = Vo2 /Ro . (2)

1) The switching frequency shall be high enough, since as fsw gets higher the ripples in iLo and vo become smaller; 2) The switching frequency cannot be arbitrarily high. As fsw increases, the switching losses in the power devices will increases. Meanwhile, the core power loss and loss due to the skin effects also become more signiﬁcant as fsw increases. The following main problems need to be addressed in our design: 1) The output stage should be designed such that the output voltage has small ripples. 2) An input EMI ﬁlter should be added between the switch and the input source, to ensure that the current ﬂowing through the input source has small ripples. 3) The circuit should be designed such that this DC buck converter can work well under load variations from 1.5Ω to 4.5Ω (or vise versa). 4) The power and passive devices and thermal devices should be carefully selected such that designed circuit works well under parasitic and thermal effects. 5) As the input voltage change in the range of 22 ∼ 32 V, the duty ratio d should be tuned according to the input level to ensure Vo stay at 15 V. This requires us to design a feedback controller to form a stable close-loop system such that the output stays at the nominal value. III. C IRCUIT S CHEMATIC D ESIGN A. Output Stage The output stage is designed under two constraints: 1) The inductor Lo should be large enough to make the current rippels of iLo small enough;

Since Vo = 15 V, and Po = 50 ∼ 150 W, the load resistance Ro can vary in the range of 1.5 ∼ 4.5Ω. And accordingly, the averaged current through the inductor shall vary in the range of 10 3 ∼ 10 A. In our design, we see V1 = 27 V and d = 5 9 as the nominal design. The switching frequency is set as fsw = 200 KHz based on the following tradeoffs:

we can model the output stage by a current source and get an equivalent circuit for analyzing the input current of this converter. as shown in the left part of Fig.4A.ac is odd in time and its n-th Fourier coefﬁcient can be easily obtained as 2IL .5I Lo. we can add a damped LC ﬁlter. B. To ensure the peak-to-peak value of the inductor current below a speciﬁed bound δ1 . and thus g (s ) ≈ 1 ix ( s ) = L 2 is. the output voltage ripple (peak-to-peak value) can be computed as Vo.p-p Fig. we can select δ2 = 0.ac = (9) 2) The capacitor Co should be large enough to make the voltage ripple of vo small enough. (10) nπ We only consider the fundamental harmonic. Lo Lo V1 (3) which approaches the maximum (worst-case) value when V1 = 32V.5. (11) where g (s) is the transfer function from switch current to input current. Since the switch current is (t) ≈ ILo when the switch turns on and is (t) = 0 when the switch turns off. otherwise. We notice that when s = 0. 3. In Laplace domain n Is. and this ac current all ﬂows through Co .5 µF. since in this case the ac component of is. EMI filter Lf Rd V1 Cf Cd Fig. the waveform of which is plotted in the right part of Fig. 3. For simplicity. The buck converter with an EMI input ﬁlter. we perform the ac analysis using V1 =30 and d = 0.ac i s. since the higherorder harmonics in the input current are negligible due to the low-pass property of the damped EMI ﬁlter. (5) The ac component of iLo is shown in Fig.ac dt = t1 IL.ac (s). The input current of this circuit model is in fact the ac component of the switch current. 8δ2 (7) in the frequency band of interest.1 V and lead to Co ≥ 3. Therefore. 8Co (6) Given an upper bound δ2 for Vo.p−p = 1 Co t2 ix (s) = g (s)is. 2. we need to reduce its ac component ix . we remarkably increase Co and slightly increase Lo which leads to smaller inductor current ripples. δ1 δ1 (4) Here we choose δ1 = 1. 2 Iin Po (13) .ac dT T t -0. as shown in Fig.p−p T .ac dT t1 t2 T 2T t Lf ix Cf Rd Cd -dILo (1-d)ILo i s.p−p . 20lg|g (s)| = 0.46 µH. Input-Stage EMI Filter To reduce the current ripples of the input stage.p−p T . Right: waveform of the ac component of the switch current. the peak-to-peak current of Lo can be computed as ILo.5I Lo. and |g (s)| decreases by 40 dB/Dec when ω > √1 . much smaller output voltage ripples and much smaller transient peak of vo . Left: the ac signal model to analyze input current ripple. the maximum transient magnitude of Vo would decrease. AC component of the current through inductor Lo . we select Co = 100 µF. 4. Lo = 31.5 µH. the capacitance should be selected according to Co ≥ IL. When the switch turns on VD = V1 and vLo = V1 − Vo = V1 − 15. S Is q(t) +VD D Lo ILo +Vo Ro Co - ID Our simulation results show that when we increases Co and decreases Lo . Based on the data sheet information.. We can select a large damping capacitor Cd such that 2πfsw Cd 1/Rd .8438 32 T = µH. 4. 2. the inductor value should be Lo ≥ 15 − 225 39. (8) There is a “negative resistance” under constant power transfer (seen from the switch). Denote the voltage across the inductor Lo as vLo .0. Based on this observation.p-p iLo. Assume that capacitor Co is large enough. which is calculated as rl = − Po −V12 = . then we have Lo ≥ 28. 4.ac (s) +1 s Lf Cf + s Rf d (12) iL. the diode turns on and vLo = −15 V. To reduce the ripple of the input current.p−p = 1 15 1 (V1 − 15) dT = (V1 − 15) T. C f Lf Since it is required that Vo.p−p ≤ 1 mV. Fig.

we set V1 = 32 V and d = 0.3662sin(2πfsw t). and then it was changed to 4. We consider the worst case: ILo = 10 A.113 × 105 rad/ sec . we select Rd = 0. which shows that Vo. we can select Lf and Cf such that 40 lg (2πfsw ) − lg from which we get 1 ≤ 1.2267Ω when V1 = 22 V.1 mV and the average value is 14.6818. To make 2πfsw Cd 1/Rd .5Ω. 6. Simulation Results Using the above speciﬁed design parameters. the magnitude of the fundamental component of is. Rd should be adequately below 3.735 V.3mF and Rd = 0. we select Cd = 3. Steady-state waveform of the input current. and thus the ac component of the switch current can be well ﬁltered. The minimum value of |rl | is 3.5Ω and d = 0. 9.2267Ω. To make the EMI ﬁlter well damped. Transient behavior of the output voltage. 8. Clearly. the load is ﬁrst set as 1. π (14) To make the ripple of the input current below δ3 = 100 mA. 1) Output Voltage: As shown in Fig.ac is i1 s. 5. 10 shows the transient behavior of the current through ILo . we select Cf = 20µF and Lf = 9µ H. Steady-state waveform of the output voltage. which occurs when the output power is 150 W. when the load is 1.p−p = 8. 7.5Ω. At fsw = 20 KHz. 6. C. In this simulation.ac = 2ILo sin(2πfsw t) = 6. the magnitude of g (s) is plotted in Fig. the averaged value is 3. |g (s)| is −49 dB. the averaged value is 10 A. 7. 2) Input Current: To see the worst-case input current ripple. Circuit schematic used for simulation of the steady-state and transient behavior of Vo . delivering 50- . which leads to √ 1 = 7. showing the worst-case voltage ripple. The steady-state waveform of Vo is plotted in Fig. 3) Output Power: Fig. In our design. 8. The circuit schematic used for simulation is shown in Fig.4Ω. leading to 150-W output power.4Ω.45 × 104 rad/sec. showing the transient limit.4688 to check the transient and steady-state waveforms of Vo . Clearly.3 mF.33 A. this EMI ﬁlter is a well-damped low-pass ﬁlter. the worst-case peak-to-peak value is 27 mA.3662) − lg With Cf = 20µF. the maximum output voltage is about 17. In this case. Fig. When the load is 4.8 V. 9. Magnitude of the transfer function g (s) (current gain of the EMI Fig. As shown in Fig. ﬁlter).5Ω. 5. Lf = 9µH.0 20lg(|g(jω)|) −50 −100 −150 −2 0 2 4 6 8 10 10 10 10 ω (rad/sec) 10 10 10 10 Fig. C f Lf Fig.5Ω. during the steps between the minimum and maximum load. leading to very small ripples in the input current. To be on the safe side. we set the input voltage as 22 V. showing the worst-case ripples. Cd = 3. Ro = 1. Fig. C f Lf (16) √ 1 C f Lf δ3 2 (15) ≥ 20 lg (6.

the switching loss is 1 Po Po Psw. therefore use the 20-µF CS4 capacitor for the LC ﬁlter. the worst-case power loss happens when Po = 150 W.6 0. leading to the worst-case conduction loss max (Pd.on + Psw. 4) Summary: The simulated performance parameters are summarized in Table II.65 0.worst−case = max (Pd.5 mΩ and the parasitic inductance is 11 nH.0934 W. (19) Clearly shown in (17) and (18). At the maximum allowable temperature 175◦ C . (18) 2 Vo 2d To make the total loss small.6 A and the averaged current is 0.on = dILo Rds = d 2 0 CV dV ≈ 0. 11.40 W (23) which is very small compared with the conduction loss.0322 Ω. The maximum peak-to-peak current of this inductor is 1.on ) + Pd. which is negligible compared with the damping resistor. and the maximum current can be around 0.cap = 2. Fig. Transient behavior of the current through output-stage inductor Lo. (21) Pd. switching loss and total loss are plotted in Fig. Therefore.1 mV 27 mA 2) Diode: Since the maximum reverse voltage is 32 V and the maximum forward current can be 10 A. Switching frequency Input voltage range Output power range Output voltage (static) Maximum output voltage (transient) Maximum output voltage ripple (p-p value) Maximum input current ripple (p-p value) 200 KHz 22 ∼ 32 V 50 ∼ 150 V 15 V±1. the listed electrical parameters all meet the corresponding design requirements. 3) Co : Simulation results show that the peak-to-peak current of this capacitor is around 0.2 A when V1 = 32 V.45 conduction loss switching loss total loss 0. With tr = 78 ns and tf = 34ns. In our design.82 A. Since Vo = 15 V.3 = 0. 10. (17) Vo where Rds is the drain-to-source resistance at the maximum allowable junction temperature.7 d (duty ratio) Fig. The switching loss can be calculated as the sum of the loss during the rise and fall time.3-mF U767D capacitor.6 A. E LECTRICAL AND T HERMAL D EVICE S ELECTION A. the drain-to-source resistance is 2 Psw.014 × 2. 11 as functions of the duty ratio. Switch and Diode 1) Switch: The worst-case conduction loss of the switch is Po Rds . (22) The worst-case discharge loss due to the diode capacitance can be calculated as 32 Pd. C. maximum worst−case power loss 6 5 4 3 2 1 0. Since the maximum drain-too source voltage is V1 and the maximum current is ILo = P Vo .52 W. showing the output power range. The simulation results in Fig. IRFZ48N Power MOSFET is selected due to the good tradeoff between Rds and tr + tf .67% 17. (26) Awire .5 0. the worst-case conduction loss. which allows the simulated capacitor current.rf = V1 (tr + tf ) fsw = (tr + tf ) fsw . There is a constraint for the wire area Awire by the maximum current density: Iin.on = ILo (1 − d)VF = Vo where VF is the forward voltage at the maximum allowable junction temperature.rf ) = 5. min V1 ) (25) Rds = 0. (24) B. The parasitic resistance of this capacitor is about 11 mΩ. we select 30CPQ45 as our diode device.12 W. Clearly. the worst-case diode power loss is Pd. Passive Components: Capacitors 1) Cf : The simulation results show that the current through Cf can approach 7 A. Clearly.4 F.67%) 8.55 0.max 2 ≤ 500 A/cm . 11 show that the maximum worstcase switch device loss is Psw. the worst-case conduction loss is obtained when Po = 150W and d = 15 32 . we select the 100-µF HD-series capacitor. (20) which occurs when d = 15 32 . The conduction loss is Po (1 − d)VF .max = max (Po ) = 6.on ) = 2. Loss of the IRFZ48N Power MOSFET under different duty ratios. TABLE II S IMULATION RESULTS OF THE PROPOSED DESIGN .cap = fsw IV.W power to the load. In this case ILo = 10 A and VF = 0. we should select a switch that has small conduction resistance and small rise/fall time.worst−case = max (Psw.8 V (+18. therefore we use the 3. Passive Components: Inductors 1) Lf : The maximum input current is Iin. The parasitic resistance of this capacitor is 2. 2) Cd : The maximum voltage across Cd is around 32 V (when V1 = 32 V).

core + PLo. The resulting wire resistance is RLo = N × lturn × ρcu. we select ML73/1. (44) In our estimation. ambient temperature TA .2282 × 10−3 T. Ac is the effective core area.(31) and (35).CS = 0. β max (PLf.max Bmax = < Bmax (27) N Ac where N is the turn number. the thermal resistance of which is 16.1158 W. 0. β (35) where Ploss is the total power loss which can be calculated as Ploss = Psw.worst−case = max (PLf. we have many choices for the heat sink.The second constraint is that the maximum ﬂux density Bmax should be below the saturated ﬂux density Bsat .10◦ C/W.SA : TJ = TA + Pdiss (Rθ. and we require the junction temperature is at least 25◦ C below the maximum allowable temperature at the device junction speciﬁed by the data sheet.00249 = 0. The wire resistance of the inductor is RLf = N × lturn × ρcu. for the output-stage inductor Lo the maximum winding loss can be calculated as max (PLo.max = PLf.RM10 = 3. we have the worst-case winding loss for Lf : For the inductor Lf . the worst-case loss of Lf is PLf.winding ) = 102 × 0. the calculated worst-case power loss is 2. (21). and the speciﬁed maximum allowable junction temperature is 150◦ C. we use the RM12/I core set.JC + Rθ.e. and ρcu. From the simulation results we know that the minimum power efﬁciency is ηmin = 94.40 W) for Pd. Bac. 2) Lo : The output-stage inductor Lo can be designed in a similar way. (40) where lturn = 52 mm is the average length of turn.7◦ C/W. Heat Sinks The junction temperature of a power device can be expressed as a function of the power dissipation Pdiss . the calculated worst-case device loss is 5.cap + PLf.52 (42) Therefore.peak ) Vcore = 7.winding + PLo. Fig.CS = 0.15 mW.winding ) = 6. (34) Similarly. (39) (38) Note that the practical minimum power efﬁciency can be larger. β = 2.15 − 0. 2. we have many choices for the heat sink. i.winding ) + PLf. therefore. Lf Iin.6239 W.0943 Therefore.42◦ C/W. Therefore.63. In our design.on + Psw. From the data sheet we have Rθ.JC . we assume that TA = 50◦ C.core . the thermal resistance of which is 11. (31) When Po = 150 W and V1 = 22 V.59%.83 mm. Rθ.SA ) .peak ) Vcore = 0.35◦ C.JC = 1. . we have CM = 2.wire = 7. the maximum temperature rise is ∆TLf. we know that the power efﬁciency η depends on the duty ratio d and output power Po . (32) Since our design should work for the worst case.006161 = 0.45.max = PLo. Power Efﬁciency The power efﬁciency can be estimated as η= Po Po + Ploss (43) (33) which is much smaller than the winding loss. The maximum temperature rise for the inductor Lo is ∆TLo.winding ) + PLf..worst−case × Zθ. fsw = 2 × 105 Hz.80 mW.10 − 0.worst−case = max (PLf.. with AL = 250 nH and N = 6. The diameter of the wire (size-13 copper wire) is dwire = 1. case-to-sink thermal resistance Rθ.JC = 1.e. According to (17).core = CM fsw (Bac. The core loss is 2 PLo. α = 1. (37) 4) Temperature Rise of Inductors: For the inductor Lf .6161 W.98◦ C/W.52 W.winding = ILf RLf = Po V1 2 RLf . 1) Heat Sink for the Switch: For the IRFZ48N Power MOSFET. In our design. (41) Rθ.161 mΩ. and the speciﬁed maximum allowable junction temperature is 175◦ C.SA ≤ − 1.24 = 28. Based on these two constraints.wire = 6.cap . For this inductor. we use ML24 to remove the heat of the diode.core = 0. We use the size-14 copper wire (diameter is 1.worst−case × Zθ.core = CM fsw (Bac.CS + Rθ.CS and sink-to-ambient thermal resistance Rθ. 12 has plotted η as a function of d and Po . the core loss can be decided as 2 PLf. therefore. since in our calculation the worst-case Pd.50◦ C/W. therefore. we select the RM10/I core set.5 × 10−4 . (18).0943 W.peak ≈ 2.31cm3 .99 × 10−3 Ω/m is the resistivity of size-13 copper wire. the heat sink thermal resistance should be 175 − 25 − 50 − 1. and Vcore = 4.cap is used.core = 0.0◦ C/W.15◦ C/W.5 as the heat sink.wire = 2.49 mΩ (29) (28) D.48◦ C. From the data sheet we have Rθ. with AL = 315 nH and N = 10.SA ≤ 5. Rθ.63 mm).rf + Pd. E. we use the worst-case capacitance discharge loss (i.24◦ C/W. (45) (36) THE worst-case loss of Lo is PLo.RM12 = 14. The winding loss of inductor Lf is 2 PLf. the heat sink thermal resistance should be 150 − 25 − 50 Rθ.on + Pd. 2) Heat Sink for the Diode: For the 30CPQ45 Schottky Diode.5 = 17.822 × 0. (30) 3) Power Loss of Inductors: The inductor loss includes the winding and core loss.116 W. junction-to-case thermal resistance Rθ.winding + PLf.

we can set up a state-space model for the buck converter: Lo Lo di dt = q (t)v1 − vo (t) dvo o ( t) . under load variations all poles are located on the left-hand rise (LHS) of the complex plane. the three poles are plotted in Fig. Results 1) Whole System Structure: The block diagram of the buck converter with the voltage-mode PI controller is given in Fig. marked in black.5. and the left-hand o side of (47) is zero. (53) −1 −2 −3000 −2500 −2000 −1500 −1000 −500 real Fig. 13.d=D= V V1 = 27 . Substitute (53) into (49) we get the transfer function of the close-loop system: G(s) = sD s3 L o Co V. The block diagram includes the following blocks • H1 (s). Now assume that the system is perturbed ˜= D + d ˆ. 4. C. we obtained the linearized model: dˆ iLo 1 ˆ− v ˆ1 + V1 d ˆo dt = Lo D v (48) dv ˆo v ˆ 1 o ˆ dt = Co iLo − Ro . since the real part of its poles are all negative for any Ro ∈ [1. we set vref = 0.5 ∼ 4. and the close-loop system is stable and its step response y (t) approaches 0 as t → ∞. (54) + s (1 − V1 a1 ) − V1 a2 From (54) we know that due to the integrator in the controller. A simple MATLAB experiment shows that if we select a1 = 0. ˆ(s) • H2 (s). hilighted in red.5.5]Ω. 4. If the system is stable. offset to the control signal d ˜ = q ( t) . The voltage-mode controlled system is stable. 13 as the load resistor Ro changes from 1.5Ω. State-Space Model From Fig. the signal path from v ˆ1 (s) to v ˆo (s). iLo = ILo = R . To see this.008 and a2 = −20. ˆ1 . d away from the equilibrium point: v1 = V1 + v ˆ v o = Vo + v ˆo and iLo = ILo + iL . Power efﬁciency of the buck converter under different duty ratio and output power values.In Laplace domain we have s 2 Lo C o + s Lo ˆ(s). where d At the nominal point. A. By linearizing (47).5]Ω. p2 . v1 = V1 = Vo ˜ 15 o 27V . the PI controller block which transfers the output ˆ(s).5Ω. Since we want v ˆo (s) = 0. the signal path from the controlled duty ratio d to v ˆo (s) marked in blue. 12.5Ω to 4. Co dt = iLo (t) − vR o + Lo s2 R o . its poles p1 . ˆ(s) Lo d s 2 Lo C o + s R + 1 o (49) from which we get two transfer functions H1 ( s ) = and H2 ( s ) = Fig. 1. p3 ∈ C− . the system is stable under load variation. F EEDBACK C ONTROL This section designs a voltage-model feedback controller for the buck converter such that: 1) The averaged output voltage can stay at 15 V when there is a step change in the input voltage. thus the close-loop system is guaranteed stable. which leads to 1 − V1 a1 > 0 and V1 a2 < 0. (52) s such that ˆ(s) = K (s) (ˆ d vo (s) − vref (s)) . we have vo = Vo = 15 V. • K (s). . 2 x 10 4 (50) (51) B. Clearly. the step response y (t) is zero when t → ∞ since G(0) = 0. we should select a1 and a2 such that a1 is small and a2 < 0 to make the system stable for Ro ∈ [1. PI Controller Design p 1 2 1 p imag p3 0 We need to design a PI controller (of course we can also use a PID controller) a2 K (s ) = a 1 + . 2) The closed-loop system is stable when the load resistor varies in the range of 1. +1 v ˆo (s) = Dv ˆ1 (s) + V1 d Ro v ˆo (s) D = Lo v ˆ1 (s) s 2 Lo C o + s R +1 o V1 v ˆo (s) = . 14. (55) (46) Averaging the above state-space model we have Lo ˜ Lo di dt = dv1 − vo dvo vo Co dt = iLo − R o (47) Therefore.

Clearly.0934 W. which decays to 0 within 0. TABLE IV S IMULATION RESULTS OF THE PROPOSED DESIGN .5 ML24 Remarks worst-case loss 5. wire resistance 2. max. The simulation results are summarized in Table IV.59% $\hat v_o$ time (s) Fig.33%) 9 mV 31 mA > 94. 16) to redo the simulation.68 mm). temperature rise 3.116 W. the deviation of the averaged output from the desired value 15 V. 14. and all design speciﬁcations are satisﬁed.0◦ C/W Rθ = 16. 15. Time-domain response when the input steps from 27 V to 32 V.7◦ C/W Fig. turn # 6. MATLAB Simulink model of the whole buck converter with voltagemode PI controller.161mΩ. INCLUDING PARASITIC EFFECTS . S UMMARY A.03 0. Since the break-down drain-to-source voltage of the selected IRFZ48N MOSFET is 55 V. loss 0. Devices Switch Diode Rd (resistor in the damping leg of the EMI ﬁlter) Cf (capacitor for the input ﬁlter) Cd (capacitor for the damping leg in EMI ﬁlter) Co (capacitor at output stage) Lf (inductor for EMI ﬁlter) Lo (inductor at output stage) Heat sink for MOSFET switch Heat sink for diode Component Selection IRFZ48N MOSFET 30CPQ45 Schottky Diode 0. this circuit can survive under 44-V input transient limit.1 Now we include device parasitics (as shown in Fig. break-down VDS 55V worst-case loss 2.48◦ C AL = 315 nH. size-14 copper wire (diameter: 1. RM10/I core 31.01 second. including their parasitic effects.49mΩ.3 mF HD Series 100µF 9µH.35◦ C Rθ = 11. turn # 10. 2) Simulation Result: We use a step input of magnitude 5V to perform the time-domain simulation.09 0. . reverse voltage 45 V parasitic resistance 0.01 second. loss 0. 16. under the input step the offset of the averaged output decays to zero (and vo returns to the desired value Vo = 15V) within 0. max.TABLE III D EVICE S UMMARY.75 V (+18.074Ω AL = 250 nH.6239 W. The y-axis data means v ˆo (t). Clearly shown in Fig. Performance Summary 6 5 4 3 2 1 0 −1 0 0. VI.0025Ω. temperature rise 14.52 W.05 0. B.04 0. The ﬁnalized circuit that includes parasitic effects. RM12/I core ML73/1. Fig. Device Selection Summary The electrical and thermal devices.06 0.08 0. the results are very close the our previous design. 15.5µH. max. which means a step of the DC input from the nominal value 27 V to the maximum value 32V.83 mm).02 0. parasitic inductance 11 nH parasitic resistance 0.01 0. and the the maximum reverse voltage of the selected 30CPQ45 Schottky Diode is 45 V.0µF U767D 3.07 0. size-13 copper wire (diameter: 1. Switching frequency Input voltage range Tolerate 44-V input transient limit? Output power range Output voltage (static) Maximum output voltage (transient) Maximum output voltage ripple (p-p value) Maximum input current ripple (p-p value) Minimum efﬁciency 200 KHz 22 ∼ 32 V yes 50 ∼ 150 V 15 V±1.33% 17. wire resistance 6.011Ω parasitic resistance 0.4Ω CSZ 20. power loss and temperature rise are summarized in Table III.

- Buck ConverterUploaded byRav Venkatesh
- buck converterUploaded bykashiub
- Buck converterUploaded byRajendra Ghivari
- Buck converterUploaded byAndres Lopez
- Simulation of Buck Boost ConverterUploaded byganeshkurapati_15512
- BUCK Converter Desig KitUploaded byrdsraj
- Buck convertersUploaded bymuddassir07
- Boost ConverterUploaded byspecializedfirm
- Buck ConverterUploaded byM Zeeshan Wazir
- Buck Converter BasicsUploaded byNish Shah
- Buck ConverterUploaded bymayank.rkl
- Buck ConverterUploaded bynehabatra14
- Buck ConverterUploaded byRamil L. Abuan
- Buck Converter Design ExampleUploaded bynsalazar1389
- Buck ConverterUploaded bymounicapaluru_351524
- LED Lighting Management SolutionsUploaded bygertibaj
- Non-Isolation Soft-Switching Buck Conve r t e r ForUploaded byNaresh Chinna
- ZXLD1362Uploaded bychkmgdew
- (Fix)Gaincontrol 2011Uploaded byfarras iqtisam
- datasheet lnk3204Uploaded byAlexandreSilva
- 5. Questions & Answers on Application of DiodesUploaded bykibrom atsbha
- DC to DC converterUploaded byibenard
- Data SheetUploaded byflaviosanchesz
- chap02Uploaded byniku_
- AEI305Uploaded byapi-26787131
- Wireless Remote ControlUploaded byBoy Liverpool
- project work-converted.pptxUploaded bySidhant Kaushik
- 369-4258-1-PBUploaded byRavi Rathod

- Unbalance in Power Systems.pdfUploaded byThanasis Stam
- Fundamental of Electric Traction Drives.pdfUploaded byThanasis Stam
- A European Benchmarking of Voltage Quality RegulationUploaded byThanasis Stam
- VSC-HVDC Control Under Unbalanced Supply ConditionsUploaded byThanasis Stam
- Study on High Voltage Capacitor Unbalance Protection in HVDC ProjectsUploaded byThanasis Stam
- classification methodologies of power quality.pdfUploaded byThanasis Stam
- VOLTAGE UNBALANCE.pdfUploaded byThanasis Stam
- Battery Energy Storage for Intermittent Renewable Electricity ProductionUploaded byThanasis Stam
- A European Benchmarking of voltage quality regulation.pdfUploaded byThanasis Stam
- Dynamic Study Model for the Interconnected Power Systems of Europe in Different Simulation ToolsUploaded byThanasis Stam
- Modeling and Simulation of the Propagation of Harmonics in Electric Power Networks Part IIUploaded byThanasis Stam
- 00551343Uploaded byThanasis Stam
- Effects of Balanced and Unbalanced Distribution System Modeling on Power Flow AnalysisUploaded byThanasis Stam
- VOLTAGE UNBALANCE.pdfUploaded byThanasis Stam
- An Analytical Approach for Stohastic Assessment of Balanced and Unbalanced Voltage Sags in Large SystemsUploaded byThanasis Stam
- Cigre_power quality indices and objectives.pdfUploaded byThanasis Stam
- Application Guide PSCAD 2007Uploaded byThanasis Stam
- AT1Uploaded byThanasis Stam
- railway electrification 25kV Ac design on British Railway.pdfUploaded byThanasis Stam
- FACTS for AVAILABILITY and Power Quality Improvement in High Speed Railway ElectrificationUploaded byThanasis Stam
- contributions towards the development of iec61000-3-13 on voltage unbalance.pdfUploaded byThanasis Stam
- Unbalance in Power SystemsUploaded byThanasis Stam
- Short-circuit analysis of the onsite electric power system at Ringhals unit 4.pdfUploaded byThanasis Stam
- Fundamental of Electric Traction Drives.pdfUploaded byThanasis Stam
- Fault Impedance Calculation as Autotransformer Tab change in traction power supply system.pdfUploaded byThanasis Stam
- 43X II Service ManualUploaded byThanasis Stam
- classification methodologies of power quality.pdfUploaded byThanasis Stam
- Voltage Unbalance Emission Limits for Installations – General Guidelines and System Specific ConsiderationsUploaded byThanasis Stam
- TRACTION POWER SUPPLY SYSTEM FOR California high speed train project.pdfUploaded byThanasis Stam
- LOAD FLOW METHOD FOR UNBALANCED SYSTEMS.pdfUploaded byThanasis Stam