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# Design of a 22V∼32V-to-15V DC/DC Power Converter under Input and Load Variations

Zheng Zhang Department of Electrical Engineering and Computer Science, MIT Email: z zhang@mit.edu Submitted on May 16, 2012

Abstract—This report presents the design procedure of a buck converter, which converts a 22V∼32V DC input voltage to a 15V DC output, under a resistive load variation from 1.5Ω to 4.5Ω. Detailed analysis and simulation results, as well as electrical and thermal device speciﬁcations are provided. A voltage-mode PI controller is designed to stabilize the averaged system under input and load variations. The worst-case efﬁciency of this buck converter is above 94.59%.

S Is V1

q(t)

+VD D -

Lo ILo +Vo Ro Co -

ID

I. D ESIGN R EQUIREMENTS The design requirements of the electrical parameters for the buck converter are listed in Table I.
TABLE I D ESIGN R EQUIREMENTS . Input voltage range Input voltage transient limit Output power range Output voltage (static) Output voltage (transient) Output voltage ripple (p-p value) Input current ripple (p-p value, ideal source) Efﬁciency 22 ∼ 32 V 44 V for up to 1 ms 50 ∼ 150 V 15 V±3% 15 V±20% ≤ 100 mV ≤ 100 mA ≥ 88% Fig. 1. Top-level schematic of a buck converter.

Besides, it is required that the junction temperature of the power devices should remain sufﬁciently (at least 25◦ C) below the allowable maximum junction temperature, while the ambient temperature is in the range of −20◦ C∼ +50◦ C. It is also required that the temperature rise of inductor should be below 50◦ C. II. T OP -L EVEL D ESIGN V IEW As shown in Fig. 1, assume that the duty ratio of the switch is d and the input DC voltage is V1 , then the output DC voltage can be decided as Vo = dV1 . (1) And the power at the output stage is Po = Vo2 /Ro . (2)

1) The switching frequency shall be high enough, since as fsw gets higher the ripples in iLo and vo become smaller; 2) The switching frequency cannot be arbitrarily high. As fsw increases, the switching losses in the power devices will increases. Meanwhile, the core power loss and loss due to the skin effects also become more signiﬁcant as fsw increases. The following main problems need to be addressed in our design: 1) The output stage should be designed such that the output voltage has small ripples. 2) An input EMI ﬁlter should be added between the switch and the input source, to ensure that the current ﬂowing through the input source has small ripples. 3) The circuit should be designed such that this DC buck converter can work well under load variations from 1.5Ω to 4.5Ω (or vise versa). 4) The power and passive devices and thermal devices should be carefully selected such that designed circuit works well under parasitic and thermal effects. 5) As the input voltage change in the range of 22 ∼ 32 V, the duty ratio d should be tuned according to the input level to ensure Vo stay at 15 V. This requires us to design a feedback controller to form a stable close-loop system such that the output stays at the nominal value. III. C IRCUIT S CHEMATIC D ESIGN A. Output Stage The output stage is designed under two constraints: 1) The inductor Lo should be large enough to make the current rippels of iLo small enough;

Since Vo = 15 V, and Po = 50 ∼ 150 W, the load resistance Ro can vary in the range of 1.5 ∼ 4.5Ω. And accordingly, the averaged current through the inductor shall vary in the range of 10 3 ∼ 10 A. In our design, we see V1 = 27 V and d = 5 9 as the nominal design. The switching frequency is set as fsw = 200 KHz based on the following tradeoffs:

we can model the output stage by a current source and get an equivalent circuit for analyzing the input current of this converter. as shown in the left part of Fig.4A.ac is odd in time and its n-th Fourier coefﬁcient can be easily obtained as 2IL .5I Lo. we can add a damped LC ﬁlter. B. To ensure the peak-to-peak value of the inductor current below a speciﬁed bound δ1 . and thus g (s ) ≈ 1 ix ( s ) = L 2 is. the output voltage ripple (peak-to-peak value) can be computed as Vo.p-p Fig. we can select δ2 = 0.ac = (9) 2) The capacitor Co should be large enough to make the voltage ripple of vo small enough. (10) nπ We only consider the fundamental harmonic. Lo Lo V1 (3) which approaches the maximum (worst-case) value when V1 = 32V.5. (11) where g (s) is the transfer function from switch current to input current. Since the switch current is (t) ≈ ILo when the switch turns on and is (t) = 0 when the switch turns off. otherwise. We notice that when s = 0. 3. In Laplace domain n Is. and this ac current all ﬂows through Co .5 µF. since in this case the ac component of is. EMI filter Lf Rd V1 Cf Cd Fig. the waveform of which is plotted in the right part of Fig. 3. For simplicity. The buck converter with an EMI input ﬁlter. we perform the ac analysis using V1 =30 and d = 0.ac i s. since the higherorder harmonics in the input current are negligible due to the low-pass property of the damped EMI ﬁlter. (5) The ac component of iLo is shown in Fig.ac dt = t1 IL.ac (s). The input current of this circuit model is in fact the ac component of the switch current. 8δ2 (7) in the frequency band of interest.1 V and lead to Co ≥ 3. Therefore. 8Co (6) Given an upper bound δ2 for Vo.p−p = 1 Co t2 ix (s) = g (s)is. 2. we need to reduce its ac component ix . we remarkably increase Co and slightly increase Lo which leads to smaller inductor current ripples. δ1 δ1 (4) Here we choose δ1 = 1. 2 Iin Po (13) .ac dT T t -0. as shown in Fig.p−p T .ac dT t1 t2 T 2T t Lf ix Cf Rd Cd -dILo (1-d)ILo i s.p−p . 20lg|g (s)| = 0.46 µH. Input-Stage EMI Filter To reduce the current ripples of the input stage.p−p T . Right: waveform of the ac component of the switch current. the peak-to-peak current of Lo can be computed as ILo.5I Lo. and |g (s)| decreases by 40 dB/Dec when ω > √1 . much smaller output voltage ripples and much smaller transient peak of vo . Left: the ac signal model to analyze input current ripple. the maximum transient magnitude of Vo would decrease. AC component of the current through inductor Lo . we select Co = 100 µF. 4. Lo = 31.5 µH. the capacitance should be selected according to Co ≥ IL. When the switch turns on VD = V1 and vLo = V1 − Vo = V1 − 15. S Is q(t) +VD D Lo ILo +Vo Ro Co - ID Our simulation results show that when we increases Co and decreases Lo . Based on the data sheet information.. We can select a large damping capacitor Cd such that 2πfsw Cd 1/Rd .8438 32 T = µH. 4. 2. the inductor value should be Lo ≥ 15 − 225 39. (8) There is a “negative resistance” under constant power transfer (seen from the switch). Denote the voltage across the inductor Lo as vLo .0. Based on this observation.p-p iLo. Assume that capacitor Co is large enough. which is calculated as rl = − Po −V12 = . then we have Lo ≥ 28. 4.ac (s) +1 s Lf Cf + s Rf d (12) iL. the diode turns on and vLo = −15 V. To reduce the ripple of the input current.p−p = 1 15 1 (V1 − 15) dT = (V1 − 15) T. C f Lf Since it is required that Vo.p−p ≤ 1 mV. Fig.

Clearly.0934 W. which decays to 0 within 0. TABLE IV S IMULATION RESULTS OF THE PROPOSED DESIGN .5 ML24 Remarks worst-case loss 5. wire resistance 2. max. The simulation results are summarized in Table IV.59% $\hat v_o$ time (s) Fig.33%) 9 mV 31 mA > 94. 16) to redo the simulation.68 mm). temperature rise 3.116 W. the deviation of the averaged output from the desired value 15 V. 14. and all design speciﬁcations are satisﬁed.0◦ C/W Rθ = 16. 15. Time-domain response when the input steps from 27 V to 32 V.7◦ C/W Fig. turn # 6. MATLAB Simulink model of the whole buck converter with voltagemode PI controller.161mΩ. INCLUDING PARASITIC EFFECTS . S UMMARY A.03 0. Since the break-down drain-to-source voltage of the selected IRFZ48N MOSFET is 55 V. loss 0. Devices Switch Diode Rd (resistor in the damping leg of the EMI ﬁlter) Cf (capacitor for the input ﬁlter) Cd (capacitor for the damping leg in EMI ﬁlter) Co (capacitor at output stage) Lf (inductor for EMI ﬁlter) Lo (inductor at output stage) Heat sink for MOSFET switch Heat sink for diode Component Selection IRFZ48N MOSFET 30CPQ45 Schottky Diode 0. this circuit can survive under 44-V input transient limit.1 Now we include device parasitics (as shown in Fig. break-down VDS 55V worst-case loss 2.48◦ C AL = 315 nH. size-14 copper wire (diameter: 1. RM10/I core 31.01 second. including their parasitic effects.49mΩ.3 mF HD Series 100µF 9µH.35◦ C Rθ = 11. turn # 10. 2) Simulation Result: We use a step input of magnitude 5V to perform the time-domain simulation.09 0. . reverse voltage 45 V parasitic resistance 0.01 second. loss 0. 16. under the input step the offset of the averaged output decays to zero (and vo returns to the desired value Vo = 15V) within 0. max.TABLE III D EVICE S UMMARY.75 V (+18.074Ω AL = 250 nH.6239 W. The y-axis data means v ˆo (t). Clearly shown in Fig. Performance Summary 6 5 4 3 2 1 0 −1 0 0. VI.0025Ω. temperature rise 14.52 W.05 0. B.04 0. The ﬁnalized circuit that includes parasitic effects. RM12/I core ML73/1. Fig. Device Selection Summary The electrical and thermal devices.06 0.08 0. the results are very close the our previous design. 15.5µH. max. which means a step of the DC input from the nominal value 27 V to the maximum value 32V.83 mm).02 0. parasitic inductance 11 nH parasitic resistance 0.01 0. and the the maximum reverse voltage of the selected 30CPQ45 Schottky Diode is 45 V.0µF U767D 3.07 0. size-13 copper wire (diameter: 1. Switching frequency Input voltage range Tolerate 44-V input transient limit? Output power range Output voltage (static) Maximum output voltage (transient) Maximum output voltage ripple (p-p value) Maximum input current ripple (p-p value) Minimum efﬁciency 200 KHz 22 ∼ 32 V yes 50 ∼ 150 V 15 V±1.33% 17. wire resistance 6.011Ω parasitic resistance 0.4Ω CSZ 20. power loss and temperature rise are summarized in Table III.