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Analog & Mixed Signal Labs

Revision 1.0 IC613 Assura 32 Incisive Unified Simulator 82

Developed By University Support Team Cadence Desi n Systems! Ban alore


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'&(ective
Objective of this lab is to learn the Virtuoso tool as well learn the flow of the Full Custom IC design c cle. !ou will finish the lab b running "RC# $V% and &arasitic '(traction on the various designs. In the )rocess ou will create various com)onents li*e inverter# differential am)lifier# o)erational am)lifier# R+2R based ",C and -i(ed signal design of %,R based ,"C# but we won.t be designing ever cell# as the time will not be sufficient# instead we will be using some read made cells in the )rocess. !ou will start the lab b creating a librar called /myDesi n%i&0 and ou will attach the librar to a technolog librar called / pd)18*0. ,ttaching a technolog librar will ensure that ou can do front to bac* design. !ou will create a new cell called /Inverter0 with schematic view and hence build the inverter schematic b instantiating various com)onents. Once inverter schematic is done# s mbol for /Inverter0 is generated. 1ow ou will create a new cell view called /Inverter+Test0# where ou will instantiate /Inverter0 s mbol. 2his circuit is verified b doing various simulations using s)ectre. In the )rocess# ou will learn to use s)ectre# waveform window o)tions# waveform calculator# etc... !ou will learn the $a out 'ditor basics b concentrating on designing an /Inverter0 through automatic la out generation. 2hen ou will go ahead with com)leting the other la outs. ,fter that# ou will run "RC# $V% chec*s on the la out# '(tract )arasitics and bac*+annotate them to the simulation environment. ,fter com)leting the )arasitic bac*+ annotation flow# design is read for generating 3"%II.

Table of Contents
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General Notes
2here are a number of things to consider before beginning these lab e(ercises. &lease read through this section com)letel # and )erform an needed ste)s in order to ensure a successful wor*sho). 2hese labs were designed for use with Incisive 4nified %imulator52# IC617 and ,ssura72. 8efore running an of these labs# ensure that ou.ve set u) I4%52# IC617# --%I-91 and ,ssura72 correctl :

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%> %> %> %> setenv setenv setenv setenv CDSHOME <IC613-installation-home> MMSIMHOME <MMSIM71-installation-home> PVHOME <Assura !-installation-home> AMSHOME <IUS82-installation-home>

!ou will also need to ensure that the I4%52 is setu) correctl for lab <. 2o setu) the lab environment# )lease )erform the following ste)s: 1. 'nsure the software mentioned above is correctl setu). 2. %ource the C+%hell related commands file i.e. =cshrc file>. 2hese labs were designed to be run using Cadence Virtuoso tool and ,ssura tool.

Lab Getting Started


1. $og in to our wor*station using the username and )assword. 2he home director has a cs,rc file with )aths to the Cadence installation. 2. In a terminal window# t )e cs, at the command )rom)t to invo*e the C shell. -cs, -source cs,rc 7. 2o verif that the )ath to the software is )ro)erl set in the cs,rc file# t )e the below command in the terminal window and enter: >.,ic, virtuoso It gives the com)lete )ath of IC617 tool Installation. ?.,ic, spectre It gives the com)lete )ath of --%I-91 tool Installation. ?.,ic, assura It gives the com)lete )ath of ,ssura72 tool Installation. >.,ic, ncsim It gives the com)lete )ath of I4%52 tool Installation. Starting the Cadence Software 4se the installed database to do our wor* and the ste)s are as follows: ;

1. Change to the course director b entering this command: > cd /0Data&ase0cadence+analo +la&s+613 !ou will start the Cadence "esign Framewor* II environment from this director because it contains cds.lib# which is the local initiali@ation file. 2he librar search )aths are defined in this file. 2he Cadence+Analo +la&s+613 director contains %olutions folder and also Aor* folder. Inside Aor* folder ou can create new cell 0 modifications of the cell locall without affecting our %ource cell )resent inside %olutions director . $ab director details: 1 0Solutions 1 0li&s1cd& 1 0models 1 0stream 1 0pv 1 0tec,files 1 0di +source 1 0cds1li& 1 0,dl1var 1 0docs Contains a local co) of all the lab e()eriments including test circuit for simulation. Contains a technolog librar for the design =g)d*150nm>. Contains s)ectre models of com)onents for simulation in g)d*150nm technolog . Contains la er ma) file for 3"%II format Containing the ,ssura and "iva verification files Contains ,%CII versions of the oa22 techfiles Contains verilog codes for %,R register and cloc* File containing )ointer to the Cadence O,22 initiali@ation file1 File defines the wor* librar for ,-% simulation Reference manual and user manual for g)d*150nm technolog .

2. In the same terminal window# enter: > virtuoso " 2he virtuoso or Command Inter)reter Aindow =CIA> a))ears at the bottom of the screen.

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7. If the /Ahat.s 1ew ...0 window a))ears# close it with the 2ile3 Close command.

;. Bee) o)ened CIA window for the labs.

4nd of 5eneral 6otes

Lab 1: AN INV !T !

Sche"atic Ca#t$re

Sche"atic ntr%
&b'ecti(e: To create a librar% and b$ild a sche"atic of an In(erter 8elow ste)s e()lain the creation of new librar /myDesi n%i&0 and we will use the same throughout this course for building various cells that we going to create in the ne(t labs. '(ecute Tools 7 %i&rary #ana er in the CIA or Virtuoso window to o)en $ibrar -anager. 9 Analo " #i$ed Si nal %a&s

Creatin a 6e. li&rary


1. In the $ibrar -anager# e(ecute 2ile 8 6e. 7 %i&rary. 2he new librar form a))ears. 2. In the /1ew $ibrar 0 form# t )e /myDesi n%i&0 in the 1ame section.

;. In the field of "irector section# verif that the )ath to the librar is set to "#Data$ase#%a&en%e'analo('la$s')1 and clic* '9. 6ote: , technolog file is not reCuired if ou are not interested to do the la outs for the design <. In the ne(t /Tec,nolo y 2ile for 6e. li&rary0 form# select o)tion Attac, to an e$istin tec,file and clic* '9.

6. In the /Attac, Desi n %i&rary to Tec,nolo y 2ile0 form# select pd)18* from the c clic field and clic* '9.

9. ,fter creating a new librar

ou can verif it from the librar manager.

5. If ou right clic* on the /myDesi n%i&0 and select )ro)erties# ou will find that pd)18* librar is attached as techlib to /myDesi n%i&0.

Creatin a Sc,ematic Cellvie.


In this section we will learn how to o)en new schematic window in the new /myDesi n%i&0 librar and build the inverter schematic as shown in the figure at the start of this lab. 1. In the CIA or $ibrar manager# e(ecute 2ile 7 6e. 7 Cellvie.. 2. %et u) the 1ew file form as follows:

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"o not edit the %i&rary pat, file and the one above might be different from the )ath shown in our form. 7. Clic* '9 when done the above settings. , blan* schematic window for the Inverter design a))ears.

Addin Components to sc,ematic


1. In the Inverter schematic window# clic* the Instance fi(ed menu icon to dis)la the ,dd Instance form.
Ti#: !ou

can also e(ecute Create 3 Instance or )ress i.

2. Clic* on the Bro.se button. 2his o)ens u) a $ibrar browser from which ou can select com)onents and the sym&ol view . !ou will u)date the $ibrar 1ame# Cell 1ame# and the )ro)ert values given in the table on the ne(t )age as ou )lace each com)onent. 7. ,fter ou com)lete the ,dd Instance form# move our cursor to the schematic window and clic* left to )lace a com)onent. 2his is a table of com)onents for building the Inverter schematic. %i&rary name g)d*150 g)d*150 Cell 6ame )mos nmos ;roperties0Comments For -0: -odel name E )mos1# <= .p# $E150n For -1: -odel name E nmos1# AE 2u# $E150n

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If ou )lace a com)onent with the wrong )arameter values# use the 4dit3 ;roperties3 '&(ects command to change the )arameters. 4se the 4dit3 #ove command if ou )lace com)onents in the wrong location.

!ou can rotate com)onents at the time ou )lace them# or use the 4dit3 >otate command after the are )laced. ;. ,fter entering com)onents# clic* Cancel in the ,dd Instance form or )ress 4sc with our cursor in the schematic window.

Addin pins to Sc,ematic


1. Clic* the ;in fi(ed menu icon in the schematic window. !ou can also e(ecute Create 3 ;in or )ress p. 2he ,dd )in form a))ears. 2. 2 )e the following in the ,dd )in form in the e(act order leaving s)ace between the )in names. ;in 6ames vin vout Direction In)ut Out)ut

-a*e sure that the direction field is set to input0output0input'utput when )lacing the input0output0inout )ins res)ectivel and the 4sage field is set to sc,ematic. 7. %elect Cancel from the ,dd F )in form after )lacing the )ins. In the schematic window# e(ecute <indo.3 2it or )ress the f bind*e . 11 Analo " #i$ed Si nal %a&s

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Addin <ires to a Sc,ematic


,dd wires to connect com)onents and )ins in the design. 1. Clic* the <ire ?narro.@ icon in the schematic window. !ou can also )ress the w *e # or e(ecute Create 3 <ire ?narro.@1 2. In the schematic window# clic* on a )in of one of our com)onents as the first )oint for our wiring. , diamond sha)e a))ears over the starting )oint of this wire. 7. Follow the )rom)ts at the bottom of the design window and clic* left on the destination )oint for our wire. , wire is routed between the source and destination )oints. ;. Com)lete the wiring as shown in figure and when done wiring )ress 4SC *e in the schematic window to cancel wiring.

Savin t,e Desi n


1. Clic* the Check and Save icon in the schematic editor window.

2. Observe the CIA out)ut area for an errors.

S%"bol Creation
&b'ecti(e: To create a s%"bol for the In(erter In this section# ou will create a s mbol for our inverter design so ou can )lace it in a test circuit for simulation. , s mbol view is e(tremel im)ortant ste) in the design )rocess. 2he s mbol view must e(ist for the 12

schematic to be used in a hierarch . In addition# the s mbol has attached )ro)erties =cds&aram> that facilitate the simulation and the design of the circuit. 1. In the Inverter schematic window# e(ecute Create 3 Cellvie.3 2rom Cellvie.. 2he Cellvie. 2rom Cellvie. form a))ears. Aith the 'dit O)tions function active# ou can control the a))earance of the s mbol to generate. 2. Verif that the 2rom Aie. 6ame field is set to sc,ematic# and the To Aie. 6ame field is set to sym&ol# with the Tool0Data Type set as Sc,ematicSym&ol.

7. Clic* '9 in the Cellvie. 2rom Cellvie. form. 2he % mbol 3eneration Form a))ears.

;. -odif the ;in Specifications as follows:

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<. Clic* '9 in the % mbol 3eneration O)tions form. 6. , new window dis)la s an automaticall created Inverter s mbol as shown here.

4ditin a Sym&ol
In this section we will modif the inverter s mbol to loo* li*e a Inverter gate s mbol. 1;

1. -ove the cursor over the automaticall generated s mbol# until the green rectangle is highlighted# clic* left to select it. 2. Clic* Delete icon in the s mbol window# similarl select the red rectangle and delete that. 7. '(ecute Create 7 S,ape 7 poly on# and draw a sha)e similar to triangle. ;. ,fter creating the triangle )ress ESC *e . <. '(ecute Create 7 S,ape 7 Circle to ma*e a circle at the end of triangle. 6. !ou can move the )in names according to the location. 9. '(ecute Create 3 Selection Bo$. In the ,dd %election 8o( form# clic* Automatic. , new red selection bo( is automaticall added. 5. ,fter creating s mbol# clic* on the save icon in the s mbol editor window to save the s mbol. In the s mbol editor# e(ecute 2ile 3 Close to close the s mbol view window.

)$ilding the In(erter*Test +esign


&b'ecti(e: To b$ild an In(erter Test circ$it $sing %o$r In(erter

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16 Creating the In(erter*Test Cell(iew !ou will create the InverterG2est cellview that will contain an instance of the Inverter cellview. In the ne(t section# ou will run simulation on this design 1. In the CIA or $ibrar -anager# e(ecute 2ile3 6e.3 Cellvie.. 2. %et u) the 1ew File form as follows:

7. Clic* '9 when done. , blan* schematic window for the Inverter+Test design a))ears. )$ilding the In(erter*Test Circ$it 1. 4sing the com)onent list and &ro)ertiesHComments in this table# build the Inverter+Test schematic. %i&rary name
myDesignLib analogLib analogLib

Cellvie. name
Inverter vpulse vd!, gnd

;roperties0Comments
Symbol v1=0, v2=1.8,td=0 tr=tf=1ns, ton=10n, =20n vd!=1.8

Note: Remember

to set the values for ADD and ASS. Otherwise# our circuit will have no

)ower.

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2. ,dd the above com)onents using Create 3 Instance or b )ressing I. 7. Clic* the <ire ?narro.@ icon and wire our schematic.
Ti#: !ou

can also )ress the . *e # or e(ecute Create3 <ire ?narro.@. ;. Clic* Create 3 <ire 6ame or )ress % to name the in)ut ?Ain@ and out)ut ?Aout@ wires as in the below schematic. ;. Clic* on the Check and Save icon to save the design. <. 2he schematic should loo* li*e this.

6. $eave our Inverter+Test schematic window o)en for the ne(t section.

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Analog Si"$lation with S#ectre


&b'ecti(e: To set $# and r$n si"$lations on the In(erter*Test design In this section# we will run the simulation for Inverter and )lot the transient# "C characteristics and we will do &arametric ,nal sis after the initial simulation.

Startin t,e Simulation 4nvironment


%tart the %imulation 'nvironment to run a simulation. 1. In the Inverter+Test schematic window# e(ecute %aunc, 7 AD4 % 2he Airtuoso Analo Desi n 4nvironment ?AD4@ simulation window a))ears.

C,oosin a Simulator
%et the environment to use the SpectreB tool# a high s)eed# highl accurate analog simulator. 4se this simulator with the Inverter_Test design# which is made+u) of analog com)onents. 1. In the simulation window =,"'># e(ecute Setup3 Simulator0Directory0Cost. 2. In the Choosing %imulator form# set the %imulator field to spectre =1ot s)ectre%> and clic* '9.

Settin t,e #odel %i&raries


2he -odel $ibrar file contains the model files that describe the nmos and )mos devices during simulation. 1. In the simulation window =,"'># '(ecute Setup 8 #odel %i&raries1 2he -odel $ibrar %etu) form a))ears. Clic* the &ro.se button to add pd)1scs if not added b default as shown in the #odel %i&rary Setup form. Remember to select the section t )e as stat in front of the g)d*.scs file. !our -odel $ibrar %etu) window should now loo*s li*e the below figure. 15

2o view the model file# highlight the e()ression in the -odel $ibrar File field and Clic* 4dit 2ile.

2. 2o com)lete the -odel $ibrar %etu)# move the cursor and clic* '9. 2he -odel $ibrar %etu) allows ou to include multi)le model files. It also allows ou to use the 'dit button to view the model file.

C,oosin Analyses
2his section demonstrates how to view and select the different t )es of anal ses to com)lete the circuit when running the simulation. 1. In the %imulation window =,"'># clic* the C,oose 8 Analyses icon. !ou can also e(ecute Analyses 8 C,oose1 2he Choosing ,nal sis form a))ears. 2his is a d namic form# the bottom of the form changes based on the selection above. 2. 2o setu) for transient anal sis a. In the ,nal sis section select tran b. %et the sto) time as 2**n c. Clic* at the moderate or 4na&led button at the bottom# and then clic* Apply.

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7. 2o set u) for "C ,nal ses: a. In the ,nal ses section# select dc. b. In the "C ,nal ses section# turn on Save DC 'peratin ;oint1 c. 2urn on the Component ;arameter. d. "ouble clic* the Select Component# Ahich ta*es ou to the schematic window. e. %elect in)ut signal vpulse source in the test schematic window. f. %elect DDC Aolta eE in the Select Component ;arameter form and clic* OB. f. In the anal sis form t )e start and stop voltages as * to 118 res)ectivel . g. Chec* the enable button and then clic* Apply.

;. Clic* OK in the Choosing ,nal ses Form.

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Setting +esign Variables


%et the values of an design variables in the circuit before simulating. Otherwise# the simulation will not run. 1. In the %imulation window# clic* the 4dit Aaria&les icon. 2he 'diting "esign Variables form a))ears. 2. Clic* Copy 2rom at the bottom of the form. 2he design is scanned and all variables found in the design are listed. In a few moments# the .p variable a))ears in the 2able of "esign variables section. 7. %et the value of the .p variable: Aith the .p variable highlighted in the 2able of "esign Variables# clic* on the variable name .p and enter the following: Value='()r> 2u

Clic* C,an e and notice the u)date in the 2able of "esign Variables. 7. Clic* '9 or Cancel in the 'diting "esign Variables window.

Selectin 'utputs for ;lottin


1. '(ecute 'utputs 7 To &e plotted 7 Select on Sc,ematic in the simulation window. 2. Follow the )rom)t at the bottom of the schematic window# Clic* on out)ut net Aout# in)ut net Ain of the Inverter. &ress 4SC with the cursor in the schematic after selecting it. "oes the simulation window loo* li*e thisI

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>unnin t,e Simulation


1. '(ecute Simulation 7 6etlist and >un in the simulation window to start the %imulation or the icon# this will create the netlist as well as run the simulation. 2. Ahen simulation finishes# the 2ransient# "C )lots automaticall will be )o))ed u) along with log file.

Savin t,e Simulator State


Ae can save the simulator state# which stores information such as model librar file# out)uts# anal sis# variable etc. 2his information restores the simulation environment without having to t )e in all of setting again. 1. In the %imulation window# e(ecute Session 7 Save State. 2he %aving %tate form a))ears. 2. %et the Save as field to state1+inv and ma*e sure all o)tions are selected under what to save field. 7. Clic* '9 in the saving state form. 2he %imulator state is saved.

%oadin t,e Simulator State


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1. From the ,"' window e(ecute Session 7 %oad State1 2. In the $oading %tate window# set the %tate name to state1+inv as shown

7. Clic* '9 in the $oading %tate window.

,ara"etric Anal%sis
&arametric ,nal sis ields information similar to that )rovided b the %)ectreJ swee) feature# e(ce)t the data is for a full range of swee)s for each )arametric ste). 2he %)ectre swee) feature )rovides swee) data at onl one s)ecified condition. !ou will run a )arametric "C anal sis on the .p variable# of the &-O% device of the Inverter design b swee)ing the value of .p. Run a simulation before starting the )arametric tool. !ou will start b loading the state from the )revious simulation run. Run the simulation and chec* for errors. Ahen the simulation ends# a single waveform in the waveform window dis)la s the "C Res)onse at the Aout node.

Startin t,e ;arametric Analysis Tool


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1. In the %imulation window# e(ecute Tools3;arametric Analysis. 2he &arametric ,nal sis form a))ears. 2. In the &arametric ,nal sis form# e(ecute Setup3;ic) 6ame 2or Aaria&le3S.eep 1. , selection window a))ears with a list of all variables in the design that ou can swee). 2his list includes the variables that a))ear in the "esign Variables section of the %imulation window. 7. In the selection window# double clic* left on .p. 2he Variable 1ame field for %wee) 1 in the &arametric ,nal sis form is set to .p. ;. Change the Range 2 )e and %te) Control fields in the &arametric ,nal sis form as shown below: Range 2 )e %te) Control 2rom0To Auto From 2otal %te)s 1u 1* 2o 1*u

2hese numbers var the value of the .p of the )mos between 1um and 10um at ten evenl s)aced intervals.

<. '(ecute Analysis3Start. 2he &arametric ,nal sis window dis)la s the number of runs remaining in the anal sis and the current value of the swe)t variable=s>. $oo* in the u))er right corner of the window. Once the runs are com)leted the wavescan window comes u) with the )lots for different runs.

2;

6ote: Change the w) value of )mos device bac* to 2u and save the schematic before
)roceeding to the ne(t section of the lab. 2o do this use edit )ro)ert o)tion.

Creating La%o$t View of In(erter


1. From the Inverter schematic window menu e(ecute %aunc, 7 %ayout F%. , Startup 'ption form a))ears. 2. %elect Create New o)tion. 2his gives a 1ew Cell View Form 7. Chec* the Cellname ?Inverter@# Viewname ?layout@1 ;. Clic* '9 from the 1ew Cellview form. $%A and a blan* la out window a))ear along with schematic window.

Addin Components to %ayout


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1. '(ecute Connectivity 7 5enerate 7 All from Source or clic* the icon in the la out editor window# 5enerate %ayout form a))ears. Clic* '9 which im)orts the schematic com)onents in to the $a out window automaticall . 2. Re arrange the com)onents with in &R+8oundar as shown in the ne(t )age. 7. 2o rotate a com)onent# %elect the com)onent and e(ecute 4dit 7;roperties. 1ow select the degree of rotation from the )ro)ert edit form.

;. 2o -ove a com)onent# %elect the com)onent and e(ecute 4dit 8#ove command.

#a)in interconnection
1. '(ecute Connectivity 76ets 7 S,o.0Cide selected Incomplete 6ets or clic* the icon in the $a out -enu. 2. -ove the mouse )ointer over the device and clic* %#B to get the connectivit information# which shows the guide lines =or flight lines> for the inter connections of the com)onents. 7. From the la out window e(ecute Create 7 S,ape 7 ;at,0 Create .ire or Create 7 S,ape 7 >ectan le ?for vdd and gnd bar@ and select the a))ro)riate $a ers from the %S< window and Vias for ma*ing the inter connections Creating Contacts-Vias !ou will use the contacts or vias to ma*e connections between two different la ers. 1. '(ecute Create 3 Aia or select in below table Connection For -etal1+ &ol Connection For -etal1+ &substrate Connection For -etal1+ 1well Connection command to )lace different Contacts# as given Contact Type -etal1+&ol -etal1+&sub -etal1+1well

Savin t,e desi n

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1. %ave our design b selecting 2ile 3 Save or clic* la out should a))ear as below.

to save the la out# and

,h%sical Verification Assura D>C


>unnin a D>C
1. O)en the Inverter la out form the CIA or librar manger if ou have closed that. &ress s,ift 7 f in the la out window to dis)la all the levels. 2. %elect Assura 8 >un D>C from la out window. 2he "RC form a))ears. 2he $ibrar and Cellname are ta*en from the current design window# but rule file ma be missing. %elect the 2echnolog as pd)18*. 2his automaticall loads the rule file. !our "RC form should a))ear li*e this

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7. Clic* '9 to start "RC. ;. , &rogress form will a))ears. !ou can clic* on the watch log file to see the log file. <. Ahen "RC finishes# a dialog bo( a))ears as*ing ou if ou want to view our "RC results# and then clic* Ges to view the results of this run. 6. If there an "RC error e(ists in the design Aie. %ayer <indo. =V$A> and 4rror %ayer <indo. ='$A> a))ears. ,lso the errors highlight in the design itself. 9. Clic* Aie. 7 Summary in the '$A to find the details of errors. 5. !ou can refer to rule file also for more information# correct all the "RC errors and >e 7 run the "RC. D. If there are no errors in the la out then a dialog bo( a))ears with 6o D>C errors found written in it# clic* on close to terminate the "RC run.

ASSU>A %AS
In this section we will )erform the $V% chec* that will com)are the schematic netlist and 25

the la out netlist.

>unnin %AS
1. %elect Assura 7 >un %AS from the la out window. 2he ,ssura Run $V% form a))ears. It will automaticall load both the schematic and la out view of the cell. 2. Change the following in the form and clic* '9.

7. 2he $V% begins and a &rogress form a))ears. ;. If the schematic and la out matches com)letel # ou will get the form dis)la ing Sc,ematic and %ayout #atc,. <. If the schematic and la out do not matches# a form informs that the $V% com)leted successfull and as*s if ou want to see the results of this run. 6. Clic* Ges in the form. $V% debug form a))ears# and ou are directed into $V% debug environment. 9. In the %AS de&u form ou can find the details of mismatches and ou need to correct all those mismatches and >e 7 run the $V% till ou will be able to match the schematic with la out.

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Ass$ra !C.
In this section we will e(tract the RC values from the la out and )erform analog circuit simulation on the designs e(tracted with RCK. 8efore using RCK to e(tract )arasitic devices for simulation# the la out should match with schematic com)letel to ensure that all )arasites will be bac*annoted to the correct schematic nets.

>unnin >CF
1. From the la out window e(ecute Assura 7 >un >CF. 2. Change the following in the ,ssura )arasitic e(traction form. %elect output t )e under Setup tab of the form.

7. In the 4$traction tab of the form# choose '(traction t )e# Ca) Cou)ling -ode and s)ecif the Reference node for e(traction.

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;. In the 2ilterin tab of the form# 4nter ;o.er 6ets as vddH! vssH and 4nter 5round 6ets as ndH

<. Clic* '9 in the ,ssura )arasitic e(traction form when done. 2he RCK )rogress form a))ears# in the )rogress form clic* <atc, lo file to see the out)ut log file. <. Ahen RCK com)letes# a dialog bo( a))ears# informs ou that Assura >CF run Completed successfully1 6. !ou can o)en the av+e$tracted view from the librar manager and view the )arasitic.

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Creating the Config$ration View


In this section we will create a config view and with this config view we will run the simulation with and without )arasitic. 1. In the CIA or $ibrar -anager# e(ecute 2ile 7 6e. 7 Cellvie. 2. In the Create 1ew file form# set the following:

7. Clic* '9 in create 6e. 2ile form. 2he Cierarc,y 4ditor form o)ens and a 6e. Confi uration form o)ens in front of it.

;. Clic* Use template at the bottom of the 6e. Confi uration form and select Spectre in the c clic field and clic* '9. 2he 3lobal 8indings lists are loaded from the tem)late.

72

<. Change the Top Cell View to sc,ematic and remove the default entr from the %i&rary %ist field. 6. Clic* '9 in the 1ew Configuration form.

2he hierarch editor dis)la s the hierarch for this design using table format.

77 Analo " #i$ed Si nal %a&s

7; 9. Clic* the Tree Aie. tab. 2he design hierarch changes to tree format. 2he form should loo* li*e this:

5. Save the current configuration. D. Close the Lierarch 'ditor window. '(ecute 2ile 7 Close <indo..

To run t,e Circuit .it,out ;arasites


1. From the $ibrar -anager o)en Inverter+Test Config view. O)en Configuration or 2o) cellview form a))ears.

2. In the form# turn on the both c clic buttons to Ges and clic* '91 2he InverterG2est schematic and InverterG2est config window a))ears. 1otice the window banner of schematic also states Confi : myDesi n%i& Inverter+Test confi 1 7. '(ecute %aunc, 7 AD4 % from the schematic window. ;. 1ow ou need to follow the same )rocedure for running the simulation. '(ecuting Session7 %oad state, the ,nalog "esign 'nvironment window loads the )revious state. <. Clic* 6etlist and >un icon to start the simulation. 2he simulation ta*es a few seconds and then waveform window a))ears. 7;

6. In the CIA# note the netlisting statistics in the Circuit inventory section. 2his list includes all nets# designed devices# source and loads. 2here are no )arasitic com)onents. ,lso note down the circuit inventor section.

#easurin t,e ;ropa ation Delay


1. In the waveform window e(ecute Tools 7 Calculator1 2he calculator window a))ears.

2. From the functions select delay! this will o)en the dela data )anel. 7. &lace the cursor in the te(t bo( for %ignal1# select the .ave button and select the in)ut waveform from the waveform window. ;. Re)eat the same for %ignal2# and select the out)ut waveform. <. %et the T,res,old value 1 and T,res,old value 2 to 0.D# this directs the calculator to calculate dela at <0M i.e. at 0.D volts. 6. '(ecute '9 and observe the e()ression created in the calculator buffer. 9. Clic* on 4valuate t,e &uffer icon value returned after e(ecution. 5. Close the calculator window. to )erform the calculation# note down the

To run t,e Circuit .it, ;arasites


In this e(ercise# we will change the configuration to direct simulation of the av+e$tracted view which contains the )arasites. 7< Analo " #i$ed Si nal %a&s

76 1. O)en the same Lierarch 'ditor form# which is alread set for InverterG2est config. 2. %elect the Tree Aie. icon: this will show the design hierarch in the tree format. 7. Clic* ri ,t mouse on the Inverter schematic. , )ull down menu a))ears. %elect av+e$tracted view from the Set Instance vie. menu# the View to use column now shows avGe(tracted view.

;. Clic* on the >ecompute t,e ,ierarc,y icon# from schematic to avGe(tracted view.

the configuration is now u)dated

6. From the Analo Desi n 4nvironment window clic* 6etlist and >un to start the simulation again. 9. Ahen simulation com)letes# note the Circuit inventory conditions# this time the list shows all nets# designed devices# sources and )arasitic devices as well. 5. Calculate the dela again and match with the )revious one. 1ow ou can conclude how much dela is introduced b these )arasites# now our main aim should to minimi@e the dela due to these )arasites so number of iteration ta*es )lace for ma*ing an o)timi@e la out.

Generating Strea" +ata

76

Streamin 'ut t,e Desi n


1. %elect 2ile 7 4$port 7 Stream from the CIA menu and Airtuoso Fstream out form a))ears change the following in the form.

2. Clic* on the 'ptions button. 7. In the Stream'ut8'ptions form select clic* '91 under %ayers tab and

;. In the Airtuoso FStream 'ut form# clic* Translate button to start the stream translator. <. 2he stream file Inverter.gds is stored in the s)ecified location.

Streamin In t,e Desi n


1. %elect 2ile 7 Import 7 Stream from the CIA menu and change the following in the form.

79 Analo " #i$ed Si nal %a&s

75

!ou need to s)ecif the pd)18*+oa221tf file. 2his is the entire technolog file that has been dum)ed from the design librar . 2. Clic* on the 'ptions button. 7. In the Stream'ut8'ptions form select clic* '91 under %ayers tab and

;. In the Airtuoso FStream 'ut form# clic* Translate button to start the stream translator. <. From the $ibrar -anager o)en the Inverter cellview from the 5DS+%IB librar and notice the design. 6. Close all the windows e(ce)t CIA window# which is needed for the ne(t lab.

46D '2 %AB 1


Lab /: +I00 ! NTIAL AM,LI0I ! Sche"atic Ca#t$re
75

Sche"atic ntr%
&b'ecti(e: To create a new cell (iew and b$ild +ifferential A"#lifier

Creatin a Sc,ematic cellvie.


O)en a new schematic window in the myDesi n%i& librar and build the "ifferntialG,m)lifier design.

7D Analo " #i$ed Si nal %a&s

;0 1. In the CIA or $ibrar manager# e(ecute 2ile 7 6e. 7 Cellvie.. %et u) the Create 1ew file form as follows:

7. Clic* '9 when done. , blan* schematic window for the design a))ears.

Addin Components to sc,ematic


1. In the "ifferential ,m)lifier schematic window# e(ecute Create3 Instance to dis)la the ,dd Instance form. 2. Clic* on the Bro.se button. 2his o)ens u) a $ibrar browser from which ou can select com)onents and the Sym&ol view . !ou will u)date the $ibrar 1ame# Cell 1ame# and the )ro)ert values given in the table on the ne(t )age as ou )lace each com)onent. 7. ,fter ou com)lete the ,dd Instance form# move our cursor to the schematic window and clic* left to )lace a com)onent. %i&rary name g)d*150 ;roperties0Comments -odel 1ame E nmos1 =1-0# 1-1> N AE 7u N $E 1u g)d*150 nmos -odel 1ame Enmos1 =1-2# 1-7> N AE ;.<u N $E 1u g)d*150 )mos -odel 1ame E)mos1 =&-0# &-1>N AE 1<u N $E 1u 2his is a table of com)onents for building the "ifferential ,m)lifier schematic. Cell 6ame nmos

7. ,fter entering com)onents# clic* Cancel in the ,dd Instance form or )ress 4sc with our cursor in the schematic window

;0

Addin pins to Sc,ematic


4se Create 7 ;in or the menu icon to )lace the )ins on the schematic window. 1. Clic* the ;in fi(ed menu icon in the schematic window. !ou can also e(ecute Create 7 ;in or )ress p. 2he ,dd )in form a))ears. 2. 2 )e the following in the ,dd )in form in the e(act order leaving s)ace between the )in names. ;in 6ames Idc#V1#V2 Vout vdd# vss# Direction In)ut Out)ut In)utOut)ut

-a*e sure that the direction field is set to input0ouput0inputoutput when )lacing the input0output0inout )ins res)ectivel and the 4sage field is set to sc,ematic. 7. %elect Cancel from the ,dd )in form after )lacing the )ins. In the schematic window# e(ecute Aie.3 2it or )ress the f bind*e .

Addin <ires to a Sc,ematic


,dd wires to connect com)onents and )ins in the design. 1. Clic* the <ire ?narro.@ icon in the schematic window. !ou can also )ress the . *e # or e(ecute Create 8 <ire ?narro.@1 2. Com)lete the wiring as shown in figure and when done wiring )ress ESC *e in the schematic window to cancel wiring.

Savin t,e Desi n


1. Clic* the C,ec) and Save icon in the schematic editor window. 2. Observe the CI< out)ut area for an errors.

S%"bol Creation
&b'ecti(e: To create a s%"bol for the +ifferential A"#lifier

;1 Analo " #i$ed Si nal %a&s

;2 1. In the "ifferential ,m)lifier schematic window# e(ecute Create 3 Cellvie.3 2rom Cellvie.. 2he Cellvie. from Cellvie. form a))ears. Aith the 'dit O)tions function active# ou can control the a))earance of the s mbol to generate. 2. Verif that the 2rom Aie. 6ame field is set to sc,ematic# and the To Aie. 6ame field is set to sym&ol# with the 2oolH"ata 2 )e set as Sc,ematicSym&ol1 7. Clic* '9 in the Cellview from Cellview form. 2he Sym&ol 5eneration 2orm a))ears. ;. -odif the ;in Specifications as in the below s mbol. <. Clic* '9 in the % mbol 3eneration O)tions form. 6. , new window dis)la s an automaticall created "ifferential ,m)lifier s mbol. 9. -odif ing automaticall generated s mbol so that it loo*s li*e below "ifferential ,m)lifier s mbol. 5. '(ecute Create3 Selection Bo$. In the ,dd %election 8o( form# clic* Automatic1 , new red selection bo( is automaticall added.

D. ,fter creating s mbol# clic* on the save icon in the s mbol editor window to save the s mbol. In the s mbol editor# e(ecute 2ile3 Close to close the s mbol view window.

)$ilding the +iff*a"#lifier*test +esign


&b'ecti(e: To b$ild +ifferential A"#lifier Test circ$it $sing %o$r +ifferential A"#lifier Creating the +ifferential A"#lifier Test Cell(iew ;2

1. In the CIA or $ibrar -anager# e(ecute 2ile3 6e.3 Cellvie.. 2. %et u) the Create 1ew File form as follows:

7. Clic* '9 when done. , blan* schematic window for the "iffG am)lifierGtest design a))ears. )$ilding the +iff*a"#lifier*test Circ$it 1. 4sing the com)onent list and &ro)ertiesHComments in this table# build the "iffGam)lifierGtest schematic. %i&rary name
myDesignLib analogLib analogLib analogLib

Cellvie. name
Diff"amplifier vsin vdd, vss, gnd Id!

;roperties0Comments
Symbol Define spe!ifi!ation as #$ %agnitude= 1& #mplitude= 'm& (re)uen!y= 1* +dd=2.' & +ss= ,2.' D! !urrent = -0u

Note: Remember

to set the values for ADD and ASS. Otherwise our circuit will have no

)ower. 7. Clic* the <ire ?narro.@ icon and wire our schematic. Ti#: !ou can also )ress the . *e # or e(ecute Create3 <ire ?narro.@1 ;. Clic* on the C,ec) and save icon to save the design. <. 2he schematic should loo* li*e this.

;7 Analo " #i$ed Si nal %a&s

;;

6. $eave our "iffGam)lifierGtest schematic window o)en for the ne(t section.

Analog Si"$lation with S#ectre


&b'ecti(e: To set $# and r$n si"$lations on the +ifferential A"#lifier Test design1 In this section# we will run the simulation for "ifferential ,m)lifier and )lot the transient# "C and ,C characteristics.

Startin t,e Simulation 4nvironment


;;

1. In the "iffGam)lifierGtest schematic window# e(ecute %aunc, 7 AD4 %. 2he ,nalog "esign 'nvironment simulation window a))ears.

C,oosin a Simulator
1. In the simulation window or ,"'# e(ecute Setup3 Simulator0Directory0Cost1 2. In the C,oosin Simulator form# set the %imulator field to spectre =1ot s)ectre%> and clic* '9.

Settin t,e #odel %i&raries


1. Clic* Setup 8 #odel %i&raries1 6ote: %te) 2 should be e(ecuted onl if the model file not loaded b default. 2. In the -odel $ibrar %etu) form# clic* Bro.se and find the pd)18*1scs file in the 10models0spectre director . %elect stat in %ection field# clic* Add and clic* '91

C,oosin Analyses
1. In the %imulation window# clic* the C,oose 8 Analyses icon. !ou can also e(ecute Analyses 8 C,oose1 2he Choosing ,nal sis form a))ears. 2his is a d namic form# the bottom of the form changes based on the selection above. 2. 2o setu) for transient anal sis a. In the ,nal sis section select tran b. %et the sto) time as Im ;< Analo " #i$ed Si nal %a&s

;6 c. Clic* at the moderate or 4na&led button at the bottom# and then clic* Apply1 7. 2o set u) for "C ,nal ses: a. In the ,nal ses section# select dc. b. In the "C ,nal ses section# turn on %ave "C O)erating &oint. c. 2urn on the Component ;arameter d. "ouble clic* the Select Component# Ahich ta*es ou to the schematic window. e. %elect in)ut signal Asin for dc anal sis. f. In the anal sis form# select start and stop voltages as 8I to I res)ectivel . g. Chec* the enable button and then clic* Apply.

;. 2o set u) for ,C ,nal ses form is shown in the )revious )age. a. In the ,nal ses section# select ac. b. In the ,C ,nal ses section# turn on 2reJuency1 c. In the %wee) Range section select start and stop freCuencies as 1I* to 1**# d. %elect &oints )er "ecade as 2*. e. Chec* the enable button and then clic* Apply. <. Clic* '9 in the Choosing ,nal ses Form.

Selectin 'utputs for ;lottin


;6

%elect the nodes to )lot when simulation is finished. 1. '(ecute 'utputs 7 To &e plotted 7 Select on Sc,ematic in the simulation window. 2. Follow the )rom)t at the bottom of the schematic window# Clic* on out)ut net Ao! in)ut net Ain of the "iffGam)lifier. &ress 4SC with the cursor in the schematic after selecting node. "oes the simulation window loo* li*e thisI

>unnin t,e Simulation


1. '(ecute Simulation 7 6etlist and >un in the simulation window to start the simulation# this will create the netlist as well as run the simulation. 2. Ahen simulation finishes# the 2ransient# "C and ,C )lots automaticall will be )o))ed u) along with netlist.

;9 Analo " #i$ed Si nal %a&s

;5

Savin t,e Simulator State


Ae can save the simulator state# which stores information such as model librar file# out)uts# anal sis# variable etc. 2his information restores the simulation environment without having to t )e in all of setting again. 1. In the %imulation window# e(ecute Session 7 Save State. 2he %aving %tate form a))ears. 2. %et the Save as field to state1+diff+amp and ma*e sure all o)tions are selected under what to save field. Clic* '9 in the saving state form. 2he %imulator state is saved.

Creating a La%o$t View of +iff* A"#lifier


1. From the "iffGam)lifier schematic window menu e(ecute %aunc, 7 %ayout F%. , Startup 'ption form a))ears. 2. %elect Create 6e. o)tion. 2his gives a 1ew Cell View Form 7. Chec* the Cellname ?Diff+amplifier@# Viewname ?layout@1 ;5

;. Clic* '9 from the 1ew Cellview form. $%A and a blan* la out window a))ear along with schematic window.

Addin Components to %ayout


1. '(ecute Connectivity 7 5enerate 7 All from Source or clic* the icon in the la out editor window# 5enerate %ayout form a))ears. Clic* '9 which im)orts the schematic com)onents in to the $a out window automaticall . 2. Re arrange the com)onents with in &R+8oundar as shown in the ne(t )age. 7. 2o rotate a com)onent# %elect the com)onent and e(ecute 4dit 7;roperties. 1ow select the degree of rotation from the )ro)ert edit form.

;. 2o -ove a com)onent# %elect the com)onent and e(ecute 4dit 8#ove command.

#a)in interconnection
1. '(ecute Connectivity 76ets 7 S,o.0Cide selected Incomplete 6ets or clic* the icon in the $a out -enu. 2. -ove the mouse )ointer over the device and clic* %#B to get the connectivit information# which shows the guide lines =or flight lines> for the inter connections of the com)onents. 7. From the la out window e(ecute Create 7 S,ape 7 ;at, or Create 7 S,ape 7 >ectan le ?for vdd and gnd bar@ and select the a))ro)riate $a ers from the %S< window and Vias for ma*ing the inter connections Creating Contacts-Vias !ou will use the contacts or vias to ma*e connections between two different la ers. 1. '(ecute Create 3 Aia or select in below table Connection For -etal1+ &ol Connection command to )lace different Contacts# as given Contact Type -etal1+&ol

;D Analo " #i$ed Si nal %a&s

<0 For -etal1+ &substrate Connection For -etal1+ 1well Connection -etal1+&sub -etal1+1well

Savin t,e desi n


1. %ave our design b selecting 2ile 3 Save or clic* la out should a))ear as below. to save the la out and

,h%sical Verification Assura D>C


>unnin a D>C
1. O)en the "ifferentialG,m)lifier la out form the CIA or librar manger if ou have closed that.&ress s,ift 7 f in the la out window to dis)la all the levels. 2. %elect Assura 8 >un D>C from la out window. 2he "RC form a))ears. 2he $ibrar and Cellname are ta*en from the current <0

design window# but rule file ma be missing. %elect the 2echnolog as pd)18*. 2his automaticall loads the rule file. 7. Clic* '9 to start "RC. ;. , &rogress form will a))ears. !ou can clic* on the watch log file to see the log file. <. Ahen "RC finishes# a dialog bo( a))ears as*ing ou if ou want to view our "RC results# and then clic* Ges to view the results of this run.

6. If there an "RC error e(ists in the design Aie. %ayer <indo. =V$A> and 4rror %ayer <indo. ='$A> a))ears. ,lso the errors highlight in the design itself. 9. Clic* Aie. 7 Summary in the '$A to find the details of errors. 5. !ou can refer to rule file also for more information# correct all the "RC errors and >e 7 run the "RC. D. If there are no errors in the la out then a dialog bo( a))ears with 6o D>C errors found written in it# clic* on close to terminate the "RC run.

ASSU>A %AS
In this section we will )erform the $V% chec* that will com)are the schematic netlist and the la out netlist.

>unnin %AS
1. %elect Assura 7 >un %AS from the la out window. 2he ,ssura Run $V% form a))ears. 2he la out name is alread in the form. ,ssura fills in the la out name from the cellview in the la out window.

<1 Analo " #i$ed Si nal %a&s

<2 2. Verif the following in the Run ,ssura $V% form.

7. 2he $V% begins and a &rogress form a))ears. ;. If the schematic and la out matches com)letel # ou will get the form dis)la ing Sc,ematic and %ayout #atc,.

<2

<. If the schematic and la out do not matches# a form informs that the $V% com)leted successfull and as*s if ou want to see the results of this run.

6. Clic* Ges in the form.$V% debug form a))ears# and ou are directed into $V% debug environment. 9. In the %AS de&u form ou can find the details of mismatches and ou need to correct all those mismatches and >e 7 run the $V% till ou will be able to match the schematic with la out.

Ass$ra !C.
In this section we will e(tract the RC values from the la out and )erform analog circuit <7 Analo " #i$ed Si nal %a&s

<; simulation on the designs e(tracted with RCK. 8efore using RCK to e(tract )arasitic devices for simulation# the la out should match with schematic com)letel to ensure that all )arasites will be bac*annoted to the correct schematic nets.

>unnin >CF
1. From the la out window e(ecute Assura 7 >un >CF. 2. Change the following in the ,ssura )arasitic e(traction form. %elect output t )e under Setup tab of the form.

7. In the 4$traction tab of the form# choose '(traction t )e# Ca) Cou)ling -ode and s)ecif the Reference node for e(traction.

<;

;. In the 2ilterin tab of the form# 4nter ;o.er 6ets as vddH! vssH and 4nter 5round 6ets as ndH

<. Clic* '9 in the ,ssura )arasitic e(traction form when done. 2he RCK )rogress form a))ears# in the )rogress form clic* <atc, lo file to see the out)ut log file. <. Ahen RCK com)letes# a dialog bo( a))ears# informs ou that Assura >CF run completed successfully1

6. !ou can o)en the av+e$tracted view from the librar manager and view the )arasitic.

46D '2 %AB 2

<< Analo " #i$ed Si nal %a&s

<6

Lab /a: C&MM&N S&2!C AM,LI0I ! Sche"atic Ca#t$re

<6

Sche"atic ntr%
&b'ecti(e: To create a new cell (iew and b$ild Co""on So$rce A"#lifier 4se the techniCues learned in the $ab1 and $ab2 to com)lete the schematic of Common %ource ,m)lifier. 2his is a table of com)onents for building the Common %ource ,m)lifier schematic. %i&rary name g)d*150 g)d*150 Cell 6ame )mos nmos ;roperties0Comments -odel 1ame E )mos1N AE <0u N $E 1u -odel 1ame Enmos1N AE 10u N $E 1u

2 )e the following in the ,"" )in form in the e(act order leaving s)ace between the )in names. ;in 6ames vin vbias vout vdd vss Direction In)ut Out)ut In)ut

S%"bol Creation
&b'ecti(e: To create a s%"bol for the Co""on So$rce A"#lifier 4se the techniCues learned in the $ab1 and $ab2 to com)lete the s mbol of cs+am)lifier

<9 Analo " #i$ed Si nal %a&s

<5

)$ilding the Co""on So$rce A"#lifier Test +esign


&b'ecti(e: To b$ild cs*a"#lifier*test circ$it $sing %o$r cs*a"#lifier 4sing the com)onent list and &ro)ertiesHComments in the table# build the cs+am)lifierGtest schematic as shown below. %i&rary name
myDesignLib analogLib analogLib

Cellvie. name
!s"amplifier vsin vdd,vss,gnd

;roperties0Comments
Symbol Define pulse spe!ifi!ation as #$ %agnitude= 1& D$ +oltage= 0& .ffset +oltage= 0& #mplitude= 'm& (re)uen!y= 1* vdd=2.' & vss= ,2.'

Analog Si"$lation with S#ectre


<5

&b'ecti(e: To set $# and r$n si"$lations on the cs*a"#lifier*test design1 4se the techniCues learned in the $ab1 and $ab2 to com)lete the simulation of csGam)lifier# ,"' window and waveform should loo* li*e below.

Creating a la%o$t (iew of Co""on So$rce A"#lifier


<D Analo " #i$ed Si nal %a&s

60 4se the techniCues learned in the $ab1 and $ab2 to com)lete the la out of csGam)lifier. Com)lete the "RC# $V% chec* using the assura tool. '(tract RC )arasites for bac* annotation and Re+simulation.

46D '2 %AB 2a

Lab /b: C&MM&N +!AIN AM,LI0I !


60

Sche"atic Ca#t$re

Sche"atic ntr%
&b'ecti(e: To create a new cell (iew and b$ild Co""on +rain A"#lifier 4se the techniCues learned in the $ab1 and $ab2 to com)lete the schematic of Common "rain ,m)lifier. 61 Analo " #i$ed Si nal %a&s

62 2his is a table of com)onents for building the Common "rain ,m)lifier schematic. %i&rary name g)d*150 g)d*150 Cell 6ame nmos nmos ;roperties0Comments -odel 1ame E nmos1N AE <0u N $E 1u -odel 1ame E nmos1N AE 10u N $E 1u

2 )e the following in the ,"" )in form in the e(act order leaving s)ace between the )in names. ;in 6ames vin# vbias vout vdd vss Direction In)ut Out)ut In)ut

S%"bol Creation
&b'ecti(e: To create a s%"bol for the Co""on +rain A"#lifier 4se the techniCues learned in the $ab1 and $ab2 to com)lete the s mbol of cd+am)lifier

)$ilding the Co""on +rain A"#lifier Test +esign


&b'ecti(e: To b$ild cd*a"#lifier*test circ$it $sing %o$r cd*a"#lifier 4sing the com)onent list and &ro)ertiesHComments in the table# build the cd+am)lifierGtest schematic as shown below.

62

%i&rary name
myDesignLib analogLib analogLib

Cellvie. name
!d"amplifier vsin vdd,vss,gnd

;roperties0Comments
Symbol Define pulse spe!ifi!ation as #$ %agnitude= 1& D$ +oltage= 0& .ffset +oltage= 0& #mplitude= 'm& (re)uen!y= 1* vdd=2.' & vss= ,2.'

Analog Si"$lation with S#ectre


&b'ecti(e: To set $# and r$n si"$lations on the cd*a"#lifier*test design1 4se the techniCues learned in the $ab1 and $ab2 to com)lete the simulation of cdGam)lifier# ,"' window and waveform should loo* li*e below.

67 Analo " #i$ed Si nal %a&s

6;

Creating a la%o$t (iew of Co""on +rain A"#lifier


4se the techniCues learned in the $ab1 and $ab2 to com)lete the la out of cdGam)lifier. Com)lete the "RC# $V% chec* using the assura tool. '(tract RC )arasites for bac* annotation and Re+simulation. 6;

46D '2 %AB 2&

Lab 3: &, !ATI&NAL AM,LI0I ! Sche"atic Ca#t$re

6< Analo " #i$ed Si nal %a&s

66

Sche"atic ntr%
&b'ecti(e: To create a new cell (iew and b$ild &#erational A"#lifier 4se the techniCues learned in the $ab1 and $ab2 to com)lete the schematic of O)erational ,m)lifier. 2his is a table of com)onents for building the O)erational ,m)lifier schematic. %i&rary name m "esign$ib 66 Cell 6ame "iffGam)lifier ;roperties0Comments % mbol

m "esign$ib

csGam)lifier

% mbol

2 )e the following in the ,"" )in form in the e(act order leaving s)ace between the )in names. ;in 6ames Idc#Vinv#Vnoninv Vo vdd# vss Direction In)ut Out)ut In)ut

S%"bol Creation
&b'ecti(e: To create a s%"bol for the &#erational A"#lifier 4se the techniCues learned in the $ab1 and $ab2 to com)lete the s mbol of o)+am).

)$ilding the &#erational A"#lifier Test +esign


&b'ecti(e: To b$ild o#4a"#*test circ$it $sing %o$r o#4a"# 4sing the com)onent list and &ro)ertiesHComments in the table# build the o)+am)Gtest schematic as shown below. %i&rary name
myDesignLib analogLib

Cellvie. name
op,amp vsin

;roperties0Comments
Symbol Define pulse spe!ifi!ation as #$ %agnitude= 1& D$ +oltage= 0&

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65
.ffset +oltage= 0& #mplitude= 'm& (re)uen!y= 1* vdd=2.' & vss= ,2.' D! !urrent = -0u

analogLib analogLib Note: Remember

vd!, gnd Id!

to set the values for vdd and vss. Otherwise our circuit will have no

)ower.

Analog Si"$lation with S#ectre


&b'ecti(e: To set $# and r$n si"$lations on the o#4a"#*test design1 4se the techniCues learned in the $ab1 and $ab2 to com)lete the simulation of o)+am)# ,"' window and waveform should loo* li*e below.

65

Creating a la%o$t (iew of &#erational A"#lifier


4se the techniCues learned in the $ab1 and $ab2 to com)lete the la out of o)+am). Com)lete the "RC# $V% chec* using the assura tool. '(tract RC )arasites for bac* annotation and Re+simulation.

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90

46D '2 %AB 3

Lab 5: !4/! +AC

Sche"atic Ca#t$re

90

Sche"atic ntr%
&b'ecti(e: To create a new cell (iew and b$ild !4/! +AC 4se the techniCues learned in the $ab1 and $ab2 to com)lete the schematic of R+2R ",C. 2his is a table of com)onents for building the R+2R ",C schematic. %i&rary name g)d*150 g)d*150 - "esign$ib analog$ib Cell 6ame )ol res )ol res o)+am) Idc# gnd ;roperties0Comments R E 2* R E 1* % mbol idc E 70u

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92 2 )e the following in the ,"" )in form in the e(act order leaving s)ace between the )in names. ;in 6ames "o "1 "2 "7 Vout vdd# vss Direction In)ut Out)ut In)ut

S%"bol Creation
&b'ecti(e: To create a s%"bol for the !4/! +AC 4se the techniCues learned in the $ab1 and $ab2 to com)lete the s mbol of R+2R ",C.

)$ilding the !4/! +AC Test +esign


&b'ecti(e: To b$ild !4/! +AC Test circ$it $sing %o$r !4/! +AC 4sing the com)onent list and &ro)ertiesHComments in the table# build the R+2R+",CGtest schematic as shown below. %i&rary name
myDesignLib analogLib analogLib

Cellvie. name
/,2/,D#$ vpulse vd!, gnd

;roperties0Comments
Symbol (or +00 v1= 0 v2 = 2 (or +10 v1= 0 v2 = 2 (or +20 v1= 0 v2 = 2 (or +-0 v1= 0 v2 = 2 vdd = 2 vss = ,2 on = 'n = 10n on = 10n = 20n on = 20n = 10n on = 10n = 80n

92

Note: Remember

to set the values for vdd and vss. Otherwise our circuit will have no

)ower.

Analog Si"$lation with S#ectre


&b'ecti(e: To set $# and r$n si"$lations on the !4/!4+AC*Test design1 4se the techniCues learned in the $ab1 and $ab2 to com)lete the simulation of R+2R+ ",C and ,"' window and waveform should loo* li*e below.

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9;

Creating a la%o$t (iew of !4/! +AC


4se the techniCues learned in the $ab1 and $ab2 to com)lete the la out of R+2R+",C. Com)lete the "RC# $V% chec* using the assura tool. '(tract RC )arasites for bac* annotation and Re+simulation.

9;

46D '2 %AB K

Lab 6: SA! )AS + A+C Sche"atic Ca#t$re

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96

+esign Infor"ation
2he %,R 8ased ,"C used in this tutorial is a mi(ed+signal circuit that includes both a schematic database and verilog code. 2he analog com)onents include a vsin signal source# a sam)le and hold circuit=%HL># a com)arator and a R+2R ",C all based on the schematic. 2he successive a))ro(imation register =%,R> and cloc* generator are R2$+ level verilog modules. 2he *e files and directories reCuired are: 1. 2he cds.lib file defines the design libraries and associates logical librar 96

names with )h sical librar locations. 2. 2he hdl.var file defines the variables that affect the behavior of tools and utilities. 7. 2he m "esign$ib librar stores the "igital bloc*s for the schematic database. ;. 2he digGsource director stores the behavioral Verilog code for %,R and Cloc* generator.

T,e A#S Desi ner Simulator


2he VirtuosoJ ,-% simulator is a mi(ed+signal simulator that su))orts the VerilogJ+,-% language standard.

I"#ort the Verilog Mod$le into A+ 2sing Verilog In


1. In a terminal window# change director to the digGsource director where there are 2 Verilog modules. sre 1v +++++++++++++++++++++++++++++++ %uccesive ,))ro(imation Register cloc)1v ++++++++++++++++++++++++++++++ "ivider with factor 2# used for %,R in)ut cloc* 2. In the CI< or Airtuoso window# clic* 2ile 3 Import 3 Aerilo , Aerilo In form a))ears. 7. In the Verilog In form# dou&le8clic) on t,e di +source directory# then clic* on the sre 1v file# t )e myDesi n%i& in the 2arget $ibrar 1ame field =or use the browser to s)ecif it> and clic* Add to the right of the Aerilo 2iles To Import field. 2he full )ath of this verilog file a))ears in the field. 1e(t clic* cloc)1v file and clic* Add ne(t to the same verilog files to Im)ort field. cloc)1v will be added to the field after the sre 1v file.

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95

;. %croll down the form to %tructural View 1ames and change the view name in the Functional field to verilo 1

<. In the ;o.er 6et 6ame field under 5lo&al 6et 'ption tab of the Aerilo In form# change ADDH to ADD1H and clic* '9 in the Aerilo In form.

95

6. Ahen the im)ort is com)lete# a message a))ears as*ing if ou want to see the log file. Clic* Ges to dis)la the log file window.

!ou see error or warning messages in this log file if something is wrong during the im)ort )rocess. 9. Close the log file window. Clic* Tools 3 %i&rary #ana er to o)en the $ibrar -anager. Clic* Aie. 3 >efres,. In the $ibrar column# clic* myDesi n%i& to show all the cells in it. In the Cell column# two new cells =sre and Aerilo +cloc)> are generated.

Sche"atic ntr%
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50 &b'ecti(e: To create a new cell (iew and b$ild SA! )ased A+C

Creatin a Sc,ematic cellvie.


O)en a new schematic window in the myDesi n%i& librar and build the %,R 8ased ,"C design. 1. In the CIA or $ibrar manager# e(ecute 2ile 7 6e. 7 Cellvie.. 2. %et u) the Create 1ew file form as follows:

7. Clic* '9 when done. , blan* schematic window for the design a))ears.

Addin Components to sc,ematic


1. In the %,RG,"C schematic window# e(ecute Create3 Instance or to dis)la the ,dd Instance form. 2. Clic* on the Bro.se button. 2his o)ens u) a $ibrar browser from which ou can select com)onents and the Sym&ol view . !ou will u)date the $ibrar 1ame# Cell 1ame# and the )ro)ert values given in the table on the ne(t )age as ou )lace each com)onent. 7. ,fter ou com)lete the ,dd Instance form# move our cursor to the schematic window and clic* left to )lace a com)onent. 2his is a table of com)onents for building the SA>+ADC schematic. %i&rary name m "esign$ib 50 Cell 6ame %am)leOLold ;roperties0Comments % mbol

m "esign$ib m "esign$ib m "esign$ib m "esign$ib analog$ib analog$ib

O)+am) VerilogGcloc* sareg R+2R+",C vdc# idc# gnd vsin

% mbol % mbol % mbol % mbol vdcE2.<# idcE70u mag E1# am)E<0m# fE100*

7. ,fter entering com)onents# clic* Cancel in the ,dd Instance form or )ress 4sc with our cursor in the schematic window

Addin pins to Sc,ematic


4se Create 7 ;in or the menu icon to )lace the )ins on the schematic window. 1. Clic* the ;in fi(ed menu icon in the schematic window. !ou can also e(ecute Create 7 ;in or )ress p. 2he ,dd )in form a))ears. 2. 2 )e the following in the ,dd )in form in the e(act order leaving s)ace between the )in names. ;in 6ames Vin "0 "1 "2 "7 Direction In)ut Out)ut

-a*e sure that the direction field is set to input0ouput0inputoutput when )lacing the input0output0inout )ins res)ectivel and the 4sage field is set to sc,ematic. 7. %elect Cancel from the ,dd )in form after )lacing the )ins. In the schematic window# e(ecute Aie.3 2it or )ress the f bind*e .

Addin <ires to a Sc,ematic


,dd wires to connect com)onents and )ins in the design.

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52

1. Clic* the <ire ?narro.@ icon in the schematic window. !ou can also )ress the . *e # or e(ecute Create 8 <ire ?narro.@1 2. Com)lete the wiring as shown in figure and when done wiring )ress 4SC *e in the schematic window to cancel wiring.

Savin t,e Desi n


1. Clic* the Check and Save icon in the schematic editor window. 2. Observe the CIA out)ut area for an errors.

Mixed Signal Si"$lation 2sing AMS in A+


Set 2# a Config$ration to !$n Si"$lations fro" A+
1. In the $ibrar -anager# clic* the librar : myDesi n%i&# cell: SA>+ADC. 2. Lighlight %,RG,"C schematic in the $ibrar -anager and clic* 2ile 3 6e. 3 Cell Aie.1 7. In Create 6e. 2ile form# select confi o)tion in the Type field. 2he form should loo* li*e the following figure:

;. Clic* '9. , 1ew Configuration form o)ens. 'nter schematic as the 2o) Cell View or clic* Bro.se button to select it. 1e(t# clic* Use Template at the bottom of the form1

52

<. %elect A#S in the 2em)late 1ame field and clic* '9. Clic* '9 on the 6e. Confi uration form as well.

2he hierarch editor is filled with values for global bindings ta*en from the 6e. Confi uration form. 2he cells in the design are bound to views de)ending on Ahich views of the cell e(ist Ahich e(isting view comes first in the view list

6. Clic* 2ile 8 Save ?6eeded@ to save the configuration. 2he u)date icon in the menu changes as shown in the hierarch editor. Clic* the u)date icon.

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5;

2. Close the schematic and e(it the hierarch editor.

Set Up AD4 'ptions and CustomiLe t,e Connect #odule


1. In the $ibrar -anager# double+clic* config view in the View column. 2he 'pen Confi uration or Top CellAie. form o)ens.

2. 4nder O)en for editing# clic* yes for configuration /%,RG,"CG2est config0 and clic* yes for o)en the 2o) Cell View /%,RG,"CG2est schematic0 and clic* '9. 8oth Configuration and schematic window a))ears.

5;

7. '(ecute %aunc, 7 AD4 % from schematic window to o)en the ,nalog "esign 'nvironment =,"'> window. ;. In the ,"' window# clic* Setup Simulator0Directory0Cost and set the simulator to ams in the %imulator c clic field. Clic* '9.

In the u))er right corner of the ,"' window# confirm that simulator is ams=%)ectre>. If not# clic* Simulation 3 Solver# change the solver to s)ectre and clic* '9. <. Clic* Analyses 3 C,oose. 2hen t )e 3*u in Stop Time field of tran anal sis. Clic* 4na&led and clic* '9. 6. Clic* Setup 8 #odel %i&raries. In the -odel $ibrar %etu) form# clic* 8rowse and find the pd)18*1scs file in the 10models0spectre director . 2 )e 66 in %ection field# clic* Add and clic* '9.

9. Clic* Setup 3 Connect >ules. In the %elect Connect Rules form# highlight Conn>ules+18A+full+fast in the %ist of Connect >ules Used in Simulation and clic* Delete to remove the default selection. In the Built8in rules section# clic* connect%i&1 Conn>ules+3A+full+fast in the Rules 1ame c clic field. 8ecause the )ower su))l in this %,R is 21IA# which doesn.t e(ist in the 8uilt+in rules list# ou need to customi@e the rule.

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56

5. Clic* CustomiLe in the above form. In the Customi@e 8uilt+in Rules form# change the "escri)tion to /T,is is t,e description for #y+Conn>ules+2IA+full+fast0 In the Connect -odule "eclarations list# clic* on %24+2. In the &arameters list# clic* vsup# change 313 to 21I in Value field and clic* C,an e. 1e(t highlight both 42%+2 and Bidir+2 and change the values of the following )arameters: 42%+2 Bidir+2 vsup=21I vsup=21I vt,i=11M vt,i=11M vtlo=*18 vtlo=*18

Clic* '9. In the Information form# which reminds ou to add the customi@ed connect rules to the list# clic* '9.

56

D. In the Select Connect >ules form# clic* Add and select the new modified connect rules. Clic* >ename and edit the rule name to #y+Conn>ules+2IA+full+fast. Clic* '9.

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55 10. In the ,"' window# clic* 'utputs 3 To Be ;lotted 3 Select on Sc,ematic and clic* vsin! D*! D1! D2! D3# As,! Acomp! cl)! tri and Adac in the %,RG,"C %chematic. 11. In the %chematic window# clic* Simulation 3 6etlist 3 Create. ,fter the netlist )rocess is finished# clic* Simulation 3 6etlist 3 Display to dis)la the Verilog+,-% format netlist.

12. Clic* Session 3 Save State. In the %aving %tate form# change the name in %tate %ave "irector field to artistGstates# change the state 55

name to state+ams in the %ave ,s field and clic* '9. 17. In the u))er right corner of the ,"' window# confirm that simulator is ams=%)ectre>. Clic* Simulation 3 6etlist and >un O)tions. ,fter the simulation finishes running# the VIV, automaticall shows the )lotted waveforms.

1;. '(it virtuoso# e(ecute 2ile 3 4$it1

4nd of %a& I

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