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- Digital Systems Testing and Testable Design - Miron Abramovici, Melvin a. Breuer, D Arthur Friedman
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UNIT III – DIGITAL SYSTEM DESIGN Introduction : The concepts of fault modeling ,diagnosis ,testing and fault tolerance of digital circuits have become very important research topics for logic designers during the last decade. With the developments in VLSI technology, there is a drastic increase in the number of components on a single chip.As a result of increase in the chip density ,the probability of fault occurring also increased. So,the logic designer must always consider two points. One is ,to confirm whether the digital circuit operates correctly and is free from faults.This involves the process of fault diagnosis and and testing. The second is , correct operation of the circuit is to be ensured even in the presence of faults. This is the process of fault tolerance. There are different types of faults in digital circuits.A Fault in a circuit is defined as the physical defect of one or more components of the circuit.Faults can be either permanent or temporary. Permanent faults are caused by the breaking or wearing out of components. Permanent faults are also called Hard and Solid faults. Temporary faults are also known as soft faults are those faults that occur only certain intervals of time. These faults can be either transient or intermittent. A Transient fault is usually caused by some externally induced signal disturbance ,such as power supply fluctuations .An Intermittent fault is one that often occurs when a component is in the process of developing a permanent fault. Based on the effect of faults ,they are also classified as Logical or Parametric .A logical fault changes the Boolean function realized by the digital circuit ,while a parametric fault alters the magnitude of the circuit parameter causing a change in speed,current or voltage .A very important parametric fault is the delay fault ,which is caused by slow logic gates.This type of faults leads to problems of Hazards or critical races. The extent of a fault specifies whether the effect of the fault is localized or distributed. A local fault affects only a single variable, whereas a distributed fault affects more than one. A logical fault, for example, is a local fault, whereas the malfunction of the clock is a distributed fault Fault modeling: Logical faults represent the effect of physical faults on the behavior of the modeled system.The advantage of modeling physical faults as logical faults is firstly fault analysis becomes a

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logical rather than a physical problem ; also its complexity is greatly reduced since many different physical faults may be modeled by the same logical fault. Second, some logical fault models are technology-independent in the sense that the same fault model is applicable to many technologies. Hence, testing and diagnosis methods developed for such a fault model remain valid despite changes in technology. And third, tests derived for logical faults may be used for physical faults whose effect on circuit behavior is not completely understood or is too complex to be analyzed. A logical fault model can be explicit or implicit. An explicit fault model defines a fault universe in which every fault is individually identified and hence the faults to be analyzed can be explicitly enumerated. An explicit fault model is practical to the extent that the size of its fault universe is not prohibitively large. An implicit fault model defines a fault universe by collectively identifying the faults of interest typically by defining their characterizing properties. So, fault modeling is closely related to the type of modeling used for the system. Faults defined in conjunction with a structural model are referred to as structural faults ; their effect is to modify the interconnections among components. Functional faults are defined in conjunction with a functional model ; for example, the effect of a functional fault maybe to change the truth table of a component or to inhibit an RTL operation. Fault Classes : There are three important classes logical faults. They are (i) Stuck-at faults (ii) Bridging Faults and (iii) Delay Faults. Stuck-At Fault : The most common model used for logical faults is the single Stuck-at Fault. It assumes that a fault in a logic gate results in one of its inputs or the output is fixed at either a logic 0 (stuck-at-0) or at logic 1 (stuck-at-1). Stuck-at-0 and stuck-at-l faults are denoted by abbreviations s-a-0 and s-a-1, respectively. As an example let us consider a NAND Gate whose input A is s-a-1 .. The NAND gate perceives the A input as a logic 1 irrespective of the logic value placed on the input. For example, the output of the NAND gate is 0 for the input pattern A=0 and B=1, when input A is s-a-1 in. In the absence of the fault, the output will be 1. Thus, AB=01 can be considered as the test for the A input s-a-l, since there is a difference between the output of the fault-free and faulty gate.

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The single stuck-at fault model is often referred to as the classical fault model and offers a good representation for the most common types of defects for e.g., short circuits(shorts ) and open circuits (opens) in many technologies. To explain the stuck-at –model ,let us consider Complementary Metal Oxide Semiconductor realization of two input NAND gate . The number 1 in the figure below indicates an open, whereas the numbers 2 and 3 denote the short between the output node and the ground and the short between the output node and the VDD, respectively.

A short in a CMOS results if not enough metal is removed by the photolitho graphy , whereas over-removal of metal results in an open circuit . Fault 1 in figure below will disconnect input A from the gate of transistors T1 and T3. So, this fault can be represented by a stuck at value of A ; if A is s-a-0, T1 will be ON and T3 OFF, and if A is s-a-l, T1 will be OFF and T3 ON. Fault 2 forces the output node to be shorted to VDD, that is, the fault can be considered as an s-a-l fault. Similarly, fault 3 forces the output node to be s-a-0. The stuck-at model is also used to represent multiple faults in circuits. In a multiple stuck-at fault, it is assumed that more than one signal line in the circuit are stuck at logic 1 or logic 0.In

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other words, a group of stuck-at faults exist in the circuit at the same time. A variation of the multiple fault is the unidirectional fault. A multiple fault is unidirectional if all of its constituent faults are either s-a-0 or s-a-l but not both simultaneously. The stuck-at model is not very effective in accounting for all faults in very large scale

integrated (VLSI), circuits which mainly uses CMOS technology. Faults in CMOS circuits do not necessarily produce logical faults that can be described as stuck-at faults .For example, in figure above , faults 3 and 4 create stuck-on transistors faults. Let us consider the figure (ii) below which implements the Boolean expression

In the diagramt , two possible shorts numbered 1 and 2 and two possible opens numbered 3 and 4 are indicated. Short number 1 can be modeled by s-a-1 of input E ; open number 3 can be modeled by s-a-0 of input E, input F, or both. On the other hand, short number 2 and open number 4 cannot be modeled by any stuck-at fault because they involve a modification of the network function.

For example, in the presence of short number 2, the network function will change to the following new function given below.

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and open number 4 will change the function to

For this reason, a perfect short between the output of the two gates cannot be modeled by a stuck-at fault. Without a short, the outputs of gates Z1 and Z2 are

whereas with the short, Bridging Faults : Bridging faults are an important class of permanent faults that cannot be modeled as stuck-at faults. A bridging fault is said to have occurred when two or more signal lines in a circuit are connected accidently together. Bridging faults at the gate level has been classified into three types: input bridging and feedback bridging and non-feedback bridging. An input bridging fault corresponds to the shorting of a certain number of primary input lines. A feedback bridging fault results if there is a short between an output and input line. A feedback bridging fault may cause a circuit to oscillate, or it may convert it into a sequential circuit. Bridging faults in a transistor-level circuit may occur between the terminals of a transistor or between two or more signal lines. Figure (i) below shows the CMOS logic realization of the Boolean function

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A short between two lines, as indicated by the dotted line in the diagram will change the function of the circuit. The effect of bridging among the terminals of transistors is technology-dependent. For example, in CMOS circuits, such faults manifest as either stuck-at or stuck-open faults, depending on the physical location and the value of the bridging resistance. A non-feedback bridging fault identifies a bridging fault that does not belong to either of the above types. From the above it is clear that ,the probability of two lines getting bridged is higher if they are physically close to each other. The theory on the bridging faults assumes that the probability of more than two lines shorting together is very low,and wired logic is performed at the connections. In general a bridging fault in positive logic is assumed to behave as a wired-AND(whwere 0 is the dominant logic value) and a bridging fault in negative logic behaves as a wired –OR(where 1 is the dominant logic value). If bridging between any s lines in a circuit are considered ,the number of single bridging faults alone will be ( n/s)! and the number of multiple bridging faults will be very high. Delay Faults : Smaller defects, which are likely to cause partial open or short in a circuit, have a higher probability of occurrence due to the statistical variations in the manufacturing process.These defects result in the failure of a circuit to meet its timing specifications without any alteration of

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the logic function of the circuit. A small defect may delay the transition of a signal on a line either from 0 to 1, or vice versa. This type of malfunction is modeled by a delay fault. The delay faults are two types.They are (a) Gate delay fault and (b).Path delay fault. Gate delay faults have been used to model defects that cause the actual propagation delay of a faulty gate to exceed its specified worst case value. For example, if the specified worst case propagation delay of a gate is x units and the actual delay is x+Δx units, then the gate is said to have a delay fault of size Δx. The main deficiency of the gate delay fault model is that it can only be used to model isolated defects, not distributed defects, for example, several small delay defects. The path delay fault model can be used to model isolated as well as distributed defects. In this model, a fault is assumed to have occurred if the propagation delay along a path in the circuit under test exceeds the specified limit. Transition and Intermittent faults : The transition and Intermittent faults are considered as Temporary faults. In digital circuits a major part of the malfunctioning is due to the temporary faults and these faults are always difficult to detect and isolate. Transient faults are non-recurring temporary faults that caused by power supply fluctuations or exposure of the circuit to certain external radiation(like α-particle radiation).These are not repairable as there is no physical damage to the hardware.They are the major source of failures in semiconductor memory chips. Intermittent faults occur due to loose connections , partially defective components or poor designs. They are recurring faults that appear on regular basis. The intermittent faults that occur due to deteriorating or aging components may eventually become permanent.Some intermittent faults may also occur due to environmental conditions such as temperature ,humidity ,vibration etc. The occurance of intermittent faults depends on how well the system is protected from its physical environment through shielding ,filtering ,cooling etc.An intermittent fault in a circuit causes malfunction of the circuit only if it is active,if it is inactive ,the circuit operates correctly.A circuit is said to be in a fault active state if a fault present in the circuit is active and it is said to be in the fault-not-active state if a fault is present but inactive.

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Since ,the intermittent faults are random ,they can be modelled only by using probabilistic methods.The first model used was the Two-state first order Markov model.This model is for a specific class of intermittent faults,which are well behaved and signal independent .An intermittent fault is well behaved if ,during an application of test pattern ,the circuit under test behaves as if either it is a fault free or a permanent fault exists.An intermittent fault is signal independent if its being active doesnot depend on the inputs or the present state of a circuit.

The diagram above shows fault model proposed by Breuer.It assumes that the fault oscillates between the fault active state (FA) and fault not active state (FN).The transition probabilities depend on a selected time-step.i.e they have to be changed if this time step is changed.

Fault diagnosis of Combinational circuits by conventional methods: A very important activity in the manufacturing of digital ICs is to determine whether the circuit contains a faults ,and if so ,to locate the fault and to replace the faulty components. The task of finding whether a fault is present or not is called Fault detection and the task of isolating the

fault is called fault location. The combined task of fault detection and location is known as fault diagnosis. Testing is a process of diagnosing the faults. Generally testing of logical circuits consists of applying a set of input combinations to the primary inputs of the circuit. So,the aim of testing is to verify that each logic gate in the circuit is functioning properly and the interconnections are good. If a single stuck-at fault is present in the circuit under test, then the problem is to construct a test set that will detect the fault by utilizing only the inputs and the outputs of the circuit.

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Dr.Y.Narasimha Murthy.,Ph.D yayavaram@yahoo.com

One of the main objectives in testing is to minimize the number of test patterns. If the function of a circuit in the presence of a fault is different from its normal function (i.e., the circuit is non redundant), then an n-input combinational circuit can be completely tested by applying all 2n combinations to it , however, 2n increases very rapidly as n increases. There are several different test generation methods for combinational circuits. These methods are based on the assumptions that a circuit is non-redundant and only a single stuck-at fault is present at any time. Path Sensitization Technique: The basic principle of the path sensitization method is to choose some path from the origin of the fault to the circuit output. A path is sensitized if the inputs to the gates along the path are assigned values such that the effect of the fault can be propagated to the output. To explain this technique let us consider circuit shown in figure below and assume that line α is s-a-1. To test for α, both G3 and C must be set at 1. In addition, D and G6 must be set at 1 so that G7=1 if the fault is absent. To propagate the fault from G7 to the circuit output f via G8 requires the output of G4 to be 1. This is because if G4=0, the output f will be forced to be 1, independent of the value of gate G7. The process of propagating the effect of the fault from its original location to the circuit output is known as the forward trace.

Let us consider now the backward trace, in which the necessary signal values at the gate outputs specified in the forward trace phase are established. For example, to set G3 at 1, A must be set at 0, which also sets G4=1. In order for G6 to be at 1, B must be set at 0 .It is clear that G6 cannot be set at 1 by making C=0 because this is inconsistent with the assignment of C in the forward trace

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phase. Therefore, the test ABCD=0011 detects the fault α s-a-1, since the output f will be 0 for the fault-free circuit and 1 in the presence of the fault. Generally , a test pattern generated by the path sensitization method may not be unique . The main drawback of the path sensitization method is that only one path is sensitized at a time. This does not guarantee that a test will be found for a fault even if one exists. As an example,let us derive a test for the fault α s-a-0 in the figure (ii) below. To propagate the effect of the fault along the path G2−G6−G8 requires that B, C, and D should be set at 0. In order to propagate the fault through G8, it is necessary to make G4=G5=G7=0. Since B and D have already been set to 0, G3 is1, which makes G7=0. To set G5=0, A must be set to 1 ; as a result, G1=0, which with B=0 will make G4=1. Therefore, it is not possible to propagate the fault through G8. Similarly, it is not possible to sensitize the path G2−G5−G8. However, A=0 sensitizes the two paths simultaneously and also makes G4=0.

Thus, two inputs to G8 change from 0 to 1 as a result of the fault α s-a-0, while the remaining two inputs remain fixed at 0. Consequently, ABCD=0000 causes the output of the circuit to change from 1 to 0 in the presence of α s-a-0 and is the test for the fault. This example shows the necessity of sensitizing more than one path in deriving tests for certain faults and is the principal idea behind the D-algorithm. Boolean Difference Method: A combinational circuit can be tested for the presence of a single stuck-at fault by applyinga set of inputs (a test pattern) that excite a verifiable output response in that circuit. The Boolean

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difference method is one of the important algebraic methods of test generation in which the test vectors are generated by using the properties of Boolean algebra. The Boolean difference method is an algebraic procedure for determining the complete set of tests that detect a given fault. .The method consists of two parts . First, construct a formula expressing the Boolean difference of a circuit with respect to a given fault. Second, apply a Boolean satisfiability algorithm to the resulting formula. Since the Boolean difference formula defines the complete set of tests capable of distinguishing between the faulted and unfaulted circuits, satisfying this formula will give us a set of inputs that detect the fault. Let us consider a combinational circuit which realizes the function f(x1,x2,x3---------xn).The Boolean difference of a function f(x1,x2,x3----------------------xn) with respect to one of its variables xi is given by

df ( x ) f ( x1 , x2 , x3 xi 1 ,0, xn ) f ( x1 , x2 , x3 xi 1 ,1, xn ) dxi Let us denote the function f(x1,x2, x3…..xn-1,0,….xn) by fi(0) and f(x1,x2, x3…..xn-1,1,….xn)

by fi(1).

df ( x) f i (0) f i (1) dxi

If

df ( x ) 0, then fi(0) ≡ fi(1) and it implies that f(x) is independent of xi .Similarly if dxi

df ( x ) 1, then any change in the value of xi will affect the value of f regardless of remaining dxi

**variables. The objective behind this is to find those values of variables for which
**

df ( x ) 1, as these are dxi

the values that makes the output f ,to be incorrect(faulty) when a fault exists on line xi . In order to test xi for a s-a-0 fault it is important to assign the value 1 to xi and to assign all other values in such a way that is given by the equation xi

df ( x ) 1, .Consequently ,the set of tests which detect the fault x i s-a-0 dxi df ( x ) 1, dxi

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Similarly, the set of tests which detect the fault xi1

df ( x ) 1, dxi

As an example let us consider the circuit shown below.

The Boolean difference with respect to X3 is determined as below.

Using the equation

df ( x ) 1, dxi

To find the tests for detecting a s-a-0 fault ,we get

This expression is equal to 1 when any one of the three product terms is equal to 1.So,each of the following input combinations is a test for x3 s-a-0. (x1,x2,x3,x4) = {(0,0,1,1),(1,ϕ ,1,0),(ϕ,1,1,0)} Similarly the tests for detecting a s-a-1 fault at x3 are determined from the equation xi1 is as follows

df ( x ) 1, dxi

Hence These are the test sets to find the fault .

.

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Kohavi algorithm : The path sensitization method and the Boolean difference methods are not practically feasible for multiple faults , even for circuits of ordinary moderate size.This is because both the methods consider only one fault at a time.and the total number of states to be tested in a circuit with nlines become 3n-1 ,if multiple faults are allowed.So,Kohavi & Kohavi proposed a new algorithm in the year 1972 to overcome this problem. This technique has two sets of tests,namely a-tests and b-tests and considers the altered Boolean function realization by the circuit due to the presence of a single fault rather than considering the faults itself.For the effective implementation of this algorithm ,three restrictions are imposed by Kohavi. The first one is that ,the network must be a two –level AND-OR (or) OR-AND network. The second restriction is that ,each AND gate must realize a prime cube. The third one is that ,the AND-OR network must implement a Boolean function which is a sum of intrudant prime implicant. To explain this algorithm,let us consider a two-level AND-OR circuit and assume that each AND gate of the circuit realizes an irredundant prime implicant .Hence the output function of the circuit can be expressed as a sum of irredundant prime implicants or cubes. Consider a SA0 fault on any of the inputs of an AND gate.the effect of this fault on the output function is the elimination of the prime implicant realized by the AND gate. The set of distinguished minterms that tests each AND gate for SA0 faults is called the set of atests .The set of minterms that tests each AND gate for SA1 faults is called the set of b-sets.

The circuit above realizes the function f= x1 x’2+ x3 x4 .The prime implicants of the function are x1x’2 = 1022 and x3x4 =2211 which can be found from the Karnaugh map. References 1.Logic Design Theory –N.N.Biswas 2.Digital circuit testing and Testability –Parag.K.Lala.

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