You are on page 1of 4


6 JUNE 2006


Special Section on Analog Circuit and Device Technologies

Design of Analog Current-Mode Loser-Take-All Circuit

Mohsen ASLONI a) , Student Member, Abdollah KHOEI b) , and Khayrollah HADIDI c) , Members

SUMMARY A CMOS circuit is proposed which takes multiple analog input currents and extracts minimum input current at the output. It is very fast and requires no subtraction from the constant current source. It exhibits O(N) complexity and uses only 4N MOS transistors where N is the number of system inputs. This circuit consumes very little power and very small area. The substrate bias aects the threshold voltage of transistors and improves performance of the structure. key words: loser-take-all, winner-take-all

of currents, hence precision of the circuit is preserved. This structure also uses the body eect of transistors and improves the performance of the proposed circuit.



One of the principal parts of computational systems such as fuzzy controllers and neural networks is inference engine which consists of the Min and Max circuits [4],[5],[7],[8],[9]. These circuits use the loser-takeall (LTA) and winner-take-all (WTA) structures. Since 1988 in which lazzaro[6] presented the report on WTA structures, a lot of WTA and closely related LTA circuits have been proposed[1],[3] . Some of the proposed architectures use winner-take-all to compute loser-takeall function by subtracting input values from a xed reference current. The scheme of this structure is shown in Fig. 1. One of these circuits uses subtraction from a xed current and then selection of maximum current performs as a minimum current selector[2]. The analog subtraction implies loss of accuracy and limits the input current to the value of a xed reference, moreover it needs large number of MOS transistors, which increases power consumption. There are two types of the structures which have O(N) and O(N2 ), respectively. The systems with O(N2 ) occupy more area and consume high power because they grow quadratically with number of the input currents. Also, due to many devices between minimum input and output stage, the circuit precision decreases. On the other hand, structures with O(N) complexity grow linearly with the number of input currents. This paper presents a new structure with O(N) complexity which decreases the occupied area and power consumption. It does not need any subtraction
Manuscript received November 2, 2005. Manuscript revised January 15, 2006. The authors are with the Microelectronic Research Laboratory, Department of Electrical Engineering, Urmia University,Urmia57159, Iran a) E-mail: st b) E-mail: c) E-mail:

Fig. 1

LTA network using WTA network

Section 2 presents the proposed circuit architecture and describes its operation. Calculations are done in section 3. The analysis of accuracy is given in section 4 and analysis of substrate bias is presented in section 5 and simulation results on the proposed circuit are in section 6. Section 7 concludes this paper. 2. Circuit Description

The function of loser-take-all structure is dened by relation (1). f (I1 , I2 , ..., IN ) = min(I1 , I2 , ..., IN ) (1)

This function can be obtained with function of winner-take-all structure using (2). f (I1 , I2 , ..., IN ) = min(I1 , I2 , ..., IN ) = Iref max(I1 , I2 , ..., IN )


The structure presented in this paper uses the rst


VT D = |VT P | VT N


In the rst region, M5 is o, as M4 is in saturation region, thus: Imin VT D k4 (5)

There are three conditions in the second region. For the rst condition, M5 is in saturation region and M4 is in triode region. I + VT D k5 Imin k4 (6)

For the second condition, M2 is in saturation region.

Fig. 2 The schematic diagram of the proposed circuit

V S2 VS1 V T N Also it is obtained that: V I1 V S 2 = Also: V S 2 = VI1 { And: V I1 = V S 1 + { IM3 + VT N } K3 I + |VT P |} k5 I + |VT P | k5


method which consumes less power and has better precision. It comprises of input cells and output block. The schematic diagram of the proposed circuit is shown in Fig. 2. There are N cells which correspond to N inputs of the structure. Every cell has 4 MOS transistors as shown. Also, there is the output stage composed of two cascoded devices. The rst input block is dierent from the other input blocks because this block produces the bias voltage of the LTA circuit. It is assumed that the circuit has 2 inputs, for simplicity. To analyze this structure, the operation region of the circuit is divided to 3 regions. In the rst region, I2 is more than I1 . In the second region, I1 is more than I2 and in the third region, I1 and I2 are the same. In the rst region, since the bias voltage is identied by I1 , and I2 is more than I1 , M4 can not sink all I2 . So M4 only sinks I1 and (I2 - I1 ) is drawn by M6 . In the second region, as I1 is more than I2 and the bias voltages of the circuit are identied by I1 , then M2 and M4 tend to work in triode region. For this reason, M5 will be on and (I1 - I2 ) is drawn by M5 . So M2 stays in saturation region but M4 leaves saturation region and operates in triode region. The third region is located between latter two regions. In this region, as I1 is the same as I2 and the overdrive voltages of M1 and M2 are the same, hence M5 and M6 are in cut-o region. 3. Principal Conditions




Substituting (9) and (10) in (7), we obtain: VS1 + { { IM3 + VT N } k3 (11)

I + |VT P |} VS1 VT N K5

Using k3 = k4 and substituting them in (11), we obtain: Imin k4 I + VT D V T N 0 k5 (12)

For the third condition, using this point that M4 is in triode region, we obtain: Imin |V T P | k4 (13)

In this section, the conditions in which the circuit is operated, is shown. The sizes of M1 and M2 are the same as well as M3 and M4 . For simplicity, two parameters are dened that are used in this paper: k= 1 W n Cox ( ) 2 L (3)

It is assumed that the range of the applied input currents is restricted to IH . For obtaining the basic condition, the current range of the circuit is substituted in (5), (6), (12) and (13). Now we calculate these boundaries:



Boundriess Calculations


The Substrate Bias Eect

1. By substituting IM in = IH in (5), it is obtained: IH VT D k4 (14)

When the voltage is applied to the bulk, it aects the threshold voltage of a MOS transistor. The threshold dierence due to an applied source to the bulk voltage is expressed as: VT = ( |2F + VSB | 2F ) (21)

2. By substituting IM in = IH and ID =0 in (6), we have: IH VT D k4 (15)

3. By substituting IM in =0 and ID = IH in (12), it is resulted in: IH VT N 0 VT D k5 (16)

Where is the body eect parameter given by: 2s qNa (22) = Cox So, we obtain by: VT D = 5 4 |2F + |VSB5 || |2F + VSB4 | (23)

4. By substituting IM in =IH in (13), it is obtained that: IH |VT P | k4 (17)

Hence VT D can be increased with bulk bias. Hence, according to (18) the range of input currents will also increases, if the rst term of (18) would be smaller than the second term. 6. Simulation Results

From combination of above four conditions, we obtain the nal equation for estimating the current range belonged to the input currents:
2 2 IH = min(k4 VT D , k5 (VT N 0 VT D ) ) (18)

It is seen clearly that the range of the input currents is dependent to k4 , k5 , VT D and VT N 0 but it is known that two last parameters are not variable in CMOS processes, so only k4 and k5 are variable. However, we know that the bulk eect, aects on VT D .Now, we can increase the current range of inputs. 4. Error of The Circuit

We simulated the circuit for 2 input and 3 input cases in 0.35 process with 3.3 v power supply. Using (18), the range of input current obtained is about 0 20 A. The sizes of MOS transistors for simulation of the circuit are shown in Table 1. The results are shown in Fig. 3 ,Fig. 4 ,Fig. 5 and Fig. 6 . In both cases, the circuit is simulated for two ranges of input currents. 7. Conclusion

We presented a new CMOS structure for loser-take-all network. It exhibits O(N) complexity and uses only
Table 1 The sizes Mn W L M1 1 0 .5 M2 1 0 .5 M3 1 0 .5 of MOS transistors Mn W L M4 1 0 .5 M5 5 0 .5 M6 3 0 .5

Obtaining precise error in this structure and similar structures is dicult. For this reason, the error of the proposed circuit is estimated. The largest error in this structure is produced in the case of I1 I2 . When I1 I2 , because M1 , M2 and M5 are in saturation region, and drain to source voltages of M1 and M2 are not the same, we have: IM1 1 + VT N Iout = = Imin IM2 1 + (Vds Vdssat. ) In the worst case, we have: Vds Vdssat. = 0 Iout = 1 + VT N Imin (20) (19)

However, since M5 is in saturation region, it inhibits the drain to source voltage of M2 to drop to the boundary of saturation and triode region. Thus this worst case does not occur.

Fig. 3 Simulation results for 2 input case circuit with current range of 4 6 A for IN1 and IN2




Fig. 4 Simulation results for 2 input case circuit with current range of 2 8 A for IN1 and IN2




trollers, Electron. Lett. , 6th June 1996, 32,(12), pp. 10671069 N. Donckers, C. Dualibe and M. Verleysen: A Currentmode CMOS Loser-Take-All with minimum function for neural computation , ISCAS 2000 - IEEE International Symposium on Circuits and Systems, May 28-31, 2000, Geneva, Switzerland, pp. 415-418 J. Lazzaro, S. Ryckebusch, M. A. Mahowald and C. A. Mead: Winner-take-all networks of O(n) complexity ,Advances in neural information processing system, 1, D. S. Touretsky, Ed. Los Altos, CA: Morgan Kaufman,1989, pp. 703-711 M. Sasaki, T. Inoue, U. Shirai and F. Ueno: Fuzzy Multiple-Input Maximum and Minimum Circuits in Current Mode and Their Analyses Using Bounded-Dierence Equations , IEEE Transactions on computers, June 1990, Vol. 39, No. 6, pp. 768-774 L. Lemaitre, M. J. Patyra and D. Mlynek: Analysis and Design of CMOS Fuzzy Logic Controller in Current Mode, IEEE Journal of Solid-State Circuits, March 1994, Vol 29, No. 3, pp. 317-322 R. G. Carvajal, A. Torralba, R. Millan and L. G. Franquelo: Automatic Synthesis of Analog and Mixed-Signal Fuzzy Controllers with Emphasis in Power Consumption, ISCAS 99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, vol.5, pp. 571-574

Fig. 5 Simulation results for 3 input case circuit with current range of 46 A for IN1 ,IN2 and 28 A for IN3

Fig. 6 Simulation results for 3 input case circuit with current range of 28 A for IN1 ,IN2 and IN3

4N MOSFETs. For this reason, the power consumption is low and occupied area is small, while it achieves high speed operation. In fact, the main reason for its high speed and good precision is lack of any current subtraction. Notice that the currents all are unipolar and the related range is about 0 20 A .
References [1] G.N. Patel and S.P. DeWeerth: Compact current-mode loser-take-all circuit, Electron. Lett. , 23rd November 1995, 31, (24), pp. 2091-2092 [2] I. Baturone, J.L. Huertas, A. Barriga and S. Sanchez Solano: Current-mode multiple-input Max circuit, Electron. Lett. , 28th April 1994, 30,(9),pp. 678-680 [3] C. Y. Huang and B. D. Liu: Current-mode multiple input maximum circuit for fuzzy logic controllers, Electron. Lett. ,10th November 1994,30,(23),pp. 1924-1925 [4] C. J. Huang, C. Y. Wang, and B. D. Liu: Modular currentmode multiple input minimum circuit for fuzzy logic con-