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EE 577a VLSI DESIGN I FALL 2013 INSTRUCTOR: M.

PEDRAM LAB ASSIGNMENT 1

Submitted by

KARTHIK RAMASAMY 5539 4733 38

SPECIFICATION:

Supply Vdd = 1.8V. Data and Clock transitions are 10ps. Clock signal has 50% duty cycle. Both true and the complement signals are available.

SRAM CELL DESIGN:

1. 256 bit SRAM DESIGN: a) Read Delay (ns) 0.33 0.28 Write Delay (ns) 0.065 0.06

i. ii.

All 6T of 4/2 6/2 Inverter Nmos 4/2 Nmos Access 4/3 Inverter Pmos

I have chosen the case ii. The area for the 6T SRAM cell of Case ii: 4.6 * 5.05 = 22.725 b) Comparison of Architectures: The following observations are from the schematic simulations mimicking the load capacitances of the different Architectures. Read Delay (ns) 0.33 0.33 0.328 Write Delay (ns) 0.225 0.203 0.22

i. ii. iii.

One 644 Bit Two 324 Bit (2-1 Mux) Four 164 Bit (4-1 Mux)

Model: = 50.14 = 225.78 fF The elmore delay = 0.69 /2 = 3.9 ps

c) The Architecture chosen is 32 8 with 4 (2-1) Mux.

i. ii. iii.

The BIT BIT line bar time is 226 ps. Sense Amplifier delay is 58 ps. The write delay is less than the read delay.

Sizing: Sense Amplifier (Optimized) = 3um = 800nm = 800nm = 600nm = 600nm = 1um = 1um

Mux: (Read,Write) Mux has the sizing of W = 4um L = 200nm The write and the Precharge circuitry has the default sizing.

2. DECODER DESIGN: The pre decoding implementation is done with the 3 input NAND, 2 input NAND and 3 input NOR gates with a enable signal.

3. OUTPUT REGISTER: The D-FLIP FLOP (4 FF) using Transmission Gate is used at the output of the Sense Amplifier with the Clock Period of 3ns.

4. SRAM LAYOUT: The 256 bit SRAM Layout is done using the optimized 6T SRAM cell, Row Decoder, Write Circuitry, Read Circuitry, Column Muxes and the output Registers. Metal 1,2,3 are used for routing.

DELAY OF SRAM:

READ DELAY OF SRAM 256bits = 3ns AREA = 13,348.68

LVS OUTPUT: @(#)$CDS: LVS version 6.1.4-64b 09/21/2011 03:25 (sjfdl054) $ Command line: /usr/local/cadence/IC610/tools.lnx86/dfII/bin/64bit/LVS -dir 13/kramasam/cds/LVS -l -s -t /home/scf-13/kramasam/cds/LVS/layout 13/kramasam/cds/LVS/schematic Like matching is enabled. Net swapping is enabled. Using terminal names as correspondence points. Compiling Diva LVS rules... Net-list summary for /home/scf-13/kramasam/cds/LVS/layout/netlist count 808 nets 36 terminals 864 pmos 1412 nmos Net-list summary for /home/scf-13/kramasam/cds/LVS/schematic/netlist count 808 nets 36 terminals 840 pmos 1340 nmos /home/scf/home/scf-

Terminal correspondence points N778 N33 A0 N799 N94 A0_b N776 N87 A1 N785 N91 A1_b N775 N83 A2 N800 N101 A2_b N774 N98 A3 N786 N105 A3_b N773 N97 A4 N801 N104 A4_b N772 N38 A5 N787 N100 A5_b N805 N14 D0 N804 N99 D1 N803 N26 D2 N802 N103 D3 N784 N92 D_b0 N783 N86 D_b1 N782 N52 D_b2 N780 N74 D_b3

N806 N792 N795 N791 N797 N790 N777 N789 N798 N788 N779 N796 N807 N793 N781 N794

N50 N22 N27 N82 N79 N13 N96 N12 N95 N15 N20 N49 N19 N17 N1 N0

Precharge Read_en Write_en Z0 Z0_b Z1 Z1_b Z2 Z2_b Z3 Z3_b clk clk_b en gnd! vdd!

Devices in the netlist but not in the rules: pcapacitor Devices in the rules but not in the netlist: cap nfet pfet nmos4 pmos4 The net-lists match. layout schematic instances 0 0 0 0 0 0 0 0 2276 2180 2276 2180 nets 0 0 0 808 808

un-matched rewired size errors pruned active total

un-matched merged pruned active total

0 0 0 808 808

un-matched matched but different type total

terminals 0 0 0 36 0 36

Probe files from /home/scf-13/kramasam/cds/LVS/schematic devbad.out: netbad.out: mergenet.out: termbad.out: prunenet.out: prunedev.out: audit.out: Probe files from /home/scf-13/kramasam/cds/LVS/layout devbad.out: netbad.out: mergenet.out: termbad.out: prunenet.out: prunedev.out: audit.out:

WAVEFORMS: SCHEMATIC:

LAYOUT WAVEFORMS: