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B.Tech III Year I Semester (R09) Regular & Supplementary Examinations December/January 2013/14

**DIGITAL SYSTEM DESIGN
**

(Computer Science & Systems Engineering)

Time: 3 hours Answer any FIVE questions All questions carry equal marks ***** 1 Draw an ASM chart to design a FSM which directs 11001 and 10001 bit sequences and set output Z = 1. For all offer sequences Z = 0. Realize the sequence detector using D-flip-flops and MUXs. (a) Describe some important features of an FPGA and a CPLD. (b) With an example, explain how an FPGA is useful in the design of a digital circuit. What is the significance of Kohavi algorithm? Explain how it is useful in the detection of faults in digital circuits. (a) With an example, explain, the transition count testing method. (b) Describe the algorithm steps involved in PODEM. Design a fault diagnosable machine for the 101 sequence detector. Use successor tree. (a) Describe the advantages of PLA minimization and folding. (b) Design a 3 bit BCD to grey code converter and realize the circuit using PLA and then show that how folding will reduce the number of cross points on the PLA. Describe the various DFT schemes used in digital circuits. (a) With respect to an Asynchronous sequential machine, explain about minimal closed covers. (b) Explain the following with examples: (i) Flow table. (ii) State reduction. Max. Marks: 70

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Code: 9A15502

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B.Tech III Year I Semester (R09) Regular & Supplementary Examinations December/January 2013/14

**DIGITAL SYSTEM DESIGN
**

(Computer Science & Systems Engineering)

Time: 3 hours Answer any FIVE questions All questions carry equal marks ***** 1 (a) Draw an ASM chart to design a control logic of a binary multiplier. Realize the same using MUX decoder and D-type flip-flops. (b) What is difference between Melay and Moore state machine? Draw the general structure of an FPGA and explain how a logic function can be realized on FPGA with a suitable example. What are the different faults found in combinational circuits? How can they be categorized? With an example, explain the transition count testing method, signature analysis and random testing. (a) Find a preset distinguish experiment that determine the initial state of the machine shown in table given below. Given that it cannot be initially in state E. (b) Can you identify the initial state when the initial uncertainty is (ABCDE)? Table Ns Z Ps X=0 X=1 A B,1 A,1 B E,0 A,1 C A,0 E,1 D C,1 D,1 E E,0 D,1 Apply PLA maximization procedure and obtain the minimized expression to be implemented on PLAF = 2021 + 0022 + 1200. Discuss the steps involved in the PLA folding algorithm ‘compact’. Write a short notes on: (i) Fundamental mode model. (ii) Races, cycles and hazards. Max. Marks: 70

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Code: 9A15502

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B.Tech III Year I Semester (R09) Regular & Supplementary Examinations December/January 2013/14

**DIGITAL SYSTEM DESIGN
**

(Computer Science & Systems Engineering)

Time: 3 hours Answer any FIVE questions All questions carry equal marks ***** 1 (a) Develop an ASM chart of D-flip-flop and realize it using only NAND gates. (b) Discuss in detail about reduction of state table and state assignments. Explain the steps involved in system design using PLA with an example. (a) List out the Boolean difference properties and explain them. (b) Apply Kohavi’s algorithm to the given POS function F = (A+ ) (C+BD). (a) Briefly describe about the different types of fault model and fault types in a PLA. (b) Explain briefly about random testing and transition count testing. (a) Discuss the BIST scheme for PLD and CPLDs. (b) With an example, explain the principle of operation of path sensitizations method. (a) Explain briefly, the occurrence of various types of hazards in digital circuits. (b) With an example, explain how faults are detected in a PLA. Describe a square generator of a given 3-bit input using PROM. Describe an asynchronous BCD down counter using JK flip-flops and explain its operation. Max. Marks: 70

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Code: 9A15502

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B.Tech III Year I Semester (R09) Regular & Supplementary Examinations December/January 2013/14

**DIGITAL SYSTEM DESIGN
**

(Computer Science & Systems Engineering)

Time: 3 hours Answer any FIVE questions All questions carry equal marks ***** 1 (a) What are the basic fault model in digital systems? How they are diagonized? (b) Write a brief note on cube based operations. Apply CAMP II algorithm to the following 5 variable function and obtain the minimized function. F( A,B,C,D,E) = (a) Draw the table giving the set of all possible single struck faults and the faulty-free responses and also construct the fault cover table for circuit in figure. Max. Marks: 70

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(b) Explain “compact” algorithm used in PLA folding. 4 Apply D-algorithm to detect h SAO fault in the given circuit and derive the test vectors. A B f C X h

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(a) Draw the general structure of a CPLD and explain how a logic function can be realized on CPLD with simple example. (b) How does the ASM chart differ from a software flow chart. Write a short note on: (a) Design for testability. (b) Field programmable gate arrays. (a) Apply PLA maximization procedure and obtain the minimized expression to be implemented on PLA. F = 2021 + 0022 +1200. (b) Obtain the minimum test vector set for the above function F in 7(a). What is testing? Explain briefly test generation and testable PLA design. *****

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